Abstract: An adhesive film for semiconductor assembly includes a binder portion 1, a sub-binder portion, and a cured portion, wherein the binder portion 1 and the sub-binder portion co-exist in a co-continuous phase structure after curing begins.

Abstract: A leadframe design for forming leadframe-based semiconductor packages having curvilinear shapes is disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts.

Abstract: A semiconductor chip package having a molding layer is provided. The semiconductor chip package includes a semiconductor chip, a plurality of external connection terminals, and the molding layer. The semiconductor chip comprises a backside surface, side surfaces, and an active surface having a plurality of chip pads disposed thereon. The molding layer substantially covers the backside surface, the side surfaces, and the active surface of the semiconductor chip and defines at least one opening exposing a portion of the backside surface of the semiconductor chip. A multi-chip package including the semiconductor chip package and a method of manufacturing the semiconductor chip package are also provided.

Abstract: A power semiconductor module is disclosed including a housing for receiving at least one essentially board-type circuit carrier, the circuit carrier being provided with a metallization on at least one part of its surface and being populated with and electrically connected to at least one power semiconductor, rigid, integral and essentially straight load connection elements being applied on the metallized part of the metallized surface of the circuit carrier, which load connection elements are electrically and mechanically fixedly connected to the circuit carrier by one of their ends and project essentially perpendicularly into the housing interior, separate connection terminal elements for electrical conduct-making being placed onto the free end of the load connection elements.

Abstract: The invention provides semiconductor material (e.g., gallium nitride material) devices (e.g., transistors) and methods associated with the same. The devices may be supported within a package that is formed, in part, of a polymeric material. In other embodiments, the devices may be mounted to a support (e.g., circuit board) and a polymeric material may encapsulate a portion of the device extending from the support.

Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.

Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.

Abstract: A semiconductor device comprises: a semiconductor chip; a first frame; a solder layer which bonds the solder bonding metal layer of the semiconductor chip and the first frame; and a second frame bonded to the rear face of the semiconductor chip. The semiconductor chip includes: a semiconductor substrate; a first metal layer provided on a major surface of the semiconductor substrate and forming a Schottky junction with the semiconductor substrate; a second metal layer provided on the first metal layer and primarily composed of aluminum; a third metal layer provided on the second metal layer and primarily composed of molybdenum or titanium; and a solder bonding metal layer provided on the third metal layer and including at least a fourth metal layer which is primarily composed of nickel, ion or cobalt.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.

Abstract: An exemplary Electromagnetic Interference (EMI) shielding package (1) includes a substrate (10), a metal cap (15), and a potting compound (18). The substrate has a plurality of electronic components (11a, 11b, 12) fixed thereon. The metal cap includes a horizontal base panel (152) and a plurality of peripheral walls (151) vertical to the base panel. A related method for making the EMI shielding package includes: providing a substrate with a plurality of electronic components fixed thereon; providing a metal cap including a horizontal base panel and a plurality of peripheral walls vertical to the base panel; attaching the walls to the substrate, thereby covering selected one or more of the electronic components that need to be shielded with the metal cap; sealing the electronic components and the metal cap with a potting compound; and curing the potting compound to form an encapsulation.

Abstract: An IC device includes a base plate, a plurality of terminal pins, a functional component such as an IC chip, and a resin package for protection of the functional component. The base plate is generally flat and formed with a plurality of through-holes into which the terminal pins are inserted. The functional component, disposed away from the base plate, is mounted on a printed circuit board to be electrically connected to at least one of the terminal pins. While enclosing the functional component, the resin package is held in contact with the upper surface of the base plate.

Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.

Abstract: A power converter unit has a metal case; a power module having a plurality of power semiconductor devices that is provided inside the metal case; a gate drive circuit board having a circuit for driving the plurality of the power semiconductor devices that is mounted on the power module; a voltage sensor that is mounted on the gate drive circuit board; a metal plate for electrically connecting the metal case with the gate drive circuit board; screws and soldered parts for fixing the metal plate to the gate drive circuit board; a first wiring that is set up on the gate drive circuit board for electrically connecting the voltage sensor with the soldered parts; and a second wiring that is set up on the gate drive circuit board for electrically connecting the screws and the soldered parts.

Abstract: An RF-coupled digital isolator includes a first leadframe portion and a second leadframe portion, electrically isolated from one another. The first leadframe portion includes a first main body and a first finger. The second leadframe portion includes a second main body and a second finger. The first main body is connected to a first ground, and the second main body is connected to a second ground that is electrically isolated from the first ground. The first finger and the second finger are electrically isolated from one another, e.g., by a plastic molding compound that forms a package for the digital isolator. The first finger acts as a primary of a transformer, and the second finger acts as a secondary of a transformer, when an RF signal drives to the first finger. The first finger and the second finger can be substantially parallel or anti-parallel to one another.

Abstract: Provided is a wiring substrate, a semiconductor device package including the wiring substrate, and methods of fabricating the same. The semiconductor device package may include a wiring substrate which may include a base film. The base film may include a mounting region and a non-mounting region. The wiring substrate may further include first wiring patterns on the non-mounting region and extending into the mounting region, second wiring patterns on the first wiring patterns of the non-mounting region, and an insulating layer on the non-mounting region, and a semiconductor device which may include bonding pads. At least one of side surfaces of the second wiring patterns adjacent to the mounting region may be electrically connected to at least one of the bonding pads of the semiconductor device.

Abstract: A semiconductor device 10 includes a first transistor 11 placed on a substrate 16, a second transistor 12 placed on the first transistor 11 via a heat radiation layer 17, a third transistor 13 placed on the substrate 16, and a fourth transistor 14 placed on the third transistor 11 via a heat radiation layer 17. The first transistor 11 has a first region corresponding to a region where the second transistor is placed, and a second region which is formed so as to surround the first region and in which the rate of area occupied by the emitter region in the base region is higher than in the first region. Likewise the first transistor 11, the third transistor 13 has a region in which the rate of area occupied by the emitter region in the base region is varied.

Abstract: A chip package structure including a carrier, a chip, and an underfill layer is disclosed. The carrier has a number of bumps disposed thereon. The chip has an active surface. The chip is flip-chip bonded and electrically connected to the carrier through the bumps such that the active surface of the chip faces the carrier. The underfill layer is disposed on the carrier between the chip and the carrier such that a gap is maintained between the underfill layer and the chip.

Abstract: A practical bonding technique is provided for solid-phase room-temperature bonding which does not require a profile irregularity of the order of several nanometers, in which a high-vacuum energy wave treatment and continuous high-vacuum bonding are not required. Since an adhering substance layer is thin immediately after a surface activating treatment using an energy wave, a bonding interface is spread by crushing the adhering substance layer to perform bonding, so that a new surface appears on a bonding surface, and objects to be bonded are bonded together. In order to crush the adhering substance layer more easily, a bonding metal of a bonding portion of the object to be bonded needs to have a low hardness. According to the results of various experiments conducted by the present inventors, it was found that the hardness of the bonding portion which is a Vickers hardness of 200 Hv or less is particularly effective for room-temperature bonding.

Abstract: A method of producing a MEMS device removes the bottom side of a device wafer after its movable structure is formed. To that end, the method provides the device wafer, which has an initial bottom side. Next, the method forms the movable structure on the device wafer, and then removes substantially the entire initial bottom side of the device wafer. Removal of the entire initial bottom side effectively forms a final bottom side.

Abstract: An arrangement for the equipping of electronic packages with elliptical C4 connects possessing optimal orientation for enhanced reliability. Furthermore, disclosed is a method providing elliptical C4 connects which possesses optimal orientation for enhanced reliability, as implemented in connection with their installation in electronic packages. Employed are essentially elliptical solder pads or elliptical C4 pad configurations at various preferably corner locations on a semiconductor chip.

Abstract: This invention provides a method for fabricating a semiconductor device and a carrier applied therein. The method includes the steps of: disposing a chip-mounted substrate in an opening of a carrier; forming at least a storage aperture and at least an inspection aperture in the carrier; infusing an adhesive into the storage aperture to fill a gap between the substrate and carrier with the adhesive by capillarity; determining whether the inspection aperture is filled with the adhesive to ascertain whether the gap is completely filled with the adhesive; in response to a positive result, performing a molding process to form a molding compound for encapsulating the chip; and performing implantation of solder ball and a singulation process to form a semiconductor device with desirable dimensions.

Abstract: A process for assembling two parts of an integrated electronic circuit has two successive steps. During a first step, the two circuit parts are made into a single unit by molecular bonding, realized on respective application surfaces of the two parts. During a second step, electrical connections are formed from connection portions already present in the application surfaces of the two circuit parts. The connections formed extend across the bonding interface, and are compatible with a high reliability and a high level of integration of the circuit.

Abstract: The invention under consideration refers to a circuit arrangement for a switch-mode power supply, wherein the switch-mode power supply has a primary side, which can be connected to a supply voltage, and a secondary side, which can be connected to a consumer, and wherein the circuit arrangement comprises a primary-sided switch, a control circuit for controlling the primary-sided switch and additional active primary-sided components. Furthermore, the invention under consideration also refers to a switch-mode power supply with an active primary-sided circuit arrangement of that type.

Abstract: A three-dimensional architecture chip includes a base chip including a unit integrated thereon and configured to perform electrical signal operations. An active layer is separately fabricated from the base layer. The active layer includes a component to service the unit of the base chip. The active layer is bonded to the base chip such that the component is aligned in vertical proximity of the unit. An electrical connection connects the unit to the component through vertical layers of at least one of the base chip and the active layer.

Abstract: A nano-scale compliant mechanism includes a coupler and a plurality of nanotubes disposed for nano-scale motion relative to a grounded component. The nanotubes are fastened at one end to the coupler and at the other end to ground, to guide motion of the coupler relative to the ground. Particular embodiments include a plurality of parallel carbon nanotubes. An exemplary embodiment exhibits first and second regions of mechanical behavior; a first region governed by bulk elastic deformation of the nanotubes and a second region governed by compliant, hinge-like bending of the buckled nanotubes.

Abstract: An electronic multi-component package is assembled by placing multiple electronic components within multiple openings of a package substrate, then depositing and curing adhesive filler in gaps between the components and the inner peripheries of the openings. Circuit features, including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces of the package substrate. Preformed conductive vias through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components may be attached to conductive lands on at least one side of the package. The circuit features also include contact pads for external package connections, such as in a ball-grid-array or equivalent structure.

Abstract: An integrated circuit includes a buck converter controller, a PFET, an NFET that is coupled in common drain configuration to the PFET, a first microbump that is connected to the source of the PFET, a second microbump that is connected to the source of the NFET, a third microbump that is connected to the common drain node, a fourth microbump that is connected to a feedback input lead of the controller, and a plurality of other microbumps. The other microbumps are utilized to supply signals to and/or to conduct signals from the controller. A respective one of the four microbumps is disposed to occupy a respective one of the four corners of a square pattern. The other microbumps are disposed in a regular grid along with the four microbumps, but none of the other microbumps is disposed between any two of the four microbumps.

Abstract: A power semiconductor module having a carrier plate, on which at least four substrates are arranged, and having a first and a second busbar having two conductive plates is disclosed. The conductive plates are arranged such that they are at a distance from one another and are insulated from one another, for respectively carrying a lower and an upper electrical potential, said busbars each being fitted with outer connecting lugs which lead away from the substrates and inner connecting lugs on the substrate side. Symmetrization of the current during dynamic commutation operations is achieved by correctly selecting the order of the outer connecting lugs of the respective first busbar for a lower potential and of the second busbar for an upper potential in accordance with the order of the inner connecting points of the parallel-connected half-bridge circuits and also of the inner connecting lugs of the first busbar and of the second busbar.

Abstract: An improved LED positioning structure includes a retaining holder and a cover; multiple slots being disposed on one side of the retaining holder; a slope externally extending beneath each slot gradually and externally extending a slope; a hole connecting through each slot being formed on the bottom of the slope; a positioning channel at the top of the retaining holder for LED pins to respectively penetrate each hole, thus each pin being placed in a slot; a bent part of each pin being formed by the curvature located between the slot and the positioning channel to position the LED mask in the positioning channel; and the cover being positioned at top of the slot to secure the LED in place.

Abstract: This invention discloses an EMI shielding module installed on the circuit board with at least one connection hole. This EMI shielding module includes a shielding case and at least one protrusion. The shielding case capped on the device is arranged on the circuit board. The protrusion is arranged on the shielding case and inserted in the connection hole. Therefore, the shielding case is grounded by connecting it to the circuit board with the protrusion inserted in the connection hole.

Abstract: A light source module includes a ceramic circuit board having a predetermined conductive pattern, a semiconductor light emitting element arranged on said ceramic circuit board and connected to the conductive pattern, and an attachment for power feeding bonded to the ceramic circuit board. The attachment for power feeding is provided with a power feeding part connected to an external power source, a plate-shaped part adjacent to a position opposed to an outer circumferential surface of the ceramic circuit board, and a power feeding terminal formed in plate shape and protruded from the plate-shaped part to a side of the ceramic circuit board. The top of the power feeding terminal is connected to a part of the conductive pattern with the top overlapped from a thickness direction. The power feeding terminal of the attachment for power feeding is fixed and connected to the conductive pattern of the ceramic circuit board.

Abstract: A group of bus bars, forming a power circuit, are adhesively bonded to a surface of a control circuit board. Surface-mounting type relay switches are used as a switching unit for the power circuit. Contact-side terminals of each relay switch are mounted on the bus bar group while coil-side terminals thereof are mounted on the control circuit board. The opening and closing of relay contacts are controlled by a control circuit incorporated in the control circuit board.

Abstract: A component mounting circuit board includes a circuit pattern including a plurality of electrically conductive plates, an inner electrical component electrically connected to the circuit pattern, and a resin molded section made of a resin by way of molding so as to cover the circuit pattern and the inner electrical component. The resin molded section has an opening allowing an outer electrical component located outside the resin molded section to be connected to the circuit pattern through it.

Abstract: When a silicone gel is injected into a case, since the gel is liquid before curing, the gel attempts to rise along a minute gap formed between a front face of a first electrode and a rear face of a resin member due to capillary action. However, since the gap becomes larger at a cavity in the first electrode, the rising motion of the gel stops at the level of the cavity. More specifically, the gel is prevented from reaching portions of the first electrode and a second electrode for connection with external terminals. Further, since the rising motion of the gel can be prevented by the cavity, the first electrode and the second electrode can be arranged in a close relationship with each other.

Abstract: Disclosed is a method and structure for locally powering a semiconductor chip within a package. The structure and method incorporate a local voltage regulator mounted adjacent a semiconductor chip on a top surface of a carrier. The voltage regulator is electrically connected to a power plane disposed within the carrier. The voltage regulator continuously senses the reflected voltage of the power plane at a regulated output port and actively cancels time domain noise within its operational bandwidth. Mounting the voltage regulator on top of the carrier adjacent to the chip minimizes loop inductance between the regulator and power plane and also minimizes delay caused by impedance of the power plane on the current flowing to the chip.

Abstract: An electronic device has a plastic housing. The plastic housing has components of a height-structured metallic leadframe. The components are in a matrix form and contain contact islands and chip islands on the underside of the plastic housing. Furthermore, the electronic device has a first line structure containing height-structured interconnects on the underside of the plastic housing and a second line structure containing bonding connections which are disposed within the plastic housing.

Abstract: A semiconductor device is disclosed that performs fingerprint recognition on the electrostatic-capacity principle. A finger sweeping across a fingerprint recognition area of a semiconductor chip provides positive fingerprint recognition operations with improved reliability. The semiconductor device includes the semiconductor chip having a sensor unit that performs fingerprint recognition, and a substrate having an opening formed in the position corresponding to the sensor unit. The semiconductor chip is flip chip bonded to the substrate such that the sensor unit corresponds to the opening, and except for the formed position of the opening, an under-fill material is provided between the semiconductor chip and the substrate.

Abstract: First and second chips each having a transistor are provided. The first chips are arranged along a first axis on a first metallic body in side-by-side and interspaced manner. The second chips are arranged parallel to the first axis on a second metallic body in a side-by-side and interspaced manner. The second chips are arranged perpendicular to the first axis opposite an area of the first body and are each connected to the opposite area via at least one bonding connection. The first chips, with regard to the third axis, are arranged opposite an area of the second body, which is located between adjacent second chips. A third metallic body is arranged on the second body and comprises projections each of which being arranged on one of the areas of the second body. The first chips are each connected to the opposite projection via at least one bonding connection.

Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.

Abstract: A board-shaped thermal conductor base board (3) is arranged on the bottom surface of a power module (1). Substrates (4) and (5) are arranged on the top surface of the thermal conductor base board (3), and semiconductor elements (6) and (7) are respectively arranged on the top surfaces of the substrates (4) and (5). The semiconductor elements (6, 7) are surrounded by a resinous case (2). A source electrode (13) is attached above and apart from the semiconductor elements (6, 7) by using the resinous case (2). The connection between the source electrode (13) and the sources of the semiconductor elements (7) are connected by wire bonding.

Abstract: A fully integrated wireless spread-spectrum sensor incorporating all elements of an “intelligent” sensor on a single circuit chip is capable of telemetering data to a receiver. Synchronous control of all elements of the chip provides low-cost, low-noise, and highly robust data transmission, in turn enabling the use of low-cost monolithic receivers.

Abstract: A double-sided oscillator package having an open-top oscillator housing adapted to receive electronic components and a hermetically sealed resonator housing containing a piezoelectric element is described. The electronic components and piezoelectric element are electrically connected. The respective housing can be manufactured separately and the components thereof assembled thereafter to form the package.

Abstract: A power semiconductor device comprises a power switching element having two main electrodes and one control electrode, a metal electrode connected to one of main electrodes of the power switching element, and a protection circuit for controlling an operation of the power switching element so that a main current flowing between the main electrodes of the power switching element is detected and the main current is limited when the detected main current is determined to be an overcurrent. The protection circuit detects the main current flowing through the power switching element by detecting a voltage between predetermined two points of the metal electrode.

Abstract: A center bond flip chip device carrier and a method for making and using it are described. The carrier includes a flexible substrate supporting a plurality of conductive traces. A cut out portion is formed in each trace at a position within a gap of a layer of elastomeric material provided over the traces. Each cut out portion is sized and configured to receive a solder ball for electrically connecting the carrier with a semiconductor die.

Abstract: A combination device of the IC package connection device and the main board comprises a socket and a main board. The socket has a holding assembly which is placed on the top surface of the socket. The holding assembly connects to the external IC package electrically and the socket has a plurality of solder balls. The solder balls are placed on the bottom surface of the socket and connect to the holding assembly electrically. The socket is stable on the top surface of the main board and connects to the main board electrically. The positions of a plurality of PTHs in the main board are corresponding to the plurality of solder balls. The totally melting temperature of the solder balls is higher than that in prior art in order to make the solder balls be in controllable semi-solid state in solder reflow step.

Abstract: An IC socket is provided which realizes a uniform pressure of contact with an IC package over the entire length of a row of contacts and thereby enables an appropriate evaluation of characteristics of the IC package. The IC socket mounted on a printed circuit board includes: a socket base having a large number of contacts arranged in a row and brought into contact with leads of an IC package; a cover bearing on the contacts through an elastic body; and fixing portions for securing the cover to the socket base; wherein a contact surface between the elastic body and the contacts is curved in a longitudinal direction and the curved surface is so shaped as to generate a uniform contact force between the contacts and the leads of the IC package.

Abstract: An embedding resin embeds an electronic part in an object and has a dielectric constant of about 5 or less and tan &dgr; of about 0.08 or less.

Abstract: The invention relates to a capacitor module for a converter. The capacitor module contains a capacitor which can be fastened to a base frame or to a cooling body by means of lateral, mechanical holding devices. In addition, the capacitor comprises at least one additional mechanical holding device for fastening at least one electronic terminal of the converter and of at least one measuring sensor, especially of a current transformer and/or of a voltage transformer. The inventive capacitor module makes it possible to realize a construction of a converter which is compact and has a reduced weight.

Abstract: A process for picking up and moving a microelectronic package during card assembly operations. A clipping lid having a top surface and at least two sides attaches to a substrate via friction where the sides act as leaf springs gripping the substrate. The top surface of the lid provides a clean, smooth, flat surface to which a vacuum probe may be attached. In the preferred embodiment, the lid and sides are formed from an integral piece of stainless steel. Also provided are flares at the bottom of each side to aid in guiding the lid onto the substrate. Protrusions are provided in the sides to prevent the lid from slipping too far onto the substrate and contacting the components mounted to the substrate. Also provided is at least one hole in the top surface to allow the lid to be pried free from the substrate after completion of the steps where vacuum probe movement is required.

Abstract: A method for making a build-up package of a semiconductor die and a structure formed from the same. A copper foil with conductive columns is bonded to an encapsulated die by thermal compression, between thereof there is a pre-curing dielectric film sandwiched. The dielectric film is cured to form a dielectric layer of a die build-up package and the copper foil on the dielectric layer is etched to form the conductive traces. At least one conductive column in one of the dielectric layers is vertically corresponding to one of conductive column in the adjacent dielectric layer.