Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.

Abstract: An assembly for mounting a plurality of electrical components having terminals with leads onto a surface of a printed circuit board is disclosed. The assembly includes a substantially planar configured electrically insulated body member having top to bottom surfaces. Cavities extend through the body member and are dimensioned for receiving an electrical component and holding the component laterally by the walls defining the cavity. An elastomer element with conductive portions is positioned adjacent to the bottom surface of the cavities and receives the leads of electrical components. A lid is connected to the body member and movable from an open position for allowing insertion and removal of electrical components to and from the cavities, and a closed position where the lid covers the cavities.

Abstract: A device and method for interconnection packages in a stack. Each package encapsulates, for example a semiconductor chip containing an integrated circuit, which for example may be a memory. The packages (2) which have connecting pins (21) are mounted on support grid (4) which preferably act as a heat shunt, and are stacked and linked to each other with a resin coating (5). A stack (3) is cut out so that the pins on the packages and one edge of the grids are flush with faces (31, 32) of the stack (3). Connections between the packages themselves, and between the packages and stack connecting pads, are made on the faces of the stack. The connecting pads are where necessary fitted with connecting pins.

Abstract: A double-sided oscillator package (200) is provided. The package (200) has an open-top receptacle (212) adapted to receive an electronic component and an open-bottom receptacle (214) adapted to receive at least a piezoelectric element and a cover, forming a hermetic environment. The electronic component (226) and piezoelectric element (234), can be suitably connected to the package (200). The package (200) is designed to be mass-producable, and is compact, easily surface mounted and provides a narrow profile.

Abstract: A plurality of memory modules are stacked so as to form a multilayer integrated memory circuit. All of the memory modules have a plurality of bare memory IC chips mounted thereon, and have the same structure, the same circuit configuration and the same terminal arrangement in lead frames with each other. Each of the memory modules to be stacked in each layer is rotated by 90.degree., 180.degree. or 270.degree. before being stacked and connected to each other. Thus, in the multi-layered memory circuit, it is possible that signals can be selectively input/output to/from a particular layer in the multilayer structure, although the lead terminals of each of memory modules has the same configuration and the same arrangement with each other. As a result, a small-size integrated memory circuit device with a large memory-capacity can be provided, which can be fabricated easily and efficiently. A higher processing speed of digital computers can be also achieved.

Abstract: Trays having the same size are piled up by fitting a downward extending edge frame formed on the whole periphery of the undersurface of each tray on the outer wall of the upward extending outer peripheral frame formed on the outer wall of the lower tray. The tray has multiple rectangular pockets defined by longitudinal and crosswise partition portions formed in a space defined by the inner wall of the outer peripheral frame. An upward projecting base is formed in the central portion of each pocket, for supporting the undersurface of a semiconductor device. Downward extending ribs are formed on the undersurface of each tray. Each rib surrounds upper side portions of the semiconductor device housed in the corresponding pocket of the lower tray and fitted on the inner wall of the inner wall of the lower tray. A first horizontal space D.sub.1 is defined between the outer peripheral frame and the edge frame, and a second horizontal space D.sub.

Abstract: An integrated electro-optical package including a semiconductor chip with a large array of light emitting devices formed thereon and cooperating to generate a complete real image. The light emitting devices are positioned in rows and columns and connected to pads adjacent outer edges of the chip. A window frame substrate having a central opening therethrough coextensive with the real image generated by the chip and mounting pads, bump bonded to the pads on the chip. A plurality of driver circuits connected to the light emitting devices through terminals on the window frame substrate. A lens mounted to the substrate over the opening and on a side opposite the chip to magnify the real image and produce an easily viewable virtual image.

Abstract: Multichip integrated circuit packages and systems of multichip packages having reduced interconnecting lead lengths are disclosed. The multichip package includes a multiplicity of semiconductor chip layers laminated together in a unitized module. A first metallization pattern is connected to the integrated circuit chips on at least one side surface of the unitized module. In addition, at least one end surface of the module contains a second metallization pattern which is configured to facilitate connection of the package to an external signal source, such as another multichip package. The system includes at least two such packages which are electrically coupled via either metallization patterns provided on the end surface of the packagers. If required, a plurality of multichip packages can be directly coupled into the system in an analogous manner. Further specific details of the multichip package and the system of multichip packages are set forth herein.

Abstract: TCP (tape carrier package) type semiconductor memory elements, each having a thickness less than that of the conventional package, are provided on the front and rear surface of a print circuit board in a stacking manner. Close to the semiconductor memory elements stacked, provided are TCP type semiconductor memory elements stacked one on another. Each TCP type semiconductor memory element has outer leads on its one side surface. The outer leads having the same function are arranged in a straight line on the front or rear surface of the print substrate. The outer leads arranged in the straight line are connected with each other via a straight wiring pattern.

Abstract: An electrical module assembly (100) includes a mounting frame (130) having a passage (135) extending though the mounting frame (130). A heat sink (160) is positioned within the passage (135) of the mounting frame (130). A module substrate (120) is located on or near the heat sink (160) such that there is thermal conductivity between the module substrate (120) and the heat sink (160). A heat-generating semiconductor device (122), such as a power amplifier (122), which requires heat dissipation, is positioned on the module substrate (120) such that there is thermal conductivity between the heat-generating semiconductor device and the heat sink (160). Electrical connection to the module substrate (120) is provided through the mounting frame (130).

Abstract: A master-slice type semiconductor chip in the form of a PGA package has a plurality of external pins arranged in a plurality of rows. The external pins of at least the outermost row are electrically connected to an input cell on the semiconductor chip, while the external pins of at least the innermost row is connected to an input/output cell provided on the semiconductor chip. With this arrangement, the wires in the package connected to the input/output cell can have smaller lengths than the wires connected to the input cell, so that crosstalk noises produced by output signals can be reduced.

Abstract: A semiconductor package is described which has external connection points (pins, pads, etc.) which may be configured from outside of the package. In one embodiment, this is accomplished with programming holes which pass through and form contact surfaces with various conductors within the package. Conductive material is then deposited into selected holes, forming connections between all of the contact surfaces in any hole. In another embodiment, configurability is accomplished via conductive pads disposed on the exterior surface of the package. Conductive jumpers are then used to connect selected pads. An auxiliary externally effected power plane and bus-bar structure are also described.

Abstract: A ceramic package for a memory semiconductor accommodates therein the memory semiconductor and is sealingly closed by an ultraviolet ray transmissible ceramic lid. The ceramic lid is made of a polycrystalline alumina and formed with at least one groove in a sealing portion with the ceramic package. With the arrangement, the ceramic package is superior in sealing strength, air-tightness and ultraviolet ray transmission and can easily accommodate any increase of memory amount of semiconductor elements.

Abstract: The package (10) of the integrated circuit (11) includes a TAB carrier (12), the supply conductors (15b) of which comprise shielding elements between groups of signal conductors and have a length that is largely shunted via a corresponding potential conductor plane (26b) of the decoupling device (24) of the package.

Abstract: Wells are formed in an external surface of a semiconductor device package body. Capacitors are disposed within the wells at least partially, and preferably fully within the body. Cleaning channels are formed underneath the capacitors, for removing residual flux and/or solder.