For Semiconductor Device Patents (Class 361/820)
  • Publication number: 20030137814
    Abstract: Embodiments of the present invention provide an electronic device. The electronic device includes a circuit board. A first circuit is disposed on a first side of the circuit board. The first circuit is connected to a first ground plane of the circuit board. A second circuit is disposed on a second side of the circuit board. The second side is opposite the first side, and the second circuit is connected to a second ground plane of the circuit board. Moreover, the first and second ground planes respectively lie in different planes of the circuit board and are electrically interconnected by a conductive trace disposed within the circuit board.
    Type: Application
    Filed: January 24, 2002
    Publication date: July 24, 2003
    Applicant: ADC DSL Systems, Inc.
    Inventor: Janusz M. Kucharski
  • Patent number: 6597585
    Abstract: A power semiconductor module includes a plastic housing, a plurality of connection elements for external main connections and control connections, and at least one ceramic substrate which is provided at least on its top side with a structured metalization. The at least one ceramic substrate is fitted with semiconductor components and is inserted into a bottom opening of the plastic housing. The connection elements for the external main connections and control connections are connected by detaching a part of the structured metalization from the at least one ceramic substrate and bending it vertically upward to form a grip tab so that the grip tab can be connected to a connection element through the use of a brazed joint or a welded joint. These measures ensure an excellent stability with regard to fluctuating thermal loads.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: July 22, 2003
    Assignee: Eupec Europaeische Gesellschaft fuer Leistungshalbleiter GmbH & Co. KG
    Inventors: Gottfried Ferber, Reimund Pelmer
  • Patent number: 6571468
    Abstract: A method for forming a fine-pitch flip chip assembly interconnects fine pitch devices after they have been connected to a carrier substrate. A die having a plurality of conductive sections, such as solder balls, is attached to a conductive layer of the substrate. An interconnect pattern is then formed in the conductive layer to connect the conductive sections and generate electronic functionality to the assembly. By forming the interconnect pattern after the device have been connected to the carrier, the invention provides precise alignment between the devices and the interconnect pattern without actually aligning the two components during the assembly process.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: June 3, 2003
    Assignee: Saturn Electronics & Engineering, Inc.
    Inventors: Timothy Patterson, John Burke
  • Patent number: 6562643
    Abstract: A LED packaging process is to place LED chips at predetermined positions on the printed circuit board substrate, followed by drilling holes to penetrate the substrate, followed by passing the printed circuit board through the solder furnace to completely fill the through-hole position with solder points, followed by using molds to make the soldering points into a groove reflector, followed by placing LED chips in the groove reflector, followed by wire bonding and using encapsulation resin for packaging to form SMD LED with reflectors. In the present invention, the filling with metal conductor in electrode through holes on the printed circuit board to form the groove reflector can enhance the heat dissipation of LED and the brightness of LED, which has the advantageous effects that traditional SMD LED can not have.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: May 13, 2003
    Assignee: Solidlite Corporation
    Inventor: Hsing Chen
  • Patent number: 6563203
    Abstract: In a motor driving device, an IC chip of a drive circuit for driving a motor is die-bonded to one island of a leadframe, and a diode chip of a protection diode for preventing the drive circuit from being destroyed when supplied power is connected to the IC chip with reverse polarities is die-bonded to another island of the leadframe. The supplied-power pad of the IC chip is wire-bonded to the second island, which serves as the cathode electrode of the diode chip.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: May 13, 2003
    Assignee: Rohm Co., Ltd.
    Inventor: Kazuhiko Nishimura
  • Patent number: 6557675
    Abstract: The present invention relates to a method and apparatus that minimizes shock/vibrational motion in interposer sockets. The ability to control shock/vibration can ensure successful operation and substantially increase socket lifetime. The present invention discloses a device for maintaining a heat sink in a desired relationship to a mounting base while limiting the transmission of shock and vibrational motion to and from the heat sink includes a fastener extending from the mounting base, a spring compressed between the fastener and the heat sink, and a damper compressed between the fastener and the sink wherein the fastener maintains the spring and the damper in a compressed state such that the spring and the damper bear on said heat sink.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: May 6, 2003
    Assignee: Compaq Information Technologies Group, L.P.
    Inventor: Raymond J. Iannuzzelli
  • Patent number: 6549425
    Abstract: An electronic apparatus has a casing, electrically insulating separating plates arranged in the casing, electronic components arranged in proximity to the separating plate, and a securing member. The separating plate has latch regions each having a top and latch grooves below the top. The securing member is snap-fitted on the latch region and has a pawl engaged with the latch grooves and a securing portion to secure the upper edge of the electronic component. The separating plate electrically insulates one electronic component from another electronic component. The latch regions have different heights.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: April 15, 2003
    Assignee: Fujitsu Limited
    Inventor: Naofumi Kosugi
  • Patent number: 6532157
    Abstract: A novel semiconductor package comprises a rigid dielectric, e.g., ceramic, substrate having first and second portions joined to one another at respective margins thereof to form an angle, e.g., a right angle, between the portions. Each of the portions has electrically conductive paths connected to one another through the angle. A semiconductor device, e.g., a die, is mounted to the first portion and electrically connected to the conductive paths thereof. An array of electrically conductive lands, balls, or pins are mounted on the second portion for connecting the package to a printed circuit board. In a high-power embodiment, the device is mounted directly on a threaded stud projecting from the first portion to enable intimate thermal coupling of the device to a heat sink. In another embodiment, a connector projects from the first portion to optically couple an optical device directly to an end of a fiber optic cable.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: March 11, 2003
    Assignee: Amkor Technology, Inc.
    Inventors: Thomas P. Glenn, Roy D. Hollaway, Steven Webster
  • Patent number: 6521989
    Abstract: An electronic package and/or package lid includes at least one connection slot for receiving a line, such as an optical fiber. The package and/or package lid also includes at least one sealant slot proximate the connection slot. Optical fibers are connected to a component, such as an opto-electronic component, through the connection slot. A sealant provided via the sealant slot hermetically seals the optical fibers within the connection slot.
    Type: Grant
    Filed: October 8, 1998
    Date of Patent: February 18, 2003
    Assignee: Honeywell Inc.
    Inventor: Ping Zhou
  • Publication number: 20030024735
    Abstract: A protective device for subassemblies having a substrate and at least one component to be protected which is disposed on the substrate includes at least one covering element for covering a subassembly. An expanded filler material fills at least one given space between the substrate and the covering element and provides protection against mechanical compression. A method of producing a protective device is also provided. An expandable material is applied to the substrate and is expanded after the covering element has been mounted.
    Type: Application
    Filed: August 1, 2002
    Publication date: February 6, 2003
    Inventors: Volker Strutz, Uta Gebauer
  • Publication number: 20030025193
    Abstract: Provided is a method of manufacturing a semiconductor laser device capable of reducing time required for manufacture and preventing deterioration in performance due to heating, and a mounting plate and a supporting plate which are used in the method of manufacturing a semiconductor laser device. A semiconductor laser device is formed by stacking a laser chip, a sub-mount and a heat sink and adhering them to each other. The laser chip has a structure such that a p-side electrode and an n-side electrode are formed on the same surface of the crystalline substrate. The sub-mount has a structure such that a front face solder film and a back face solder film are formed on front and back surfaces of a supporting body, respectively. When the laser chip, the sub-mount and the heat sink are stacked, the front face solder film is positioned between the laser chip and the sub-mount and the back face solder film is positioned between the sub-mount and the heat sink.
    Type: Application
    Filed: September 30, 2002
    Publication date: February 6, 2003
    Inventor: Masafumi Ozawa
  • Publication number: 20030026083
    Abstract: A tray for semiconductors having a tray portion, a rail portion, and an intermediate portion. The tray portion has a plurality of chip recesses formed therein. The rail portion extends substantially around the tray portion. The intermediate portion interconnects the tray portion and the rail portion and is oriented at an angle of more than 115° with respect to the rail portion.
    Type: Application
    Filed: July 12, 2002
    Publication date: February 6, 2003
    Applicant: Entegris, Inc.
    Inventors: Joy Duban-Hu, James Nigg
  • Patent number: 6512680
    Abstract: In a semiconductor package which contains an IC element therein and effects the inputting and outputting of a signal to the IC element through a plurality of pads, a group of signals is layout-patterned so as to be divided into a plurality of groups such as a group of signals weak against noise, a group of signals liable to discharge noise and a group of signals exchanging a heavy current and so that the groups may be isolated from one another.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: January 28, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshihito Harada, Katsunori Nakamura
  • Patent number: 6507268
    Abstract: A low profile mount for a disc varistor. A thermally sensitive switch is provided both for single and multiple electrode embodiments. The switch may be placed in a shorting circuit and include a spring biased conductor prevented from closure by a heat sensitive element which softens in responsive to excessive heat. The varistor may be fused to prevent excessive current from a short circuited but not open circuited varistor. Methods are also provided.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: January 14, 2003
    Assignee: Littlefuse, Inc.
    Inventor: Neil McLoughlin
  • Patent number: 6490166
    Abstract: The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: December 3, 2002
    Assignee: Intel Corporation
    Inventors: Suresh Ramalingam, Nagesh Vodrahalli, Michael J. Costello, Mun Leong Loke, Ravi V. Mahajan
  • Publication number: 20020141171
    Abstract: An apparatus, comprising: a die having a surface, comprising: an array of electrically conductive bumps; and a plurality of electrically conductive bars positioned within the array of electrically conductive bumps.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 3, 2002
    Inventor: Mark T. Bohr
  • Patent number: 6456168
    Abstract: A dual-cavity temperature compensated crystal oscillator (100) provides a three-layer ceramic package (110), with a crystal (170) sealed in a well or cavity (148). Oscillator components (180-184) such as a compensation circuit and an oscillator are attached through screened solder onto the back side of the ceramic package (110) and are encapsulated within potting compound or encapsulant. Electrical connection is provided between the oscillator and compensation circuitry and the piezoelectric element (170) to produce a frequency-controlled oscillator. After frequency tuning, a hermetic seal is provided between a cover (160) and ledge (140) to hermetically seal the cavity (148).
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: September 24, 2002
    Assignee: CTS Corporation
    Inventor: Marlin Luff
  • Patent number: 6456240
    Abstract: A switch modulated low duty cycle low energy mass limited radio frequency beacon system for locating spent, un-exploded or experimental munitions projectiles in a large open-air test range or within a dirt backstop. The disclosed locator beacon is mounted on a rear portion of a projectile before launch and includes a protective (and antenna length-shortening) resin dielectric material housing in which locator beacon circuit components are contained and immunized against high G forces by a combination of component supporting, energy deflecting and energy absorbing protective arrangements.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: September 24, 2002
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: John L. Cesulka
  • Patent number: 6434008
    Abstract: A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements being
    Type: Grant
    Filed: August 27, 1998
    Date of Patent: August 13, 2002
    Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.
    Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
  • Publication number: 20020097567
    Abstract: A desk that contains an integrated computer. The desk includes a screen and a keyboard that are attached to a frame. The desk may also have a backplane located in a slot of the frame. A portable transporter computer can be plugged into the backplane to couple the transporter with the screen and keyboard. A battery module may also be plugged into the frame to power the transporter, screen and keyboard. When the desk is not in use the battery module can be plugged into a charging station to recharge the batteries of the module.
    Type: Application
    Filed: November 29, 2001
    Publication date: July 25, 2002
    Inventors: Richard Zodnik, Rick Goerner, Charles Pelly
  • Patent number: 6421254
    Abstract: A multi-chip module includes a housing having insulative side walls and an end plate, conductive leads extending from the side walls, integrated circuit (IC) dies mounted to the end plate, and one or more interconnect dies mounted to the end plate. The end plate is made from a heat sink material, such as copper. Each interconnect die is positioned between a pair of the IC dies. Electrically conductive material connects the IC dies to the interconnect die, connects the IC dies to the conductive leads, and connects the interconnect dies to the conductive leads. The interconnect dies function to interconnect the IC dies and to interconnect the IC dies to the conductive leads. The interconnect die may be embodied by wiring layers formed on a silicon substrate.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: July 16, 2002
    Assignee: Silicon Bandwidth Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Yun Li, Moises Behar, Dan Fuoco, Bill Ahearn
  • Patent number: 6414852
    Abstract: A semiconductor integrated circuit comprising a functional block 500 which includes macrocells 510 to 513. A macrocell 510 is connected to four input-output terminals 530 to 533 on four sides of an outline of the functional block 500 via a multi-layer wiring 580. Another functional block to be connected to this macrocell 510 is placed in any position upward, downward, left, or right of the functional block 500, whereas one input terminal located closest to the other functional block is selected as an effective terminal among four input-output terminals 530 to 533. Two of the functional blocks are connected only via this effective terminal. The other input-output terminals remain as dummy terminals. It is possible to reduce detouring routing among functional blocks by providing the semiconductor integrated circuit with the functional block 500 having such a configuration.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: July 2, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Masao Mizuno
  • Patent number: 6404644
    Abstract: A non-contact IC card (1, 2, 30, 50) includes a substrate (10), a coil (12, 32, 52, 57) provided on substrate (10), and an IC chip (11, 31, 51) electrically connected to a coil (12, 32, 52, 57) and having a main surface (11c, 31c, 51e). IC chip has a terminal (11a, 11b, 31a, 31b, 51a, 51b, 51c, 51d) formed in main surface (11c, 31c, 51e). Coil (12, 32, 52, 57) has a coil inner end (12b, 32b, 52b, 57b) electrically connected to a terminal (11b, 31b, 51b, 51d) and a coil outer end (12a, 32a, 52a, 57a) electrically connected to a terminal (11a, 31a, 51a, 57c). IC chip (11, 31, 51) is provided above coil (12, 32, 52, 57) such that coil inner end (12b, 32b, 52b, 57b) is positioned in vicinity of terminal (11b, 31b, 51b, 51d) and coil outer end (12a, 32a, 52a, 57a) is positioned in vicinity of terminal (11a, 31a, 51a, 51c).
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: June 11, 2002
    Assignee: Rohm Co., Ltd.
    Inventors: Yoshihiro Ikefuji, Hiroharu Okada
  • Patent number: 6388888
    Abstract: A semiconductor device comprising a patterned wiring including a connector for external connection formed on an elongate base film, a semiconductor element or the semiconductor element and a component other than the semiconductor element mounted on and electrically connected with a portion for connection of the patterned wiring, an elongate reinforcement member provided on a surface of the base film opposite to a surface on which the patterned wiring is formed, the reinforcement member having sprocket holes at positions corresponding to the lengthwise sides of the base film, wherein the reinforcement member is further provided on said opposite base film surface in a region corresponding with a region on which the connector for external connection is formed.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: May 14, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiharu Seko, Kenji Toyosawa
  • Publication number: 20020051353
    Abstract: A high-frequency ceramic package 10 comprises a ceramic frame plate 12 brazed to a jointed metal plate 11 on the surface thereof, the jointed metal plate 11 including a substantially rectangular shaped first metal plate 17 which has a hollowed portion 19 at a central portion thereof and a second metal plate 18 which is fitted in the hollowed portion 19 in a state in which the first and second metal plate 17, 18 are jointed together in end-to-end relationship. The first metal 17 is close to the ceramic frame plate in thermal expansion coefficient, and the second metal plate 18 is made from a material having a high level of heat-sinking characteristics. A concave cavity 16 defined between the second metal plate 18 and the ceramic frame plate 12 has a semiconductor electronic component mounting portion on a bottom 16a of the cavity 16.
    Type: Application
    Filed: May 1, 2001
    Publication date: May 2, 2002
    Applicant: Sumitomo Metal (SMI) Electronics Devices Inc.
    Inventor: Akiyoshi Osakada
  • Patent number: 6377468
    Abstract: Circuit elements of surface-mounting type such as MOSFETs etc. are mounted on a circuit board by soldering. The circuit board is retained slantingly by a base so that any one of the MOSFET falls out by its self-weight when the solder melts due to an abnormal heat generation of the MOSFET. The falling of the MOSFET is stopped by a stopper member, and then the MOSFET becomes in an electrically open state and retained at the stopped position in consequence of the subsequent cooling of the solder. Accordingly, even if one or more of the MOSFETs cause the abnormal heat generation, the continuous heat generation of the MOSFET is stopped and also the other circuit elements are prevented from being short-circuited.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: April 23, 2002
    Assignees: ANDEN Co., Ltd., DENSO Corporation
    Inventors: Hideyuki Ohtani, Fukuo Ishikawa, Hideki Kabune, Hiroshi Hattori
  • Patent number: 6377466
    Abstract: A header containing a semiconductor die, method of manufacture thereof and electronic device employing the same. In one embodiment, the header includes first and second contacts, and an intermediate body. The intermediate body includes an insulated section interposed between the first and second contacts and has a cavity therein. The intermediate body also includes a semiconductor die, located within the cavity, adapted to condition a signal passing through at least a portion of the header.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: April 23, 2002
    Assignee: Lucent Technologies Inc.
    Inventors: Shiaw-Jong Steve Chen, Roger J. Hooey
  • Patent number: 6373273
    Abstract: An insert is provided for testing a chip-scale-packaged microelectronic device having an encapsulant-protrusion and a ball-grid-array of outwardly-projecting contacts. The insert comprises a substrate of mono-crystalline silicon. Walls of the substrate define a plurality of pockets that are configured to receive and contact the outwardly-projecting contacts of the microelectronic device. Additional walls of the substrate define a recess disposed amongst the plurality of pockets. The recess has a width greater than the widths of any of the pockets. Additionally, the recess comprises a perimeter greater than that of the encapsulant-protrusion of the chip-scale-packaged microelectronic device, and a depth operative to clear the encapsulant-protrusion when the chip-scale package is seated upon the insert.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: April 16, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, David R. Hembree
  • Patent number: 6369324
    Abstract: In a conventional high-frequency input/output feedthrough having a microstrip line, for a millimeter wave band, the reliability of a hermetic seal portion was low and transmission characteristics in the millimeter wave band were not preferable.
    Type: Grant
    Filed: August 27, 1998
    Date of Patent: April 9, 2002
    Assignee: Kyocera Corporation
    Inventor: Satoru Tomie
  • Patent number: 6366468
    Abstract: Precision alignment of one or more parts on a common carrier is described. A self-aligned common carrier includes a carrier substrate having one or more pockets formed in the substrate. Each pocket includes a side profile formed in the pocket. A chip having an identical side profile that complements the side profile in the pocket is mounted to the carrier substrate by inserting the chip into the pocket. The complementary side profiles result in near perfect self-alignment between the chip and at least two orthogonal planes of the carrier substrate. The chip and the carrier substrate can be made from a single crystal semiconductor material and the side profiles can be formed by anisotropic etch process that selectively etches the chip and the substrate along a predetermined crystalline plane. The chip and the carrier substrate can be single crystal silicon having a (100) crystalline orientation and the side profiles can be formed by selectively etching the silicon along a (111) crystalline plane.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: April 2, 2002
    Assignee: Hewlett-Packard Company
    Inventor: Alfred I-Tsung Pan
  • Patent number: 6351027
    Abstract: A chip mounted enclosure (“CME”) comprises a base formed by an integrated circuit chip, a transducer element disposed on the integrated circuit chip, a side piece surrounding the transducer element that is coupled to the base, and a top piece coupled to the side piece. A method of making a CME comprises mounting a transducer element to a planar surface of an integrated circuit chip, where the planar surface forms a base of the CME. A side piece is fabricated to surround the transducer element. A top piece of the CME is placed on the side piece. Individual CMEs can be fabricated from a wafer assembly, where transducer elements, each respectively mounted to an integrated circuit wafer having corresponding integrated circuit chips, are individually surrounded by a side piece structure that is bonded to the integrated circuit wafer. Individual CMEs are formed by singulating the wafer assembly.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: February 26, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Kirk S. Giboney, Jonathan Simon
  • Patent number: 6350630
    Abstract: A sensor assembly is formed by attaching a micromechanical semiconductor sensor in a housing. The micro-mechanical sensor is secured to the housing by a gel, which leads to a particularly favorable isolation between the micromechanical sensor and the housing.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: February 26, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventor: Andreas Wildgen
  • Patent number: 6344976
    Abstract: An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least some of the leads are constructed to extend across the front-side surface of the die from one edge substantially to another edge, such as an adjacent or opposing edge. As a result, a substantial area of the front-side surface of the die is adhesively attachable to the leads through the tape, so the die is supportable in an IC package in an improved manner, and the heat may be conducted away from the die through the lead frame in an improved manner.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: February 5, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Aaron Schoenfeld, Jerry M. Brooks
  • Publication number: 20020005574
    Abstract: An electronic package and/or package lid includes at least one connection slot for receiving a line, such as an optical fiber. The package and/or package lid also includes at least one sealant slot proximate the connection slot. Optical fibers are connected to a component, such as an opto-electronic component, through the connection slot. A sealant provided via the sealant slot hermetically seals the optical fibers within the connection slot.
    Type: Application
    Filed: October 8, 1998
    Publication date: January 17, 2002
    Inventor: PING ZHOU
  • Patent number: 6335669
    Abstract: An RF circuit module comprising a first RF semiconductor device 19 mounted within a cavity 4 surrounded by a wall 3 of a first dielectric circuit board 1, and a second RF semiconductor device 29 mounted to a second dielectric circuit board 2 placed on the wall 3. A metal base 11 is disposed on the first circuit board 1 and a number of embedded conductors 13 such as via holes are embedded within the wall 3 and arranged to surround the cavity 4 so that each having one end electrically connected to the metal base 11 and the other end exposed and arranged to surround the cavity 4. A metal cover 12 is sealingly attached to the first circuit board 1 to cover the second circuit board 2 and the second RF semiconductor device 29 and electrically connected at the upper surface of the wall 3. Therefore, the first and second RF semiconductor devices are electrically shielded and hermetically sealed, providing an RF circuit module of small-sized and high-performance.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: January 1, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Moriyasu Miyazaki, Hidenori Yukawa, Hideyuki Oh-Hashi, Masatoshi Nii
  • Patent number: 6313999
    Abstract: An apparatus which aligns a ball grid array (BGA) device over a substrate. The apparatus preferably includes a cup-shaped member for cupping and holding the solder balls of the BGA device, and an elongate member attached to the cup-shaped member. The cup-shaped member is attached between the BGA device and the substrate at two or more different positions so that the solder balls of the BGA device become aligned over the terminals of the substrate by operation of gravity.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: November 6, 2001
    Assignee: Agere Systems Optoelectronics Guardian Corp.
    Inventors: Roger Anthony Fratti, John Wayne Bowen, Dwight David Daugherty, Xiaohong Jiang
  • Patent number: 6310792
    Abstract: A component module includes a processor and at least a portion of a voltage regulator module which regulates voltages being supplied to said processor.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: October 30, 2001
    Assignee: Intel Corporation
    Inventor: Josef Drobnik
  • Patent number: 6307755
    Abstract: A leadframe for making an electric connection to a semiconductor die contains a plurality of notches which correspond to the edges of the die. Shorts are thereby prevented between the leadframe and electrical elements near the edge of the die, even when the leadframe is bent in the direction of the die to make a surface mount package. Alternatively or additionally, the leads in the leadframe may contain moats which prevent the epoxy or solder used to attach the leadframe to a die from spreading outward and thereby creating electrical shorts with other leads.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: October 23, 2001
    Inventors: Richard K. Williams, Allen K. Lam, Alexander K. Choi
  • Patent number: 6281695
    Abstract: An integrated circuit package pin indicator that may include probe guides. The indicator includes a top marking plate with indicia for the multiple pins of the IC package. The top plate has individual indicia for each pin, and will have numerical or alpha labels for some or all of the pins, depending on the number of pins present. The top marking plate may include a securing means to attach the top marking plate to the top of the IC package and to hold the top marking plate in place. Each pin marker terminates in a hole or slot that is adapted to guide a probe to a selected pin. The pin indicator can be used with both through hole and surface mount IC boards.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: August 28, 2001
    Inventors: Robbie M. K. Chung, Elynna M. C. Chung
  • Patent number: 6278618
    Abstract: A variety of improved substrate structures and substrate fabrication techniques for use in integrated circuit packaging are described. In one aspect, a substrate strip fabrication technique that facilitates strip testing of the dice mounted thereon is described. The described technique works well even when landings on the substrate are electrolytically plated. In a preferred embodiment, the substrate is formed in a manner that facilitates the use of non-stick detection during wire bonding. In a distinct aspect of the invention the substrate strip has a plurality of distinct molding area tiles that each have a two dimensional array of substrate segments formed thereon. The substrate segments each have a die attach area, a plurality of landing one surface and a plurality of contact pads on the other. The contact pads are positioned substantially across from the landings and are electrically connected thereto by associated vias.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: August 21, 2001
    Assignee: National Semiconductor Corporation
    Inventors: Shaw Wei Lee, Anindya Poddar, Ram Veeraraghavan, Thanh Lequang
  • Patent number: 6252777
    Abstract: An IC card, which can be mass-produced at low cost, is composed of a plane coil formed by means of punching or etching.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: June 26, 2001
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takashi Ikeda, Masatoshi Akagawa, Daisuke Ito
  • Publication number: 20010004397
    Abstract: The invention is intended to provide a body wearable type music reproducing device having excellent portability by which a user is able to use the reproducing device without hindering the user's action even during sport, the reproducing device enabling the user to acquire desired music data rapidly and easily and to reproduce a piece of music based on the acquired music data, and also to provide a music reproducing system comprising such music reproducing device. The music reproducing device is worn on a user's body by a band attached thereto. In this state, a piece of music is reproduced based on corresponding music data stored in a memory one of the music reproducing device and the band.
    Type: Application
    Filed: December 18, 2000
    Publication date: June 21, 2001
    Inventors: Kazunori Kita, Akira Nakazawa, Satomi Michitsuta
  • Patent number: 6249440
    Abstract: The contact arrangement is a connector block for detachably fastening an electrical component, particularly an integrated circuit having a plurality of terminal contacts disposed in a ball grid array (BGA), in a column grid array (CGA), in a land grid array (LGA) or of the flip-chip type to a printed circuit board. In a support part, a number of contact pins are disposed in a grid in bores. The contact pins project from the bore on the side facing the printed circuit board and are surface-mounted together with contact areas of the printed circuit board. A free end region of each bore is intended for guiding the substantially dome-shaped terminal contacts. Between the end of a contact pin and a terminal contact there is a space bridged for establishing an electrical connection with a contact element, for example an axially compressible coil spring. By means of several holding-down elements disposed peripherally to the integrated circuit, the integrated circuit is pressed down upon the support part.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: June 19, 2001
    Assignee: E-TEC AG
    Inventor: Hugo Affolter
  • Patent number: 6239987
    Abstract: First and second thermoplastic case parts house a surge protector semiconductor subassembly having a plurality of components. The first and second thermoplastic case parts are substantially identical, and each case part has a semiconductor subassembly receiving recess therein. The first and second thermoplastic case parts have corresponding projections and recesses so that the first and second thermoplastic case parts may be snapped together to form a hollow case encapsulating the semiconductor subassembly. The hollow case includes spring means integral with the hollow case for applying force on the semiconductor subassembly to retain the components of the semiconductor subassembly together in the event that the case is subjected to high temperature due to a high current surge.
    Type: Grant
    Filed: March 28, 1994
    Date of Patent: May 29, 2001
    Assignee: General Semiconductor, Inc.
    Inventors: Richard Sheng-Tong Shyr, Enrico F. Napoletano, Marie Guillot
  • Patent number: 6229404
    Abstract: A crystal oscillator in which IC control terminal electrodes for writing temperature compensation data in an IC chip are formed on side surfaces of a main body while being distanced from the top and bottom surfaces of the main body. The IC control terminal electrodes will not be short-circuited with a conductive pattern for sealing the crystal oscillating element on the top surface, and the IC chip will not be destroyed by a welding current which flows when a metal cover is mounted on the top surface. The IC control terminal electrodes will not be short-circuited with other wiring conductors during the soldering to bond the crystal oscillator to a printed circuit board. The compensation data or other data written in the IC chip can be stably maintained, thereby securing a stable operation.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: May 8, 2001
    Assignee: Kyocera Corporation
    Inventor: Hidefumi Hatanaka
  • Patent number: 6219254
    Abstract: The chip-to-board (or chip-to-MCM) connection assembly and method therefor features a semiconductor chip (31) having a front surface (31f) on which external terminal pads are provided; a board or MCM (32) having a surface (e.g., a recessed surface) at a first side thereof to which the rear surface (31r) of the chip is affixed; and a connection carrier (33), disposed as an overlay, which electrically links the chip and the board or MCM. In this assembly scheme, the connection carrier (e.g., a bump carrier) which is affixed to both the chip and the board or MCM, contains all required signal line tracings (57) to provide the electrical interconnection between the semiconductor chip and the board or MCM. The bump carrier replaces all bond wires (24) and the like and can include support/control circuitry, passive and/or active, associated with, for example, high-speed/high-power IC chips (51).
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: April 17, 2001
    Assignee: TRW Inc.
    Inventors: Gershon Akerling, James M. Anderson, John W. Spargo, Benjamin Tang
  • Patent number: 6191955
    Abstract: An electronic module comprises (a) an electrical assembly of electrical components and a cap. The cap surrounds a portion of the electrical assembly of electrical components to form a pocket between a portion of the electrical assembly of electrical components and the cap. The cap has at least one sidewall, each of the at least one sidewalls having an end, one of at least one sidewalls proximately positioned to at least one electrical lead and having at least one notch positioned in the end, the pocket filled with an encapsulant. A process comprises providing a cap and filling the cap with encapsulant, placing an electrical assembly of electrical components in the cap filled with the preselected amount of encapsulant, and allowing the electrical assembly to seat to a proper depth.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: February 20, 2001
    Assignee: Dallas Semiconductor Corporation
    Inventors: Joe Guillot, Michael Quan Dinh, Bill Roberts, Linda M. McLemore
  • Patent number: 6184576
    Abstract: A packaging and interconnection for connecting a contact structure to an outer peripheral component with a short signal pass length to achieve a high frequency operation. The packaging and interconnection is formed of a contact structure made of conductive material and formed on a contact substrate through a photolithography process, a contact trace formed on the contact substrate and electrically connected to the contact structure at one end, and the other end of the contact trace is extended toward an edge of the contact substrate, a connection target provided at an outer periphery of the contact structure to be electrically connected with the other end of the contact trace, an elastomer provided under the contact substrate for allowing flexibility in the interconnection and packaging of the contact structure, and a support structure provided between for supporting the contact structure, the contact substrate and the elastomer.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: February 6, 2001
    Assignee: Advantest Corp.
    Inventors: Mark R. Jones, Theodore A. Khoury
  • Patent number: 6150715
    Abstract: A semiconductor device of the present invention comprises a semiconductor pellet, a radiation plate mounted with the semiconductor pellet, a plurality of lead terminals electrically connected with the semiconductor pellet, and a resin member for encapsulating the above items. The resin member has a first surface and a second surface, and the radiation plate has a first portion exposed to the outside from the first surface of the resin member and a second portion exposed to the outside from the second surface of the resin member.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: November 21, 2000
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Takeshi Umemoto, Kazunari Sato, Kunihiko Tsubota, Yoshikazu Nishimura, Toshiaki Nishibe, Kazuhiro Tahara, Masato Suga, Toru Kitakoga, Tatsuya Miya, Keita Okahira
  • Patent number: 6144560
    Abstract: A semiconductor device including bond pads disposed proximate an edge thereof, and an overcoat layer. The overcoat layer defines notches around each of the bond pads. The overcoat layer may be formed from a photoimageable material such as a photoimageable epoxy. The invention also includes an alignment device that secures the semiconductor device perpendicularly upon a carrier substrate. The alignment device includes intermediate conductive elements which correspond to the bond pads of the semiconductor device. Upon insertion of the semiconductor device into the alignment device, the notches facilitate alignment of the bond pads with their corresponding intermediate conductive elements. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: November 7, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Walter L. Moden, Larry D. Kinsman