Semiconductive Patents (Class 365/103)
  • Patent number: 10883953
    Abstract: Described examples include a sensor device having at least one conductive elongated first pillar positioned on a central pad of a first conductor layer over a semiconductor substrate, the first pillar extending in a first direction normal to a plane of a surface of the first conductor layer. Conductive elongated second pillars are positioned in normal orientation on a second conductor layer over the semiconductor substrate, the conductive elongated second pillars at locations coincident to via openings in the first conductor layer. The second conductor layer is parallel to and spaced from the first conductor layer by at least an insulator layer, the conductive elongated second pillars extending in the first direction through a respective one of the via openings. The at least one conductive elongated first pillar is spaced from surrounding conductive elongated second pillars by gaps.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: January 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Enis Tuncer, Vikas Gupta
  • Patent number: 10831220
    Abstract: A voltage regulator circuit using precharge voltage rails is generally disclosed. For example, the voltage regulator circuit may include a first voltage regulator having a voltage output, an output capacitor coupled to the voltage output, and one or more precharge voltage circuits configured to selectively couple to the voltage output, each of the one or more precharge voltage circuits comprising a capacitor coupled between an output of a precharge voltage regulator and a reference potential.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: November 10, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Chris Rosolowski, Todd Sutton, Orlando Santiago, Joseph Duncan
  • Patent number: 10777255
    Abstract: Provided is a control signal generator for a sense amplifier, the control signal generator including a replica circuit including replica transistors corresponding to transistors included in the sense amplifier, and configured to receive at least one input signal of the sense amplifier and a first control signal for enabling a sensing operation by the sense amplifier; and an amplifying circuit configured to output, by amplifying an output signal from the replica circuit, a second control signal for enabling an amplifying operation by the sense amplifier after the sensing operation is enabled.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: September 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Artur Antonyan, Hyun-taek Jung
  • Patent number: 10706946
    Abstract: Provided is a one-time programmable (OTP) memory device, which includes a data input circuit that receives a supply voltage and applies the supply voltage to one of a plurality of bit lines that is selected by a write switch, and an OTP memory cell array including a plurality of OTP memory cells arranged in a plurality of rows and columns. The OTP memory cells on the same row connected to the same bit line. The OTP memory device also includes a column decoder that selects one of the plurality of columns of the OTP memory cells to apply the supply voltage thereto, and a detection amplifier that performs a read operation of the OTP memory cells connected to one of the plurality of bit lines that is selected by a read switch.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: July 7, 2020
    Assignee: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventor: Duk Ju Jeong
  • Patent number: 10685728
    Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: June 16, 2020
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Zhe Wong, Ching-Sung Yang, Ching-Hsiang Hsu
  • Patent number: 10468248
    Abstract: In various embodiments, a method is provided. The method may include forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer, and forming a second layer above the first layer using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: November 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Heiko Aßmann, Felix Braun, Marcus Dankelmann, Stefan Doering, Karsten Friedrich, Udo Goetschkes, Andreas Greiner, Ralf Rudolf, Jens Schneider
  • Patent number: 10447275
    Abstract: Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Andy L. Lee, Richard G. Smolen, Rusli Kurniawan, Jeffrey T. Watt, Christopher J. Pass, Yue-Song He
  • Patent number: 10355128
    Abstract: A semiconductor device is disclosed that includes a substrate and at least a first, second, third, and fourth vertical transistor supported by the substrate. Each transistor comprises a vertical channel, a polarity gate electrode forming a polarity gate adapted to act on a first portion of the channel to affect a polarity of the channel, and a control gate electrode forming a control gate adapted to act on a second portion of the channel to control the electrical conductivity of the channel. The polarity gate electrode and the control gate electrode of each one of the transistors extend laterally from their respective gate and in mutually opposite directions, and the transistors are laterally spaced from each other and arranged such that the control gate electrodes of the first and third transistor face each other and the control gate electrodes of the second and fourth transistor face each other.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: July 16, 2019
    Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D
    Inventors: Praveen Raghavan, Odysseas Zografos
  • Patent number: 10276494
    Abstract: Memory cells and corresponding memory arrays are provided. The memory cell comprises a fusable element and a bipolar transistor arranged adjacent to the fusable element.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 30, 2019
    Assignee: Infineon Technologies AG
    Inventors: Kerstin Kaemmer, Martin Bartels, Henning Feick
  • Patent number: 9812393
    Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: November 7, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey P. Jacob, Suraj K. Patil, Min-hwa Chi
  • Patent number: 9773792
    Abstract: A one-time programming cell includes a first metal oxide semiconductor (MOS) structure and a second transistor having a common gate electrode electrically connected to a word line. The first MOS structure has a first gate dielectric layer and the second MOS structure has a second gate dielectric layer. The second gate dielectric layer is thicker than the first gate dielectric layer. Source nodes of the first MOS structure and the second MOS structure are electrically connected, and a drain node of the second MOS structure is electrically connected to a bit line.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9767857
    Abstract: Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Gerald John Barkley, Daniele Vimercati, Pierguido Garofalo
  • Patent number: 9614007
    Abstract: Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: April 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Mattia Boniardi, Andrea Redaelli
  • Patent number: 9589663
    Abstract: A one-time programmable (OTP) memory capable of performing a multi-programming and a semiconductor memory device including the OTP memory are disclosed. The OTP memory includes a plurality of fuse cells in which two or more fuse cells are programmed at a time. In a program mode, in response to determining that a current flowing through each of the fuse cells increases to a predetermined value, the OTP memory blocks the current flowing through each of the fuse cells.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: March 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Minyeol Ha
  • Patent number: 9202588
    Abstract: Disclosed is a ROM memory device including a plurality of rows and columns of memory cells, each memory cell including a bit line pair and a transistor to store two bits of data therein, and a virtual ground line disposed between adjacent pairs of bit line pairs, wherein the bit line pair and virtual ground line are used to read data stored in the memory cells.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: December 1, 2015
    Assignee: NXP B.V.
    Inventors: Rajat Kohli, Patrick Van de steeg, Jwalant Mishra, Pankaj Agarwal
  • Patent number: 9082469
    Abstract: A semiconductor chip D1 of a flash memory which is stacked together with other semiconductor chips D2˜DN to form a multi-chip package (MCP), including a memory cell array 20 of the flash memory for storing an ID code and an upper address, wherein the ID code is written into the a fuse data region 20F of the memory cell array 20 before the assembly process. According to the invention, ID codes and upper addresses can be assigned and written to each of the semiconductor chips of a multi-chip package easily without increasing the size of the semiconductor chips in comparison with the prior art.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 14, 2015
    Assignee: Powerchip Technology Corp.
    Inventors: Akira Ogawa, Yoshichika Nakaya
  • Patent number: 9058887
    Abstract: The present invention provides a reprogrammable electrically blowable fuse and associated design structure. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Louis C. Hsu, Conal E. Murray, Chandrasekhar Narayan, Chih-Chao Yang
  • Patent number: 8995164
    Abstract: A two-bit read-only-memory (ROM) cell and method of sensing its data state. Each ROM cell in an array includes a single n-channel metal-oxide-semiconductor (MOS) transistor with a source biased to a reference voltage, and its drain connected by a contact or via to one or none of first, second, and third bit lines associated with its column in the array. Each row in the array is associated with a word line serving as the transistor gates for the cells in that row. In response to a column address, a column select circuit selects one pair of the three bit lines to be applied to a sense line in wired-NOR fashion for sensing.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 31, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Michael Patrick Clinton
  • Publication number: 20150078061
    Abstract: A semiconductor memory device includes a non-volatile device array of once rewritable non-volatile devices arranged in a matrix. The device includes a plurality of non-volatile device sub-arrays formed by dividing the non-volatile device array; a power interconnect contact region provided between at least one of pairs of the plurality of non-volatile device sub-arrays, and connected to a power interconnect provided at an upper layer of the non-volatile device array; and an ESD protection circuit located in the power interconnect contact region between ground and a power source for the non-volatile devices.
    Type: Application
    Filed: November 21, 2014
    Publication date: March 19, 2015
    Inventors: Masanori SHIRAHAMA, Toshiaki KAWASAKI, Kazuhiro TAKEMURA, Yasuhiro AGATA
  • Patent number: 8964444
    Abstract: A one-time programmable memory includes a first one-time programmable memory cell including a fuse core having an input terminal for receiving a trim signal, an output terminal for providing a sense signal, and a fuse. The fuse core conducts current through the fuse in response to the trim signal. The one-time programmable memory cell also includes a sense circuit having an input terminal coupled to the output terminal of the fuse core, and an output terminal for providing a termination signal, and a logic circuit having a first input terminal for receiving a program enable signal, a second input terminal for receiving a data signal, a third input terminal coupled to the output terminal of the sense circuit for receiving the termination signal, and an output terminal coupled to the input terminal of the fuse core for providing the trim signal.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jefferson W. Hall, Josef Halamik, Pavel Londak
  • Patent number: 8916938
    Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: December 23, 2014
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 8885384
    Abstract: The present invention discloses a mask-ROM with reserved space (mask-ROMRS). For small content revision, the present invention salvages the original data-mask by writing the data-pattern of new content into a reserved mask-region which originally has no data-pattern.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: November 11, 2014
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Publication number: 20140268985
    Abstract: A Read Only Memory (ROM) bitline cell apparatus and programming method therefore. The programming methodology ensures a ROM structure having open state and/or breaks in the diffusion and/or dummy wordline rows to provide bitline load balancing. The ROM bitline cell apparatus and programming method exhibits improved load balancing for any combination of 1's or all 0's on the bitline. The programming methodology identifies groups of consecutive ‘1’s on the bitline and instead of connecting the ‘1’ devices between BL/BL or GND/GND, those ‘1’ devices can be connected between BL/OPEN, OPEN/BL, GND/OPEN, OPEN/GND or OPEN/OPEN. With little or no variation in bitline loading, timing can be optimized for that single case of bitline loading.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 18, 2014
    Applicant: International Business Machines Corporation
    Inventors: Rahul K. Nadkarni, Daniel R. Baratta, Konark Patel, Hoan H. Nguyen
  • Publication number: 20140268986
    Abstract: An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number of encoded bitlines, e.g., 2, 4, 8, 16, and so on. Each of the first plurality and second sets of bit lines are coupled to circuits for charging and discharging the bitlines. To read data from the first set of bit lines, the second set of bitlines is discharged, and vice versa.
    Type: Application
    Filed: March 27, 2013
    Publication date: September 18, 2014
    Inventors: Narayana Rao VEDULA, Dechang Sun, Myron Buer
  • Patent number: 8837192
    Abstract: Among other things, an n-bit ROM cell, such as a twin-bit ROM cell, and techniques for addressing one or more ROM cell portions of the n-bit ROM cell are provided. A twin-bit ROM cell comprises a first ROM cell portion adjacent to or substantially contiguous with a second ROM cell portion. The first ROM cell portion is associated with a first data bit value. The second ROM cell portion is associated with a second data bit value distinct from the first data bit value. Because the first ROM cell portion is adjacent to the second ROM cell portion, OD-to-OD spacing between the twin-bit ROM cell and an adjacent twin-bit ROM cell is increased to provide, for example, improved isolation, cell current, ROM speed, and VCCmin performance in comparison with single-bit ROM cells, while maintaining a substantially similar to pitch as the single-bit ROM cells.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Wei Wu, Kuang Ting Chen, Cheng Hung Lee
  • Patent number: 8797782
    Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer, second and third semiconductor layers, a dielectric film and a conductive film, a first electrode, a second electrode, and a third electrode, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, the filament being formed by causing a dielectric breakdown of at least a part of the dielectric film, through application of a voltage equal to or higher than a predetermined threshold between the second and third electrodes, thereby causing an electric current to flow between the conductive film and the third semiconductor layer.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 5, 2014
    Assignee: Sony Corporation
    Inventors: Shigeru Kanematsu, Yuki Yanagisawa, Matsuo Iwasaki
  • Publication number: 20140140121
    Abstract: A two-bit read-only-memory (ROM) cell and method of sensing its data state. Each ROM cell in an array includes a single n-channel metal-oxide-semiconductor (MOS) transistor with a source biased to a reference voltage, and its drain connected by a contact or via to one or none of first, second, and third bit lines associated with its column in the array. Each row in the array is associated with a word line serving as the transistor gates for the cells in that row. In response to a column address, a column select circuit selects one pair of the three bit lines to be applied to a sense line in wired-NOR fashion for sensing.
    Type: Application
    Filed: June 27, 2013
    Publication date: May 22, 2014
    Inventor: Michael Patrick Clinton
  • Patent number: 8729622
    Abstract: A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui-Chang Moon, Sung-Min Hwang, Woonkyung Lee
  • Patent number: 8730707
    Abstract: The programming of a read-only memory formed of MOS transistors is set by a mask for forming an insulating layer prior to the forming of contacts of active regions of the transistors. The programming of the read-only memory cannot be determined by visible inspection of the memory.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 8724364
    Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an antifuse component, a switch, and a read transistor having a control electrode. Within the nonvolatile memory cell, the switch can be coupled to the antifuse component, and the control electrode of the read transistor can be coupled to the antifuse component. The nonvolatile memory cell can be programmed by flowing current through the antifuse component and the switch and bypassing the current away the read transistor. Thus, programming can be performed without flowing current through the read transistor decreasing the likelihood of the read transistor sustaining damage during programming. Further, the antifuse component may not be connected in series with the current electrodes of the read transistor, and thus, during read operations, read current differences between programmed and unprogrammed nonvolatile memory cells can be more readily determined.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: May 13, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Moshe Agam, Thierry Coffi Herve Yao, Shizen Skip Liu
  • Publication number: 20140119093
    Abstract: Described embodiments provide a memory having at least one sense amplifier. The sense amplifier has a first capacitor, an inverting amplifier, a switch, an amplifier, and a second capacitor. The first capacitor is coupled between the input of the sense amplifier and a first node. The inverting amplifier has an input coupled to the first node and an output coupled to an internal node and the switch is coupled between the input and output of the inverting amplifier. The amplifier has an input coupled to the internal node and an output coupled to an output of the sense amplifier and the second capacitor is coupled between the internal node and a control node. When data is to be read from the memory, the second capacitor forces a small voltage reduction onto the intermediate node, helping the sense amplifier resolve the data value stored in the memory cell.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: LSI CORPORATION
    Inventors: Sahilpreet Singh, Disha Singh
  • Publication number: 20140104921
    Abstract: Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 17, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Je-Min YU, Sung-Min SEO, Ho-Young SONG, Gil-Su KIM, Jong-Min OH
  • Patent number: 8699257
    Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 15, 2014
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Publication number: 20140056051
    Abstract: A one-bit memory cell for a nonvolatile memory includes a bit line and a plurality of serially-connected storage units. The bit line is connected to the serially-connected storage units. Each storage unit includes a first doped region, a second doped region and a third doped region, which are formed in a surface of a substrate. A first gate structure is disposed over a first channel region between the first doped region and the second doped region. The first gate structure is connected to a control signal line. A second gate structure is disposed over a second channel region between the second doped region and the third doped region. The second gate structure is connected to an anti-fuse signal line.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: eMemory Technology Inc.
    Inventors: Meng-Yi Wu, Yueh-Chia Wen, Hsin-Ming Chen, Ching-Sung Yang
  • Publication number: 20140056050
    Abstract: In various embodiments, a memory cell and a memory are provided. The memory cell comprises a Static Random Access Memory (SRAM) cell including a reset-set (RS) flip-flop and a Read Only Memory (ROM) cell being connected (or coupled) to the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered. The size of the memory cells proposed in an embodiment of the invention is much smaller than the sum of the size of ROM cells and the size of SRAM cells with the capacity of the memory cells same as the sum of the capacity of the ROM cells and the capacity of the SRAM cells.
    Type: Application
    Filed: August 27, 2013
    Publication date: February 27, 2014
    Inventors: Jun YANG, Hwong-Kwo LIN, Hua CHEN, Yong LI, Ju SHEN
  • Patent number: 8659941
    Abstract: A nonvolatile memory includes a memory cell including a first transistor and a second transistor. The first transistor includes a first channel, a first gate electrode, a first source electrode, and a first drain electrode. The second transistor includes a second channel made of oxide semiconductor material, a second gate electrode, a second source electrode, and a second drain electrode. One of the second source electrode and the second drain electrode is electrically connected to the first gate electrode. Data writing in the memory cell is done by raising the potential of a node between one of the second source electrode and the second drain electrode and the first gate electrode. Data erasure in the memory cell is done by irradiating the second channel with ultraviolet light and lowering the potential of the node.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: February 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Kamata, Yusuke Sekine
  • Patent number: 8611129
    Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type, which are disposed to be separated from each other in the first semiconductor layer, a first electrode electrically connected to the second semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, through application of a voltage equal to or higher than a predetermined threshold between the first electrode and the second electrode.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: December 17, 2013
    Assignee: Sony Corporation
    Inventors: Shigeru Kanematsu, Yuki Yanagisawa, Matsuo Iwasaki
  • Patent number: 8582370
    Abstract: A storage unit for an occupant detection system detecting an occupant based on a magnitude correlation between a detection load value obtained by a load sensor and a threshold value, the storage unit includes a first ROM storing either one of the threshold value and a threshold value specific information for identifying the threshold value, the first ROM being rewritable and a second ROM storing information except for either one of the threshold value and the threshold value specific information, a rewriting of the second ROM being more difficult than a rewriting of the first ROM.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: November 12, 2013
    Assignee: Aisin Seiki Kabushiki Kaisha
    Inventors: Ryota Nakanishi, Chiaki Sumi, Koji Ito
  • Patent number: 8576603
    Abstract: Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by e
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: November 5, 2013
    Assignee: NXP, B.V.
    Inventors: Rob Verhaar, Guido J. M. Dormans, Maurits Storms, Roger Cuppens, Frans J. List, Robert H. Beurze
  • Patent number: 8551844
    Abstract: Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect the lower portion of the etch stop structure, and the higher portion is removed. Subsequently, at least some of the first and second insulative materials are removed. Some embodiments include semiconductor constructions having a first region with first features, and a second region with second features. The first features are closer spaced than the second features. A first insulative material is over the second region and an insulative structure is over the first insulative material. The structure has a stem joined to a bench. The bench has an upper surface, and the stem extends to above the upper surface.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: October 8, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Zengtao T. Liu
  • Publication number: 20130235644
    Abstract: In-system repairing or configuring faulty memories after being used in a system are disclosed. In one embodiment, a memory chip can include at least one OTP memory to store defective addresses that are to be repaired. Advantageously, the OTP memory can operate without requiring additional I/O pins or high voltage supplies for reading or programming. The memory chip can also include control logic to control reading or programming of the OTP memory as needed.
    Type: Application
    Filed: August 10, 2012
    Publication date: September 12, 2013
    Inventor: Shine C. Chung
  • Patent number: 8530979
    Abstract: Provided is a semiconductor package which includes: a semiconductor substrate; a functional element that is disposed on one surface of the semiconductor substrate; a protection substrate that is disposed in an opposite side of that surface of the semiconductor substrate with a predetermined gap from a surface of the semiconductor substrate; and a junction member that is disposed to surround the functional element and bonds the semiconductor substrate and the protection substrate together, wherein the functional element has a shape different from a shape of a plane surrounded by the junction member in that surface of the semiconductor substrate, or is disposed in a region deviated from a central region of the plane surrounded by the junction member in that surface of the semiconductor substrate.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: September 10, 2013
    Assignee: Fujikura Ltd.
    Inventors: Shingo Ogura, Yuki Suto
  • Publication number: 20130148404
    Abstract: In some aspects, a memory cell is provided that includes a steering element and a metal-insulator-metal (“MIM”) stack coupled in series with the steering element. The MIM stack includes a first dielectric material layer and a second dielectric material layer disposed on the first dielectric material layer, without a metal or other conductive layer disposed between the first dielectric material layer and the second dielectric material layer. Numerous other aspects are provided.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 13, 2013
    Inventors: Abhijit Bandyopadhyay, Roy E. Scheuerlein, Peter Rabkin
  • Patent number: 8427857
    Abstract: A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hung Chen, Sung-Chieh Lin, Kuoyuan Hsu, Jiann-Tseng Huang
  • Publication number: 20130063999
    Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an antifuse component, a switch, and a read transistor having a control electrode. Within the nonvolatile memory cell, the switch can be coupled to the antifuse component, and the control electrode of the read transistor can be coupled to the antifuse component. The nonvolatile memory cell can be programmed by flowing current through the antifuse component and the switch and bypassing the current away the read transistor. Thus, programming can be performed without flowing current through the read transistor decreasing the likelihood of the read transistor sustaining damage during programming. Further, the antifuse component may not be connected in series with the current electrodes of the read transistor, and thus, during read operations, read current differences between programmed and unprogrammed nonvolatile memory cells can be more readily determined.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 14, 2013
    Inventors: Moshe Agam, Thierry Coffi Herve Yao, Shizen Skip Liu
  • Patent number: 8395923
    Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: March 12, 2013
    Assignee: Intel Corporation
    Inventors: Zhanping Chen, Sarvesh H. Kulkarni, Kevin Zhang
  • Patent number: 8374016
    Abstract: An apparatus includes a bit cell of a programmable memory circuit. The bit cell includes a programmable device. The bit cell includes a first device having a first type. The first device is configured to conduct a first current between a first node and a second node in response to a first value of a signal on the word line and a signal on a bit line. The programmable device is configured to be programmed in response to a first level of the first current. The bit cell includes a circuit coupled to the second node. The circuit is configured to reduce a leakage current through the first device in response to a second value of the signal on the word line and based on a feedback signal. In at least one embodiment of the apparatus, the feedback signal is based on a signal on the bit line.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: February 12, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jeffrey A. Correll
  • Patent number: 8339832
    Abstract: A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus, it is difficult to provide a memory with few defects. It is an object of the present invention to provide a write-once memory where the probability of a defect is reduced considerably. A nonvolatile memory that can be written only once includes a redundant memory cell, a first circuit which allocates an address to the redundant memory cell, a second circuit which outputs a determination signal that expresses whether writing is performed normally or not, and a third circuit, to which the determination signal is inputted, which controls the first circuit and the second circuit.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: December 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 8339831
    Abstract: A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: December 25, 2012
    Assignee: eMemory Technology Inc.
    Inventors: Hau-Yan Lu, Ching-Sung Yang, Shih-Chen Wang, Hsin-Ming Chen
  • Patent number: 8335098
    Abstract: Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data to be stored, the memory device being built from a one time programmable (OTP) memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets selected out of the plurality of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the plurality of memory sets which remains after the memory sets of the OTP memory block are excluded and operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: December 18, 2012
    Assignee: Seiko Instruments Inc.
    Inventor: Biao Shen