Diodes Patents (Class 365/105)
  • Patent number: 10347690
    Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. One of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 9, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Shingo Nakazawa, Tsuneo Inaba, Hiroyuki Takenaka
  • Patent number: 10128312
    Abstract: There is provided a non-volatile memory device which can enhance the reliability of a memory device by using an ovonic threshold switch (OTS) selection element including a multilayer structure. The non-volatile memory device includes a first electrode and a second electrode spaced apart from each other, a selection element layer between the first electrode and the second electrode, which is closer to the second electrode rather than to the first electrode, and which includes a first chalcogenide layer, a second chalcogenide layer, and a material layer disposed between the first and second chalcogenide layers. The first chalcogenide layer including a first chalcogenide material, and the second chalcogenide layer including a second chalcogenide material. A memory layer between the first electrode and the selection element layer includes a third chalcogenide material which is different from the first and second chalcogenide materials.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Zhe Wu, Jeong Hee Park, Dong Ho Ahn, Jin Woo Lee, Hee Ju Shin, Ja Bin Lee
  • Patent number: 10109349
    Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: October 23, 2018
    Assignee: Zeno Semiconductors, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10042458
    Abstract: The present invention relates to a method comprising providing one or more information carrier(s) with a dielectric and/or conductive pattern and a detection device having a capacitive touch screen and inducing an interaction between the information carrier and the touch screen, wherein the interaction is based on a difference in the dielectric coefficient and/or the conductivity of the pattern and generates a touch signal and wherein the interaction is induced by relative motion between the information carrier and the touch screen. The invention further relates to a system comprising an information carrier comprising a dielectric and/or conductive pattern which encodes information and a detection device having a touch screen; the detection device is able to decode the information upon interaction between the information carrier and the touch screen, wherein the interaction is caused by a difference in the dielectric coefficient and/or the conductivity of the pattern.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: August 7, 2018
    Assignee: Touchpac Holdings, LLC
    Inventors: Matthias Foerster, Sascha Voigt, Jan Thiele, André Kreutzer
  • Patent number: 9818481
    Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: November 14, 2017
    Assignee: SK Hynix Inc.
    Inventors: Hae Chan Park, Myoung Sub Kim, Se Ho Lee, Seung Yun Lee
  • Patent number: 9754680
    Abstract: An electrical fuse (eFuse) array includes eFuse cells arranged in multiple rows and columns. Each eFuse cell has an eFuse, a first diode, and a second diode coupled to an internal node, each eFuse cell further having first, second, and third terminals coupled, respectively, to the first diode, the second diode, and the eFuse. The eFuse array further includes a shared NMOSFET for each of the multiple rows, with a drain coupled to the third terminal of each of the plurality of eFuse cells in that row and a gate coupled to a word line. Each column includes a write bit line coupled to the second terminal of each of the eFuse cells in that column, and a read bit line coupled to the first terminal of the eFuse cell.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: September 5, 2017
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Chia Chi Yang
  • Patent number: 9431460
    Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: August 30, 2016
    Assignee: HGST, Inc.
    Inventors: Daniel R. Shepard, Mac D. Apodaca, Thomas Michael Trent, James Juen Hsu
  • Patent number: 9312005
    Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: April 12, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Hernan A. Castro
  • Patent number: 9270269
    Abstract: Electronic memory circuits, and more particularly, low power electronic memory circuits having low manufacturing costs are disclosed. The present invention is a circuit design that utilizes two transistor types—bipolar and MOS (but, not both NMOS and PMOS) one of which can be manufactured together with the memory cell's non-linear conductive elements (such as a diode) thereby reducing the number of processing steps and masks and resulting in lower cost.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: February 23, 2016
    Assignee: HGST, Inc.
    Inventor: Daniel R. Shepard
  • Patent number: 9159411
    Abstract: A multi-level memory apparatus includes two or more current paths configured to pass currents having different levels, a memory cell selectively coupled to the two or more current paths, and a cell current copy unit configured to copy a cell current flowing through the memory cell.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: October 13, 2015
    Assignees: SK Hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Chul Hyun Park, Seung Tak Ryu, Ji Wook Kwon, Dong Hwan Jin
  • Patent number: 9036393
    Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: May 19, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen
  • Patent number: 9007805
    Abstract: A device for one-time-programmable (OTP) memory may include a capacitor formed by a conductive layer, an oxide layer, and a semiconductor well, and a diode that is formed after programing the device. The device may be programmable by applying a voltage between the conductive layer and the semiconductor well. The applied voltage may be capable of rupturing the oxide layer at one or more points. The conductive layer, the oxide layer, and the semiconductor well may be native CMOS process formations.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: April 14, 2015
    Assignee: Broadcom Corporation
    Inventors: Yong Lu, Roy Milton Carlson
  • Publication number: 20150078062
    Abstract: A device for one-time-programmable (OTP) memory may include a capacitor formed by a conductive layer, an oxide layer, and a semiconductor well, and a diode that is formed after programing the device. The device may be programmable by applying a voltage between the conductive layer and the semiconductor well. The applied voltage may be capable of rupturing the oxide layer at one or more points. The conductive layer, the oxide layer, and the semiconductor well may be native CMOS process formations.
    Type: Application
    Filed: September 30, 2013
    Publication date: March 19, 2015
    Applicant: BROADCOM CORPORATION
    Inventors: Yong LU, Roy Milton Carlson
  • Patent number: 8916938
    Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: December 23, 2014
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 8897056
    Abstract: A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 25, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
  • Patent number: 8878235
    Abstract: In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (“CNT”) material above the substrate, wherein the CNT material comprises a single CNT. Numerous other aspects are provided.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: November 4, 2014
    Assignee: SanDisk 3D LLC
    Inventors: April D. Schricker, Wu-Yi Chien, Kun Hou, Raghuveer S. Makala, Jingyan Zhang, Yibo Nian
  • Patent number: 8830768
    Abstract: A data sensing circuit includes: a current source configured to supply a reference current to an output line; a switching precharging unit configured to couple an input line with the output line during a precharge operation of the input line; and a current sinking unit configured to sink a current from the output line in response to a voltage level of the input line.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: September 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Kwang-Seok Kim
  • Patent number: 8737110
    Abstract: A circuit is provided that includes a plurality of vertically oriented p-i-n diodes. Each p-i-n diode includes a bottom heavily doped p-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: May 27, 2014
    Assignee: SanDisk 3D LLC
    Inventor: Scott Brad Herner
  • Patent number: 8724364
    Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an antifuse component, a switch, and a read transistor having a control electrode. Within the nonvolatile memory cell, the switch can be coupled to the antifuse component, and the control electrode of the read transistor can be coupled to the antifuse component. The nonvolatile memory cell can be programmed by flowing current through the antifuse component and the switch and bypassing the current away the read transistor. Thus, programming can be performed without flowing current through the read transistor decreasing the likelihood of the read transistor sustaining damage during programming. Further, the antifuse component may not be connected in series with the current electrodes of the read transistor, and thus, during read operations, read current differences between programmed and unprogrammed nonvolatile memory cells can be more readily determined.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: May 13, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Moshe Agam, Thierry Coffi Herve Yao, Shizen Skip Liu
  • Patent number: 8699257
    Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 15, 2014
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 8619465
    Abstract: An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line; inner junction diodes at shared source/drain terminals of the pass-gate and pull-down transistors oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8604521
    Abstract: An optically controlled read only memory is disclosed. The optically controlled read only memory includes a substrate, a plurality of memory cells having optical sensors disposed on the substrate, and at least one shielding structure disposed on the optical sensor, in which the shielding structure selectively shields a portion of the optical sensor according to a predetermined layout. Preferably, the optically controlled read only memory of the present invention is capable of providing two types or more program codes and outputting different program codes carrying different function under different lighting condition.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: December 10, 2013
    Assignee: United Microelectronics Corp.
    Inventor: Yi-Tyng Wu
  • Patent number: 8593850
    Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: November 26, 2013
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen
  • Patent number: 8576607
    Abstract: An integrated circuit and methods of operating same are described. In an embodiment of the integrated circuit included is an array of memory cells, where each of the memory cells includes a resistance-change storage element and a thyristor-based storage element coupled in series. In embodiments of the methods included are methods for data transfer, data tracking, and operating a memory array.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: November 5, 2013
    Inventor: Farid Nemati
  • Patent number: 8559211
    Abstract: A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Patent number: 8546898
    Abstract: An optoelectronic memory cell has a transparent top electrode, a photoactive layer, a latching layer, and a bottom electrode. The photoactive layer absorbs photons transmitted through the top electrode and generates charge carriers. During light exposure, the latching layer changes its resistance under an applied electric field in response to the generation of charge carriers in the photoactive layer.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: October 1, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Lars Thylen, Alexandre Bratkovski, Shih-Yuan Wang, R. Stanley Williams
  • Patent number: 8542517
    Abstract: An antifuse can include an insulated gate field effect transistor (“IGFET”) having an active semiconductor region including a body and first regions, i.e., at least one source region and at least one drain region separated from one another by the body. A gate may overlie the body and a body contact is electrically connected with the body. The first regions have opposite conductivity (i.e., n-type or p-type) from the body. The IGFET can be configured such that a programming current through at least one of the first regions and the body contact causes heating sufficient to drive dopant diffusion from the at least one first region into the body and cause an edge of the at least one first region to move closer to an adjacent edge of at least one other of the first regions. In such way, the programming current can permanently reduce electrical resistance by one or more orders of magnitude between the at least one first region and the at least one other first region.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: September 24, 2013
    Assignee: International Business Machines Corporation
    Inventor: Yan Zun Li
  • Patent number: 8531871
    Abstract: An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: September 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8526228
    Abstract: An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: September 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8503215
    Abstract: A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: August 6, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
  • Patent number: 8493773
    Abstract: The invention contained herein provides electrical circuits and driving methods to operate a memory cell comprising a capacitance coupled to a breakover conduction switch such as a thyristor, DIAC or one or more complementary transistor pairs. The memory cell comprises a cell capacitance for storing a memory state and for capacitively coupling an applied voltage to the switch. During operation, pulses are applied to write, read or maintain the cell's memory state. An illumination cell comprises an LED, OLED or electroluminescent material in series with each memory cell. Breakover conduction charge passes through the switch and the emissive element to charge the cell capacitance. A memory array of breakover conduction memory cells may be organized into rows and columns for reading and writing an addressable array memory cells. An organic light emitting display memory array may be fabricated using organic light emitting devices and/or materials.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: July 23, 2013
    Inventor: Robert G Marcotte
  • Patent number: 8456904
    Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: June 4, 2013
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sang T. Nguyen, Anh Ly, Hung Q. Nguyen
  • Patent number: 8427858
    Abstract: A circuit is provided that includes a plurality of vertically oriented p-i-n diodes. Each p-i-n diode is coupled to a resistivity-switching element and includes a bottom heavily doped p-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: April 23, 2013
    Assignee: SanDisk 3D LLC
    Inventor: Scott Brad Herner
  • Patent number: 8427857
    Abstract: A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hung Chen, Sung-Chieh Lin, Kuoyuan Hsu, Jiann-Tseng Huang
  • Patent number: 8422265
    Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: April 16, 2013
    Assignee: Broadcom Corporation
    Inventors: Frank Hui, Xiangdong Chen, Wei Xia
  • Publication number: 20130051113
    Abstract: A programmable non-volatile memory including a memory cell includes a transistor acting as an anti-fuse and two diodes for access. The memory cell that can store two bits and includes a transistor acting as an anti-fuse and two diodes for access, wherein the cell transistor includes: the source electrode formed by a metal; the first diode as the source region contact structure; the drain electrode formed by a metal; and the second diode as the drain region contact structure wherein the cell transistor, the oxide layer between the source area and the gate is the first anti-fuse the first storage; the oxide layer between the drain area and the gate is the second anti-fuse the second storage; the two diodes are connected in series to access the two anti-fuses.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 28, 2013
    Inventor: Euipil KWON
  • Patent number: 8363445
    Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: January 29, 2013
    Assignee: Broadcom Corporation
    Inventors: Frank Hui, Xiangdong Chen, Wei Xia
  • Patent number: 8295072
    Abstract: Non-volatile magnetic random access memory (MRAM) devices that include magnetic flip-flop structures that include a magnetization controlling structure; a first tunnel barrier structure; and a magnetization controllable structure that includes a first polarizing layer; and a first stabilizing layer, wherein the first tunnel barrier structure is between the magnetization controllable structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the first tunnel barrier structure, wherein the magnetic flip-flop device has two stable overall magnetic; configurations a second tunnel barrier structure and a reference layer, wherein the second tunnel barrier structure is between the magnetic flip-flop device and the reference layer.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: October 23, 2012
    Assignee: Seagate Technology LLC
    Inventors: Dimitar V. Dimitrov, Olle Gunnar Heinonen, Yiran Chen, Haiwen Xi, Xiaohua Lou
  • Patent number: 8289793
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, and a control circuit. The memory cell array includes plural memory cells arranged in rows and columns and each including a diode and resistance-change element. The control circuit tests the diodes for the respective memory cells. The control circuit tests the diode at least at one of times before and after one of a write operation, erase operation and read operation with respect to the memory cell is performed.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: October 16, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazushige Kanda
  • Patent number: 8238136
    Abstract: A high performance memory based computation system comprises an array of memory cells. Each memory cell stores a logic data corresponding to a chosen combination of inputs based on a specific logic function. For improved performance, the memory cell array can be divided into sub-blocks; and the sub-blocks can be serially disposed or juxtaposed. The performance of the memory based computation system can further be improved by removing the repeated memory cell rows, column, and/or sub-arrays.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: August 7, 2012
    Assignee: Toshiba America Research, Inc.
    Inventor: Bipul C. Paul
  • Patent number: 8236623
    Abstract: In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a steering element above a substrate; and (2) fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (CNT) material above the substrate. Numerous other aspects are provided.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: August 7, 2012
    Assignee: SanDisk 3D LLC
    Inventors: April Schricker, Mark Clark, Brad Herner
  • Patent number: 8208282
    Abstract: A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: June 26, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
  • Patent number: 8199552
    Abstract: A One-Time Programmable (OTP) unit cell and a nonvolatile memory device having the same are disclosed. A unit cell of a nonvolatile memory device includes: an anti-fuse connected between an output terminal and a ground voltage terminal; a first switching unit connected to the output terminal to transfer a write voltage to the output terminal; and a second switching unit connected to the output terminal to transfer a read voltage to the output terminal.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: June 12, 2012
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Chang-Hee Shin, Ki-Seok Cho, Seong-Do Jeon
  • Patent number: 8189364
    Abstract: Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, memory cells and arrays, and methods to use silicon carbide structures to retain amounts of charge indicative of a resistive state in, for example, a charge-controlled resistor of a memory cell. In some embodiments, a memory cell comprises a silicon carbide structure including a charge reservoir configured to store an amount of charge carriers constituting a charge cloud. The amount of charge carriers in the charge cloud can represent a data value. Further, the memory cell includes a resistive element in communication with the charge reservoir and is configured to provide a resistance as a function of the amount of charge carriers in the charge reservoir. The charge reservoir is configured to modulate the size of the charge cloud to change the data value.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: May 29, 2012
    Assignee: Qs Semiconductor Australia Pty Ltd.
    Inventors: Sima Dimitrijev, Herbert Barry Harrison
  • Patent number: 8134137
    Abstract: Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: March 13, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8102699
    Abstract: A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: January 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Patent number: 8089798
    Abstract: A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: January 3, 2012
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Shao-Chang Huang, Wen-hao Ching, Chun-Hung Lu, Shih-Chen Wang, Ming-Chou Ho
  • Patent number: 8085570
    Abstract: A memory includes conductive layers provided to extend along the word lines, memory cells each including a diode having a cathode connected to the conductive layer and a source line reading data stored in the memory cells, wherein either the conductive layers or the bit lines are in floating states in a standby time.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 27, 2011
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Kouichi Yamada
  • Patent number: 8085571
    Abstract: The invention shows how diodes in a modern semiconductor process can be used as a very compact switch element in a Programmable Read Only Memory (PROM) using common integrated circuit fuse elements such as polysilicon and metal. This compact switch element allows very dense PROM arrays to be realized since diodes have the highest conduction density of any semiconductor device. The high conduction density is used to provide the relatively high current needed to blow the fuse element open. Since MOSFETs are typically used as fuse array switch elements, a relatively large area is required for the MOSFET to reach the current needed to blow the fuse element. Since diodes are two terminal switch elements unlike MOSFETs which are three terminal devices, methods are outlined on how to both read and write the arrays using this two terminal switch.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: December 27, 2011
    Inventor: Eugene Robert Worley
  • Patent number: 8059444
    Abstract: A memory is provided that includes a first memory level having a plurality of memory cells. Each memory cell includes a vertically oriented p-i-n diode including a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: November 15, 2011
    Assignee: SanDisk 3D LLC
    Inventor: Scott Brad Herner