Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: This method for producing a structure wherein base materials are bonded by atomic diffusion comprises: a step for applying a liquid resin on the base material; a step for smoothing the surface of the liquid resin by surface tension; a step for forming a resin layer by curing; a step for forming a metal thin film on the resin layer; a step for forming a metal thin film on the base material; and a step for bringing the metal thin film of the base material and the metal thin film of the base material into close contact with each other, thereby bonding the metal thin film of the resin layer and the metal thin film of the base material with each other by atomic diffusion.

Abstract: In one example in accordance with the present disclosure a memristive bit cell is described. The memristive bit cell includes a memristive device switchable between states. The memristive device is to store information. The memristive bit cell also includes a first switch regulating component coupled to the memristive device. The first switch regulating component enforces compliance of the memristive device with a first property threshold when switching between states in a first direction. The first property threshold corresponds to a state of the memristive device. The memristive bit cell also includes a second switch regulating component coupled to the memristive device. The second switch regulating component enforces compliance of the memristive device with a second property threshold when switching between states in a second direction. The second property threshold corresponds to a state of the memristive device.

Abstract: A DRAM cell includes a transistor, a first diode and a second diode. The transistor has a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder. The bit line is coupled to a power supply voltage. An anode and a cathode of the first diode are coupled to a cathode and an anode of the second diode, respectively. Each of the first diode and the second diode is coupled at a first end to a source of the transistor at a first node, and at a second end to a node voltage at the second node. A DRAM device includes an address decoder and DRAM cells. A storage method for a DRAM device includes writing data into the DRAM cells and reading data from the DRAM cells.

Abstract: The present disclosure discloses a feedback field-effect array device capable of converting between volatile and non-volatile operations and an array circuit using the same. According to one embodiment of the present disclosure, the array circuit may include a plurality of feedback field-effect array devices, wherein the source region of the feedback field-effect electronic device and the drain region of an access electronic device may be connected to each other in series, the feedback field-effect electronic device may be connected to a bit line and a first word line, the access electronic device may be connected to a source line and a second word line, and any one of first and second gate voltages may be applied to the first word line to store data in a first logic state or data in a second logic state.

Abstract: A method for correcting bit defects in an STT-MRAM memory is disclosed. The method comprises executing a read before write operation in the STT-MRAM memory, wherein the STT-MRAM memory comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. The read before write operation comprises reading a codeword and mapping defective bits in the codeword. Further, the method comprises replacing the defective bits in the codeword with a corresponding redundant bit and executing a write operation with corresponding redundant bits in place of the defective bits.

Abstract: A method for correcting bit defects in a memory array is disclosed. The method comprises determining, during a characterization stage, a resistance distribution for the memory array by classifying a state of each bit-cell in the memory array, wherein the memory array comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. Further, the method comprises determining bit-cells in the resistance distribution that are ambiguous, wherein ambiguous bit-cells have ambiguous resistances between being high or low bits. Subsequently, the method comprises forcing the ambiguous bit-cells to short circuits and replacing each short-circuited ambiguous bit-cell with a corresponding redundant bit from an associated codeword.

Abstract: A method for correcting bit defects in a memory array is disclosed. The method comprises determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for all bits comprising the memory array, wherein the margin area is a bandwidth of bit-cell resistances centered around a reference point associated with a sense amplifier, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous. The method further comprises forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits. Finally, the method comprises replacing each short-circuited memory bit-cell with a corresponding redundant bit in the codeword associated with the short-circuited memory bit-cell.

Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. One of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.

Abstract: There is provided a non-volatile memory device which can enhance the reliability of a memory device by using an ovonic threshold switch (OTS) selection element including a multilayer structure. The non-volatile memory device includes a first electrode and a second electrode spaced apart from each other, a selection element layer between the first electrode and the second electrode, which is closer to the second electrode rather than to the first electrode, and which includes a first chalcogenide layer, a second chalcogenide layer, and a material layer disposed between the first and second chalcogenide layers. The first chalcogenide layer including a first chalcogenide material, and the second chalcogenide layer including a second chalcogenide material. A memory layer between the first electrode and the selection element layer includes a third chalcogenide material which is different from the first and second chalcogenide materials.

Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the

Abstract: The present invention relates to a method comprising providing one or more information carrier(s) with a dielectric and/or conductive pattern and a detection device having a capacitive touch screen and inducing an interaction between the information carrier and the touch screen, wherein the interaction is based on a difference in the dielectric coefficient and/or the conductivity of the pattern and generates a touch signal and wherein the interaction is induced by relative motion between the information carrier and the touch screen. The invention further relates to a system comprising an information carrier comprising a dielectric and/or conductive pattern which encodes information and a detection device having a touch screen; the detection device is able to decode the information upon interaction between the information carrier and the touch screen, wherein the interaction is caused by a difference in the dielectric coefficient and/or the conductivity of the pattern.

Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.

Abstract: An electrical fuse (eFuse) array includes eFuse cells arranged in multiple rows and columns. Each eFuse cell has an eFuse, a first diode, and a second diode coupled to an internal node, each eFuse cell further having first, second, and third terminals coupled, respectively, to the first diode, the second diode, and the eFuse. The eFuse array further includes a shared NMOSFET for each of the multiple rows, with a drain coupled to the third terminal of each of the plurality of eFuse cells in that row and a gate coupled to a word line. Each column includes a write bit line coupled to the second terminal of each of the eFuse cells in that column, and a read bit line coupled to the first terminal of the eFuse cell.

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.

Abstract: Electronic memory circuits, and more particularly, low power electronic memory circuits having low manufacturing costs are disclosed. The present invention is a circuit design that utilizes two transistor types—bipolar and MOS (but, not both NMOS and PMOS) one of which can be manufactured together with the memory cell's non-linear conductive elements (such as a diode) thereby reducing the number of processing steps and masks and resulting in lower cost.

Abstract: A multi-level memory apparatus includes two or more current paths configured to pass currents having different levels, a memory cell selectively coupled to the two or more current paths, and a cell current copy unit configured to copy a cell current flowing through the memory cell.

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Abstract: A device for one-time-programmable (OTP) memory may include a capacitor formed by a conductive layer, an oxide layer, and a semiconductor well, and a diode that is formed after programing the device. The device may be programmable by applying a voltage between the conductive layer and the semiconductor well. The applied voltage may be capable of rupturing the oxide layer at one or more points. The conductive layer, the oxide layer, and the semiconductor well may be native CMOS process formations.

Abstract: A device for one-time-programmable (OTP) memory may include a capacitor formed by a conductive layer, an oxide layer, and a semiconductor well, and a diode that is formed after programing the device. The device may be programmable by applying a voltage between the conductive layer and the semiconductor well. The applied voltage may be capable of rupturing the oxide layer at one or more points. The conductive layer, the oxide layer, and the semiconductor well may be native CMOS process formations.

Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.

Abstract: A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided.

Abstract: In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (“CNT”) material above the substrate, wherein the CNT material comprises a single CNT. Numerous other aspects are provided.

Abstract: A data sensing circuit includes: a current source configured to supply a reference current to an output line; a switching precharging unit configured to couple an input line with the output line during a precharge operation of the input line; and a current sinking unit configured to sink a current from the output line in response to a voltage level of the input line.

Abstract: A circuit is provided that includes a plurality of vertically oriented p-i-n diodes. Each p-i-n diode includes a bottom heavily doped p-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided.

Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an antifuse component, a switch, and a read transistor having a control electrode. Within the nonvolatile memory cell, the switch can be coupled to the antifuse component, and the control electrode of the read transistor can be coupled to the antifuse component. The nonvolatile memory cell can be programmed by flowing current through the antifuse component and the switch and bypassing the current away the read transistor. Thus, programming can be performed without flowing current through the read transistor decreasing the likelihood of the read transistor sustaining damage during programming. Further, the antifuse component may not be connected in series with the current electrodes of the read transistor, and thus, during read operations, read current differences between programmed and unprogrammed nonvolatile memory cells can be more readily determined.

Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.

Abstract: An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line; inner junction diodes at shared source/drain terminals of the pass-gate and pull-down transistors oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.

Abstract: An optically controlled read only memory is disclosed. The optically controlled read only memory includes a substrate, a plurality of memory cells having optical sensors disposed on the substrate, and at least one shielding structure disposed on the optical sensor, in which the shielding structure selectively shields a portion of the optical sensor according to a predetermined layout. Preferably, the optically controlled read only memory of the present invention is capable of providing two types or more program codes and outputting different program codes carrying different function under different lighting condition.

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Abstract: An integrated circuit and methods of operating same are described. In an embodiment of the integrated circuit included is an array of memory cells, where each of the memory cells includes a resistance-change storage element and a thyristor-based storage element coupled in series. In embodiments of the methods included are methods for data transfer, data tracking, and operating a memory array.

Abstract: A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.

Abstract: An optoelectronic memory cell has a transparent top electrode, a photoactive layer, a latching layer, and a bottom electrode. The photoactive layer absorbs photons transmitted through the top electrode and generates charge carriers. During light exposure, the latching layer changes its resistance under an applied electric field in response to the generation of charge carriers in the photoactive layer.

Abstract: An antifuse can include an insulated gate field effect transistor (“IGFET”) having an active semiconductor region including a body and first regions, i.e., at least one source region and at least one drain region separated from one another by the body. A gate may overlie the body and a body contact is electrically connected with the body. The first regions have opposite conductivity (i.e., n-type or p-type) from the body. The IGFET can be configured such that a programming current through at least one of the first regions and the body contact causes heating sufficient to drive dopant diffusion from the at least one first region into the body and cause an edge of the at least one first region to move closer to an adjacent edge of at least one other of the first regions. In such way, the programming current can permanently reduce electrical resistance by one or more orders of magnitude between the at least one first region and the at least one other first region.

Abstract: An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell.

Abstract: An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.

Abstract: A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.

Abstract: The invention contained herein provides electrical circuits and driving methods to operate a memory cell comprising a capacitance coupled to a breakover conduction switch such as a thyristor, DIAC or one or more complementary transistor pairs. The memory cell comprises a cell capacitance for storing a memory state and for capacitively coupling an applied voltage to the switch. During operation, pulses are applied to write, read or maintain the cell's memory state. An illumination cell comprises an LED, OLED or electroluminescent material in series with each memory cell. Breakover conduction charge passes through the switch and the emissive element to charge the cell capacitance. A memory array of breakover conduction memory cells may be organized into rows and columns for reading and writing an addressable array memory cells. An organic light emitting display memory array may be fabricated using organic light emitting devices and/or materials.

Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.

Abstract: A circuit is provided that includes a plurality of vertically oriented p-i-n diodes. Each p-i-n diode is coupled to a resistivity-switching element and includes a bottom heavily doped p-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided.

Abstract: A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: A programmable non-volatile memory including a memory cell includes a transistor acting as an anti-fuse and two diodes for access. The memory cell that can store two bits and includes a transistor acting as an anti-fuse and two diodes for access, wherein the cell transistor includes: the source electrode formed by a metal; the first diode as the source region contact structure; the drain electrode formed by a metal; and the second diode as the drain region contact structure wherein the cell transistor, the oxide layer between the source area and the gate is the first anti-fuse the first storage; the oxide layer between the drain area and the gate is the second anti-fuse the second storage; the two diodes are connected in series to access the two anti-fuses.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: Non-volatile magnetic random access memory (MRAM) devices that include magnetic flip-flop structures that include a magnetization controlling structure; a first tunnel barrier structure; and a magnetization controllable structure that includes a first polarizing layer; and a first stabilizing layer, wherein the first tunnel barrier structure is between the magnetization controllable structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the first tunnel barrier structure, wherein the magnetic flip-flop device has two stable overall magnetic; configurations a second tunnel barrier structure and a reference layer, wherein the second tunnel barrier structure is between the magnetic flip-flop device and the reference layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, and a control circuit. The memory cell array includes plural memory cells arranged in rows and columns and each including a diode and resistance-change element. The control circuit tests the diodes for the respective memory cells. The control circuit tests the diode at least at one of times before and after one of a write operation, erase operation and read operation with respect to the memory cell is performed.

Abstract: A high performance memory based computation system comprises an array of memory cells. Each memory cell stores a logic data corresponding to a chosen combination of inputs based on a specific logic function. For improved performance, the memory cell array can be divided into sub-blocks; and the sub-blocks can be serially disposed or juxtaposed. The performance of the memory based computation system can further be improved by removing the repeated memory cell rows, column, and/or sub-arrays.

Abstract: In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a steering element above a substrate; and (2) fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (CNT) material above the substrate. Numerous other aspects are provided.