Abstract: A memory cell includes a first and second pull up transistor, a first and second pass gate transistor and a metal contact. The first pull up transistor has a first active region extending in a first direction. The first pass gate transistor has a second active region extending in the first direction, and being separated from the first active region in a second direction. The second active region is adjacent to the first active region. The second pass gate transistor is coupled to the second pull up transistor. The metal contact extends in the second direction, and extends from the first active region to the second active region. The metal contact couples drains of the first pull up transistor and the first pass gate transistor. The first and second pass gate transistors and the first and second pull up transistors are part of a four transistor memory cell.

Abstract: Various implementations described herein refer to an integrated circuit having an array of bitcells coupled between at least one pair of bitlines including a first bitline and a second bitline that is a complement of the first bitline. The integrated circuit may include at least one pair of ancillary lines disposed adjacent to the at least one pair of bitlines, and the at least one pair of ancillary lines include a first ancillary line disposed adjacent to the first bitline and a second ancillary line disposed adjacent to the second bitline. The integrated circuit may include multiple pairs of passgates coupled between the at least one pair of bitlines and the at least one pair of ancillary lines.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

Abstract: Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.

Abstract: Disclosed is a physical unclonable function generator circuit and method.

Abstract: A non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

Abstract: A memory circuit and a semiconductor device are provided. The memory circuit has a function of recovering data when power is suddenly shutdown. The memory device includes a bi-stable circuit capable of holding complementary data respectively at nodes N1 and N2; a first non-volatile memory circuit, connected to the node; and a second non-volatile memory circuit connected to the node. The first non-volatile memory circuit stores boot data, and the second non-volatile memory circuit inverts a logic level of the data held at the second node when the second non-volatile memory circuit stores data at the second node.

Abstract: A method and apparatus for reading data from a memory is disclosed. A particular data storage cell may generate a voltage difference between a true bit line and a complement bit line coupled to the data storage cell. A selection circuit may generate a voltage level on a true data line and a complement data line using the voltage levels of the true and complement bit lines. An amplifier circuit may amplify a voltage difference between the true data line and the complement data line to generate a full-swing voltage difference between the true and complement data lines, and may preset the voltage levels of the true and complement data lines to a ground potential based on a reset timing signal.

Abstract: A semiconductor device includes a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple, including a bottom tier including a contact disposed on a first inverter gate, a top tier including a second inverter gate, and a monolithic inter-tier via (MIV) that lands on the contact via the second inverter gate.

Abstract: An SRAM structure includes a substrate. A first active region, a second active region, a third active region and a fourth active region are disposed on the substrate. A first gate structure includes a first part, a second part and a third part disposed on the substrate. The first part and the third part are perpendicular to the first active region. The second part is parallel to the first active region. The first part covers the first active region, the second active region and the fourth active region. The third part covers the fourth active region. The second part is disposed on an insulating region between the second active region and the fourth active region, and the second part contacts the first part and the third part.

Abstract: Disclosed is a three-port static random access memory (3P-SRAM) that performs XNOR operations. The cell has a write port and first and second read ports. Read operations are enabled through either the first read port using a first read wordline and a common read bitline or the second read port using a second read wordline and the common read bitline. Read wordline activation is controlled such that only one read wordline is activated (i.e., receives a read pulse) at a time. As a result, a read operation through either read port effectively accomplishes an XNOR operation. Also disclosed is a memory array, which incorporates such cells and which performs XNOR-bitcount-compare functions. Since XNOR-bitcount-compare functions are used in XNOR-NET type binary neural networks (BNNs), the memory array can be employed for implementing such a BNN designed for improved performance, scalability, and manufacturability. Also disclosed is an in-memory computing method.

Abstract: A charge sharing Compute In Memory (CIM) may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a system voltage. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a read bit line. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal cap between XNOR and read bit line with a separate write bit line and write bit line bar.

Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

Abstract: Systems and memory devices that include a transistor shared by word line drivers are described. A memory device includes a first word line driver coupled to a first word line, and a second word line driver coupled to a second word line. The memory device also includes a transistor comprising a first terminal coupled to an output of the first word line driver, and a second terminal coupled to an output of the second word line driver.

Abstract: Disclosed is a physical unclonable function generator circuit and method.

Abstract: According to one embodiment, there is provided a semiconductor storage device including bit cells, a pair of bit lines, a word line, a write amplifier, a word line driver, and an assist timing control circuit. The pair of bit lines are electrically connected to the bit cells. The word line is electrically connected to the bit cells. The write amplifier is electrically connected to the pair of bit lines. The word line driver is electrically connected to the word line. The assist timing control circuit has an output side electrically connected to the write amplifier and the word line driver.

Abstract: Methods, systems, and devices for operating a memory device are described. A sense amplifier may be used to precharge an access line to increase the reliability of the sensing operation. The access line may then charge share with the memory cell and a capacitor, which may be a reference capacitor, which may result in high-level states and low-level states on the access line. By precharging the access line with the sense amplifier and implementing charge sharing between the access line and a capacitor, the resulting high-level state and the low-level states on the access line may account for any offset voltage associated with the sense amplifier.

Abstract: Disclosed herein is an apparatus that includes: a first diffusion region having a rectangular shape and including first and second source/drain regions arranged in the first direction; a second diffusion region having a rectangular shape and including third to fifth source/drain regions arranged in the first direction; a first gate electrode extending in a second direction, and provided between the first and second source/drain regions and between the third and fourth source/drain regions; and a second gate electrode extending in the second direction, and provided between the fourth and fifth source/drain regions. The first and third source/drain regions are brought into the same potential as each other, and the second and fourth, source/drain regions are brought into the same potential as each other.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

Abstract: Semiconductor devices are provided. The semiconductor devices may include an active pattern on a substrate. The active pattern may include a first source/drain region and a second source/drain region. The semiconductor devices may also include a bit line electrically connected to the first source/drain region, a first connection electrode electrically connected to the second source/drain region, and a capacitor on the first connection electrode. The capacitor may include a first electrode, a second electrode, and a dielectric pattern between the first and second electrodes. A lower portion of the dielectric pattern may overlap a top surface of the first connection electrode, and the first electrode may extend on an upper portion of a sidewall of the first connection electrode.

Abstract: Power consumption of a semiconductor device is reduced efficiently. The semiconductor device includes a power management unit, a cell array, and a peripheral circuit for driving the cell array. The cell array includes a word line, a bit line pair, a memory cell, and a backup circuit for backing up data in the memory cell. A row circuit and a column circuit are provided in a first power domain capable of power gating, and the cell array is provided in a second power domain capable of power gating. In the operation mode of a memory device, a plurality of low power consumption modes, which have lower power consumption than the standby mode, are set. The power management unit selects one from the plurality of low power consumption modes and performs control for bringing the memory device into the selected low power consumption mode.

Abstract: A volatile logic circuit has a storage node, and stores inputted information. A plurality of non-volatile elements are connected to the storage node of the volatile logic circuit through the same connection gate, and control lines for control for these non-volatile elements are connected to the respective non-volatile elements, every non-volatile element. A plurality of non-volatile elements are connected to the volatile logic circuit through the same connection gate in such a way, thereby enabling the yield to be enhanced.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a bitcell and multiple straps including a first strap, a second strap, and a third strap. The first strap may couple the bitcell to ground. The second strap may couple the bitcell to a bitline. The third strap may couple the bitcell to a wordline within a boundary of the bitcell.

Abstract: In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.

Abstract: A memory structure and a system-on chip (SOC) device are provided. A memory structure according to the present disclosure includes a first static random access memory (SRAM) macro comprising first gate-all-around (GAA) transistors and a second SRAM macro comprising second GAA transistors. The first GAA transistors of the first SRAM macro each includes a first plurality of channel regions each having a first channel width (W1) and a first channel thickness (T1). The second GAA transistors of the second SRAM macro each comprises a second plurality of channel regions each having a second channel width (W2) and a second channel thickness (T2). W2/T2 is greater than W1/T1.

Abstract: A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.

Abstract: Various embodiments of the present technology may comprise a method and apparatus for power management of a memory cell. The memory cell may be configured to operate at various voltage levels to mitigate power dissipation. The memory cell may receive a first voltage level during an active state and receive a second voltage level during an idle state. The active and idle states may be known based on predetermined system parameters. The second voltage level may be selected according to the particular characteristics of the memory cell in order to retain input data.

Abstract: To provide a sense amplifier which is capable of implementing a large capacity, a high speed, and an increased data rate of a semiconductor storage device. A sense amplifier is provided, the sense amplifier including: first and second inverters including switches configured to control an activation state and an inactivation state, and having inputs and outputs cross-coupled to each other, respectively; and first and second switches configured to switch between connection and disconnection of each of the cross-coupled first and second inverters with respect to an input from a storage element.

Abstract: A memory device includes a bit line precharge circuit configured to precharge bit lines of a memory array in response to a clock pulse. A controller is configured to output the clock pulse to the bit line precharge circuit, and to output a first word line enable signal to a word line driver. The first word line enable signal is delayed by a first delay time from the clock pulse, and a second word line enable signal is delayed by a second delay time from the clock pulse.

Abstract: An in-memory multiplier-accumulator includes a memory array, a multi-bit multiplier and a multi-bit layered adder. The memory array has a multiplicity of rows and columns, each column being divided into a plurality of bit line processors and each bit line processor operating on its associated pair of input values. The multi-bit multiplier utilizes each bit line processor to multiply the associated pair of input values in each bit line processor to generate multiplication results. The multi-bit layered adder accumulates the multiplication results of each column of bit line processors.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: A cell of a content-addressable memory (CAM) has a first switch, a second switch and a storage unit. A first end of the first switch and a first end of the second switch are coupled to a matchline. The first switch is controlled by a first search signal, and the second switch is controlled by a second search signal. The second search signal is complementary to the first search signal. The storage unit has a first inverter and a second inverter. The first inverter has a first latch node coupled to a second end of the first switch. The second inverter is cross-coupled to the first inverter and has a second latch node coupled to a second end of the second switch.

Abstract: Various implementations described herein are directed to memory circuitry having an array of bitcells and bitlines coupled to columns of the bitcells. Also, column decoder circuitry may be coupled to the bitcells via the bitlines, and the column decoder circuitry may have read logic coupled to an output node. The column decoder circuitry may have select logic coupled between a voltage supply and the read logic. Enable signals may be used to activate the select logic to pass the voltage supply to the read logic, and the bitlines provide bitline signals that activate the read logic to pass the voltage supply from the select logic to the output node.

Abstract: A semiconductor device includes a first fin, a first gate electrode, a second fin, a second gate electrode, and a first dielectric capping layer. The first fin extends along a direction. The first gate electrode is across the first fin and has a first notched corner. The second fin extends along the direction. The second gate electrode is across the second fin and has a second notched corner. The first dielectric capping layer has a first portion in between the first notched corner and the second notched corner.

Abstract: A memory cell includes a memory cell stack, a first word line, a second word line, a bit line coupled to one end of the memory cell stack, a first unidirectional selector having one end coupled to another end of the memory cell stack and another end coupled to the first word line, and a second unidirectional selector having one end coupled to the another end of the memory cell stack and another end coupled to the second word line. Current flow directions of the first unidirectional selector and the second unidirectional selector are opposite to each other.

Abstract: A power-supply circuit for a memory includes a bitcell power-supply circuit and a bitcell power-control circuit. The bitcell power-supply circuit includes a first terminal coupled to a bitcell of the memory. The bitcell power-control circuit is coupled to the bitcell power-supply circuit, and controls the bitcell power-supply circuit in a write-assist mode to output a first voltage on the first terminal that is based on a ratio of capacitance of the bitcell and of capacitance of a charge-sharing capacitance. The bitcell power-control circuit further controls the bitcell power-supply circuit in a data-retention mode to output a second voltage on the first terminal that is about one diode drop below a voltage of a main power supply to the bitcell. The bitcell power-control circuit also controls the bitcell power-supply circuit in a power-down mode to turn off power output from the first terminal.

Abstract: A memory device includes memory cells and a control circuit. Each memory cell includes a first inverter, a second inverter, a first transistor and a second transistor. The first and second inverters are cross-coupled between a first data node and a second data node. The first transistor has a first control terminal coupled to a wordline, a first connection terminal coupled to a bitline, and a second connection terminal. The second transistor has a second control terminal, a third connection terminal and a fourth connection terminal. The second control terminal is coupled to the first data node. The third connection terminal is coupled to the second connection terminal. The control circuit is coupled to the fourth connection terminal, and is configured to, when the bitline is selected, adjust a voltage level at the fourth connection terminal in response to activation of the wordline.

Abstract: An operation assist circuit includes a precharge and equalization circuit, a first sharing switch and a second sharing switch. The precharge and equalization circuit is coupled between a first dummy bit line and a second dummy bit line of a dummy bit line pair and configured to precharge and equalize the first dummy bit line and the second dummy bit line. The first sharing switch is coupled between a first bit line of a bit line pair and the first dummy bit line of the dummy bit line pair. The first sharing switch is configured to control an electrical connection between the first bit line of the first bit line pair and the first dummy bit line of the dummy bit line pair according to a charge sharing control signal. The second sharing switch, coupled between a second bit line of the bit line pair and the second dummy bit line of the dummy bit line pair.

Abstract: A charge sharing type lower-cell-voltage (LCV) write assist takes advantage of unused metal layers on top of a memory array to implement capacitance without incurring area costs. Only one-time fixed amount expenses of charge are needed for a given LCV level during the charge sharing phase of each write operation. Metal wires parallel to the bit cell power wires have good capacitance matching for charge sharing among all memory density configurations, thus benefitting memory compiler design.

Abstract: A memory system includes a first array (of memory cells) and a second array (of write assist circuits) arranged into columns each including a bit line and a bit_bar line coupled to corresponding memory cells of the first array and a corresponding at least one write assist circuit of the second array, each write assist circuit including: latch and memory-adapted third and fourth NMOS transistors. The latch includes: memory-adapted first PMOS and first NMOS transistors connected in series between a power-supply voltage and a first node selectively connectable to a ground voltage; and memory-adapted second PMOS transistor and second NMOS transistors connected in series between the power-supply voltage and a second node selectively connectable to ground voltage. The third NMOS transistor is connected in series between the first node and ground voltage; and the fourth NMOS transistor connected in series between the second node and ground voltage.

Abstract: A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns; a data input/output port; an address input port; a mode selection input port; and an internal control circuit configured to: read a mode selection signal applied to the mode selection port; when the mode selection signal is in a first state, read an address of a row from the address input port and implement a read or write operation in this row; and when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation including the simultaneous activation in read or write mode of at least two rows.

Abstract: A semiconductor structure includes SRAM cells, bit-line edge cells, and word-line edge cells, wherein the SRAM cells are arranged in an array, bordered by the bit-line edge cells and the word-line edge cells, each of the SRAM cells including two inverters cross-coupled together and a pass gate coupled to the two inverters, and the pass gate includes a FET; a first bit-line of a first metal material, disposed in a first metal layer, and electrically connected to a drain feature of the FET; a first word-line of a second metal material, and electrically connected to a gate electrode of the FET, and disposed in a second metal layer; and a second bit-line of a third metal material, electrically connected to the first bit-line, and disposed in a third metal layer. The first metal material and the third metal material are different from each other in composition.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: The claimed subject matter relate to circuits and/or methods, which operate to introduce a variable delay in a write-assist signal to a write driver of an array of SRAM cells. Particularly, a variable delay may be introduced by way of a voltage tracking circuit, which may generate a trigger signal in response to a voltage signal from an array of access devices that replicate access devices of the array of SRAM cells.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.

Abstract: A first gate structure, a second gate structure, and a third gate structure each extend in a first direction. A first gate via is disposed on the first gate structure. The first gate via has a first size. A second gate via is disposed on the second gate structure. The second gate via has a second size that is greater than the first size. A third gate via is disposed on the third gate structure. The third gate via has a third size that is less than the second size but greater than the first size. A first source contact is disposed adjacent to a first side of the first gate via. A first drain contact is disposed adjacent to a second side of the first gate via opposite the first side. A second drain contact is disposed adjacent to a first side of the third gate via.

Abstract: Wells formed in a semiconductor device can be discharged faster in a transition from a stand-by state to an active state. The semiconductor device includes an n-type well applied, in an active state, with a power supply voltage and, in a stand-by state, with a voltage higher than the power supply voltage, a p-type well applied, in the active state, with a ground voltage and, in the stand-by state, with a voltage lower than the ground voltage, and a path which, in a transition from the stand-by state to the active state, electrically couples the n-type well and the p-type well.

Abstract: A dynamic temperature compensation trim for use in temperature compensating a memory operation on a memory call of a memory component. The dynamic temperature compensation trim is based on a temperature of the memory component and based on in-service data for the memory operation on the memory cell. A register for the memory operation is modified based on the dynamic temperature compensation trim.

Abstract: A memory array includes a first memory cell and a second memory cell. Each of the first and the second memory cells includes a data storage element having a first terminal and a second terminal, a first access transistor coupled to the first terminal of the data storage element, and a second access transistor coupled to the second terminal of the data storage element. The memory array also includes a first word line and a second word line coupled to the first access transistor and the second access transistor, respectively, of the first memory cell, wherein the first word line and the second word line are operated independently during a read operation and activated at the same time during a write operation.