Abstract: According to one embodiment, a variable resistance memory includes first and second semiconductor regions in a layer; a memory cell on the first semiconductor region, the memory cell including a first transistor having a first gate connected to a word line and a memory element, the word line extending in a first direction parallel to a surface of the layer; and a second transistor on the second semiconductor region and connected to the memory cell via a bit line, the bit line extending a second direction parallel to the surface of the layer, and the second direction intersecting the first direction. The second semiconductor region extends in a third direction parallel to the surface of the substrate and the third direction intersects the first and second directions.

Abstract: A self-referenced MRAM cell including a reference layer having a fixed reference magnetization, a sense layer having a free sense magnetization, a tunnel barrier, a biasing layer having bias magnetization and a biasing antiferromagnetic layer pinning the bias magnetization in a bias direction when MRAM cell is at temperature equal or below a bias threshold temperature. The bias magnetization is arranged for inducing a bias field adapted for biasing the sense magnetization in a direction opposed to the bias direction, such that the biased sense magnetization varies linearly in the presence of the external magnetic field, when the external magnetic field is oriented in a direction substantially perpendicular to the one of the reference magnetization. The present disclosure further concerns a magnetic field sensor including a plurality of the self-referenced MRAM cell and a method for programming the magnetic field sensor.

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein the free layer may include a first magnetic layer; a second magnetic layer formed over the first magnetic layer; and a Zirconium (Zr)-containing material layer interposed between the first magnetic layer and the second magnetic layer.

Abstract: A high-reliability resistive random access memory (RRAM). A memory cell of a memory cell array is controlled via a word line, a bit line and a source line. The control unit of the RRAM has a word line decoder, a bit line decoder, and a source line decoder and switch circuit. The word line decoder, the bit line decoder and the source line decoder respectively control the voltage applied to the word line, the voltage applied to the bit line, and the voltage applied to the source line. The switch circuit is switched between a first state and a second state to operate the bit line decoder to apply a voltage to the bit line to read the memory cell and to operate the source line decoder to apply a voltage to the source line to read the memory cell alternately.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.

Abstract: According to one embodiment, a magnetic memory includes a first metal layer including a first metal, a second metal layer on the first metal layer, the second metal layer including a second metal which is more easily oxidized than the first metal, the second metal layer having a first sidewall portion which contacts the first metal layer, and the second metal layer having a second sidewall portion above the first sidewall portion, the second sidewall portion which steps back from the first sidewall portion, a magnetoresistive element on the second metal layer, a third metal layer on the magnetoresistive element, and a first material which contacts a sidewall portion of the magnetoresistive element and the second sidewall portion of the second metal layer, the first material including an oxide of the second metal.

Abstract: According to one embodiment, a magnetic memory device includes a first memory unit including a first memory array and a first drive unit, a second memory unit including a second memory array and a second drive unit, and a controller. The first memory array includes a first magnetic shift register unit. The second memory array includes a second magnetic shift register unit. The controller subdivides input data into a plurality of one-dimensional bit input arrays. The one-dimensional bit input arrays include a first array and a second array. The controller stores the first array in the first magnetic shift register unit on a last in, first out basis, and stores the second array in the second magnetic shift register unit on a last in, first out basis.

Abstract: Various memory devices are disclosed herein. An exemplary memory device includes a first electrode, a first magnetic layer disposed over the first electrode, a second magnetic layer disposed over the first magnetic layer, a barrier layer disposed between the first magnetic layer and the second magnetic layer, and a second electrode disposed over the second magnetic layer. The second electrode includes a magnetic assist region configured to produce a magnetic field that assists in aligning an orientation of a magnetic field of the second magnetic layer.

Abstract: A sensing amplifier includes a first bit line driver, a second bit line driver and a third bit line driver. The first bit line driver sets a first bit line for a fast-pass-write (FPW) operation. The second bit line driver sets a second bit line for a first operation rather than the FPW operation. The third bit line driver sets a third bit line for a second operation rather than the FPW operation. The first bit line is arranged between the second bit line and the third bit line, and the second bit line driver and the third bit line driver respectively adjust voltage statuses of the second bit line and the third bit line to rise a voltage level of the first bit line by a compensated level.

Abstract: A magnetic memory according to an embodiment includes: a conductive layer including a first and second terminals; a plurality of magnetoresistive elements separately disposed on the conductive layer between the first and second terminals, each magnetoresistive element including a reference layer, a storage layer between the reference layer and the conductive layer, and a nonmagnetic layer between the storage layer and the reference layer; and a circuit configured to apply a first potential to the reference layers of the magnetoresistive elements and to flow a first write current between the first and second terminals, and configured to apply a second potential to the reference layer or the reference layers of one or more of the magnetoresistive elements to which data is to be written, and to flow a second write current between the first and second terminals in an opposite direction to the first write current.

Abstract: A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.

Abstract: A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A magnetic tunneling junction (MTJ) stack is formed in between adjacent ILD levels of the upper ILD layer. The MTJ stack includes a free layer, a tunneling barrier layer and a fixed layer. The fixed layer includes a polarizer layer, a composite texture breaking layer which includes a first magnesium layer and a synthetic antiferromagnetic (SAF) layer.

Abstract: A method for writing a MRAM device, including magnetic tunnel junction with a storage layer, a sense layer, and a spacer layer between the storage and sense layers. At least one of the storage and sense layers has a magnetic anisotropy axis. The method includes an initialization step including: applying an initial heating current pulse for heating the magnetic tunnel junction to a temperature above a threshold temperature at which a storage magnetization is freely orientable, providing an initial resultant magnetic field for adjusting the storage magnetization in an initial direction oriented along the magnetic anisotropy axis. The method allows performing the writing step with improved reproducibly.

Abstract: Some embodiments include an improved memory array architecture and memory cell design. In one of such embodiments, a memory cell may comprise a memory element to store a logic state and two access transistors coupled to the memory element to access the logic state of the memory element. Other embodiments are described.

Abstract: Improved STT MRAM source line configurations are provided. In one aspect, a STT MRAM array includes: a plurality of cells including magnetic tunnel junctions in series with field effect transistors; a plurality of word lines perpendicular to a plurality of bit lines; a plurality of source line segments spanning m+1 of the bit lines, wherein m of the bit lines include regular array bit lines, and wherein at least one other of the bit lines includes an extra bit line that is connected to the source line segments such that the source line segments span the regular array bit lines and the extra bit line. An STT MRAM device and a method for operating an STT MRAM device are also provided.

Abstract: A method for reading out a resistive memory cell comprising two electrodes that are spaced from each other by an ion-conducting resistive material was developed, the memory cells being transferrable from a stable state having a higher resistance value (high resistive state, HRS) to a stable state having a lower resistance value (low resistive state, LRS) when a write voltage is applied.

Abstract: The present invention is directed to a method for programming a magnetic tunnel junction (MTJ) coupled to a transistor having a gate, a source, and a drain. The method includes the steps of setting a voltage of a source line to a first voltage, the source line being coupled to one of the source and drain of the transistor, the other one of the source and drain of the transistor being coupled to one end of the MTJ; setting a voltage of a bit line to zero, the bit line being coupled to the other end of the MTJ; setting a voltage of a word line coupled to the gate of the transistor to a second voltage that is higher than the first voltage; and programming the MTJ from a first resistance state to a second resistance state by driving a current through the MTJ from the source line to the bit line.

Abstract: Embodiments are directed to a magnetic tunnel junction (MTJ) memory cell that includes a reference layer formed from a perpendicular magnetic anisotropy (PMA) reference layer and an interfacial reference layer. The MTJ further includes a free layer and a tunnel barrier positioned between the interfacial reference layer and the free layer. The tunnel barrier is configured to enable electrons to tunnel through the tunnel barrier between the interfacial reference layer and the free layer. A first in-situ alignment is provided between a tunnel barrier lattice structure of the tunnel barrier and an interfacial reference layer lattice structure of the interfacial reference layer. A second in-situ alignment is provided between the tunnel barrier lattice structure of the tunnel barrier and a free layer lattice structure of the free layer. The PMA reference layer lattice structure is not aligned with the interfacial reference layer lattice structure.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure comprising a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer may include: a first under layer including a silicon-based alloy; a second under layer including a metal; and a blocking layer interposed between the first under layer and the second under layer and including an amorphous material.

Abstract: A nonvolatile memory device comprises: a nonvolatile memory; a resistance-time converter that outputs an end signal at timing according to a resistance value of the nonvolatile memory; and a time-digital converter that measures the time from input of a start signal to input of the end signal and converts the measured time into a digital value. The time-digital converter includes: a ring delay circuit that includes delay elements connected in a ring configuration; a counter circuit that counts the number of times of a rising edge or a falling edge in output of one of the delay elements; a first memory circuit that stores, based on the end signal, outputs of the delay elements as first data; and a second memory circuit that stores, based on the end signal, a count value of the counter circuit as second data.

Abstract: A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer. The pinned layer structure contacts the tunnel barrier layer and includes at least one pinned layer. The vertical polarizer structure contacts the insulation barrier layer and includes a plurality of magnetization multi-layered structures sequentially stacked. Each magnetization multi-layered structure includes a non-magnetic layer and a magnetic layer sequentially stacked. The pinned layer and the magnetic layer have magnetization directions anti-parallel to each other.

Abstract: A method for a non-volatile memory cell; specifically, a spin orbit torque MRAM (SOT-MRAM) memory cell which reduces the current required to switch individual bits. The memory cell includes a first interconnect line having a first longitudinal axis, an elliptically shaped MTJ bit (“bit”) having a long axis, and a second interconnect line having a second longitudinal axis perpendicular to the first interconnect line. The bit includes a polarized free layer, a barrier layer, and a polarized reference layer with a magnetic moment pinned at an angle different from the long axis. By disposing the long axis at an angle relative to the first longitudinal axis and second longitudinal axis and the reference layer as described, and applying a voltage to the interconnect line, a non-zero equilibrium angle can be induced between the free layer and the spin current or the Rashba field resulting in more coherent switching dynamics.

Abstract: According to one embodiment, a magnetic memory includes a structure body including a first magnetic layer and a conductive layer, a second magnetic layer, a first electrode, a second electrode, a third magnetic layer, an intermediate layer, a third electrode, a fourth magnetic layer, and a circuit element. The first magnetic layer is disposed between the second magnetic layer and the conductive layer. The first electrode is connected to a first portion of the structure body. The intermediate layer is provided between the third magnetic layer and the second magnetic layer. The circuit element includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is connected to the first electrode. The second semiconductor layer is connected to the third magnetic layer. The third semiconductor layer is connected to the first semiconductor layer and the second semiconductor layer.

Abstract: An apparatus includes a perpendicular magnetic tunnel junction (MTJ) including a free layer. The apparatus includes a spin orbit torque metal layer coupled to the perpendicular MTJ and configured to change a magnetization state of the free layer responsive to flow of a current along the spin orbit torque metal layer. The apparatus includes a random number generator configured to generate a random number at least partially based on a state of the perpendicular MTJ.

Abstract: According to one embodiment, a memory device includes a memory cell array; a generation circuit generating a reference current; a sense amplifier comparing a cell current flowing through a memory cell with the reference current; a first clamp transistor connected between the sense amplifier and the memory cell; a second clamp transistor connected between the sense amplifier and the generation circuit; a first interconnect layer connected to a gate of the first clamp transistor; a second interconnect layer connected to a gate of the second clamp transistor and arranged adjacent to the first interconnect layer; and a first shield line arranged adjacent to one of the first interconnect layer and the second interconnect layer, a fixed voltage being applied to the first shield line.

Abstract: A storage element and storage devices containing the same, having a layered structure and being configured for storing information are disclosed. In one example, the storage element comprises a storage portion with a storage magnetization that is perpendicular to a film surface of the layered structure, wherein a direction of the storage magnetization is configured to change according to the information. The storage element also includes a fixed magnetization portion with reference magnetization serving as a reference to the storage magnetization, and an intermediate portion between the storage portion and the fixed magnetization portion that is made of a non-magnetic material. The fixed magnetization portion includes a laminated ferrimagnetic structure that comprises a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer. The fixed magnetization portion includes a first magnetic material that is an alloy or a laminated structure including Pt, Co, and Y.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes a semiconductor memory, and the semiconductor memory includes a variable resistance structure including a material having a resistance that is changed by formation or dissipation of conductive filaments; and a Magnetic Tunnel Junction (MTJ) structure inserted in the variable resistance structure and comprising a first magnetic layer having a pinned magnetization direction, a second magnetic layer having a variable magnetization direction, and a tunnel dielectric layer interposed between the first magnetic layer and the second magnetic layer.

Abstract: A bit-line of a resistive memory cell includes a reference branch including a reference resistor having a predetermined value and a cell branch including an adjustable memory resistor having a variable value. The reference branch generates a reference current based on the predetermined value of the reference resistor and the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor. A sense amplifier has a first input coupled to the reference branch and a second input coupled to the cell branch. A first pre-charge transistor is coupled to a first pre-charge voltage and the cell branch. The first pre-charge transistor is configured to pre-charge the cell branch to the first pre-charge voltage prior to a read operation.

Abstract: Embodiments of the subject invention provide a three transistor, two domain-wall-based magnetic tunnel junction CAM cell (3T-2DW-MTJ CAM). A four transistor, two magnetic tunnel junction ternary CAM cell (4T-2MTJ TCAM) is also provided. An array of the provided CAM cells forms words of various lengths, such as 4-bit, 8-bit, and 16-bit words. Longer CAM words can be formed by an array having hierarchical structures of CAM cells having smaller word sizes, such as 4-bit words or 8-bit words.

Abstract: An integrated circuit includes a magnetic OTP memory array formed of multiple magnetic OTP memory cells having an MTJ stack with a fixed magnetic layer, a tunnel barrier insulating layer, a free magnetic layer, and a second electrode. When a voltage is applied across the magnetic OTP memory cell, the resistance of the MTJ stack and the gating transistor form a voltage divider to apply a large voltage across the MTJ stack to breakdown the tunnel barrier to short the fixed layer to the free layer. The integrated circuit has multiple MRAM arrays configured such that each of the multiple MRAM arrays have performance and density criteria that match MOS transistor based memory including SRAM, DRAM, and flash memory. The integrated circuit may include a functional logic unit connected with the magnetic OTP memory arrays and the MRAM arrays for providing digital data storage.

Abstract: Methods of etching metal by depositing a material reactive with a metal to be etched and a halogen to form a volatile species and exposing the substrate to a halogen-containing gas and activation gas to etch the substrate are provided. Deposited materials may include silicon, germanium, titanium, carbon, tin, and combinations thereof. Methods are suitable for fabricating MRAM structures and may involve integrating ALD and ALE processes without breaking vacuum.

Abstract: A method for providing a magnetic junction usable in a magnetic device and the magnetic junction are described. The method includes providing a free layer, a pinned layer and a nonmagnetic spacer layer between the free layer and the pinned layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. At least one of the steps of providing the free layer and providing the pinned layer includes providing magnetic and sacrificial layers and performing two anneals of the sacrificial and magnetic layers. The magnetic layer includes a glass-promoting component and is amorphous as-deposited. The first anneal is at a first temperature exceeding 300 degrees Celsius and not exceeding 450 degrees Celsius. The second anneal is at a second temperature greater than the first temperature and performed after the first anneal. The sacrificial layer is removed.

Abstract: A method of controlling a magnetoresistive random access memory includes receiving first signals associated with an active state through command/address pins; then receiving second signals associated with column and row addresses for a read operation, through the command/address pins, and in response reading data from a memory cell according to the row address; receiving third signals associated with column and row addresses for a write operation through the command/address pins, while reading the data; outputting the read data to data input/output pins, according to the column address for the read operation, after a lapse of a read latency; inputting data through the data input/output pins, in response to the third signals, according to the column address for the write operation, after a lapse of a write latency; and writing the data inputted from the data input/output pins to a memory cell according to the row address for the write operation.

Abstract: A nonvolatile memory of an embodiment includes: first through fifth wirings; and a memory cell including: a first circuit including a first magnetoresistive element and a first select transistor, the first magnetoresistive element and the first select transistor being electrically connected in series, the first magnetoresistive element including a first reference layer, a first storage layer, and a first nonmagnetic layer between the first reference layer and the first storage layer; a second circuit including a second magnetoresistive element and a second select transistor, the second magnetoresistive element and the second select transistor being electrically connected in series, the second magnetoresistive element including a second reference layer, a second storage layer, and a second nonmagnetic layer between the second reference layer and the second storage layer; a third circuit including first and second transistors; and a fourth circuit including third and fourth transistors.

Abstract: A storage device includes a nonvolatile memory and a memory controller. The nonvolatile memory performs read, write, and erase operations. The memory controller operates in an operating mode where the memory controller exchanges a voltage signal, set to a reference voltage level within an allowable range, with the nonvolatile memory or receives the voltage signal from an external device. When operating in the operating mode, the memory controller optimizes an operating frequency of the nonvolatile memory depending on a voltage level of the voltage signal and a temperature.

Abstract: According to one embodiment, a resistance change memory includes a memory cell, a reference voltage generating circuit, a first transistor and a sense amplifier. The memory cell includes a resistance change element. The reference voltage generating circuit generates a reference adjustment voltage. The first transistor provides a reference current in accordance with the reference adjustment voltage. The sense amplifier compares a cell current flowing through the memory cell with the reference current flowing through the first transistor.

Abstract: Integrated circuits with memory cells and methods of programming the memory cells are provided. In an exemplary embodiment, a method of programming a memory cell includes determining a memory cell temperature for a memory cell within an integrated circuit. A pulse number is determined, where the pulse number is the number of electrical pulses at a set voltage required to program the memory cell at the memory cell temperature. The memory cell is programmed with a write operation, where the write operation includes the pulse number of electrical pulses.

Abstract: A multi-bit magnetic random access memory (MRAM) cell including a magnetic tunnel junction including: a first magnetic storage layer, a second magnetic storage layer, a magnetic sense layer, a first spacer layer between the first magnetic storage layer and the magnetic sense layer, and a second spacer layer between the second magnetic storage layer and the sense layer. The first and second storage magnetization are switchable between m directions to store data corresponding to one of m2 logic states, with m>2. The present disclosure further concerns a method for writing and reading to the MRAM cell and to memory devices including multi-bit MRAM cells.

Abstract: A memory device having features of the present invention comprises a reprogrammable memory portion including therein a first plurality of magnetic tunnel junctions (MTJs) whose resistance is switchable; and a one-time-programmable (OTP) memory portion including therein a second plurality of MTJs whose resistance is switchable and a third plurality of MTJs whose resistance is fixed. Each MTJ of the first, second, and third plurality of MTJs includes a magnetic free layer having a magnetization direction substantially perpendicular to a layer plane thereof and a magnetic reference layer having a fixed magnetization direction substantially perpendicular to a layer plane thereof. The second plurality of MTJs represents one of two logical states and the third plurality of MTJs represents the other one of the two logical states.

Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier.

Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetoresistive random access memory (MRAM) chip magnetic shielding and vertical stacking capabilities processed at the wafer-level are disclosed. The method includes providing a magnetic shield in the through silicon vias and/or through silicon trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the MRAM region and also at the front side and back side of the chip. Magnetic shield in the through silicon trenches connects front side and back side magnetic shield. Magnetic shield in the through silicon vias provides vertical stacking, magnetic shielding and electrical connection of the MRAM chips to form 3D IC packages. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the MRAM region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.

Abstract: A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line (BL) coupled to the selected MTJ and a selected source line (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.

Abstract: Improved STT MRAM CSL array bias schemes are provided. In one aspect, a method for operating a CSL STT MRAM array includes: providing the STT MRAM array having a plurality of word lines perpendicular to both a plurality of bit lines and at least one source line; a plurality of memory cells including magnetic tunnel junctions in series with field effect transistors, wherein the field effect transistors are gated by the word lines, wherein the bit lines are connected to the magnetic tunnel junctions, and wherein the source line is connected to the field effect transistors; and applying a first word line voltage (Vdd) to a selected one of the word lines during a read, and a different second word line voltage (Vpp) to the selected word line during a write.

Abstract: A magnetic-assist, spin-torque transfer magnetic tunnel junction device and a method for performing a magnetic-assist, spin-torque-transfer write to the device are disclosed. In an exemplary embodiment, the magnetic tunnel junction device includes a first electrode, a pinned layer disposed on the first electrode, a free layer disposed on the pinned layer, and a barrier layer disposed between the pinned layer and the free layer. The device further includes a second electrode electrically coupled to the free layer, the second electrode containing a magnetic assist region. In some embodiments, the magnetic assist region is configured to produce a net magnetic field when supplied with a write current. The net magnetic field is aligned to assist a spin-torque transfer of the write current on the free layer.

Abstract: An electronic device includes a semiconductor memory that includes: a memory cell coupled between a first line and a second line; a first selection block configured to select the first line; a second selection block configured to select the second line; an alternate current supply block configured to supply, during a read operation, an alternate current corresponding to a resistance state of the memory cell; and a sensing block configured to sense, during the read operation, at least one of a cell current flowing through the memory cell and the alternate current.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a resistance-change element having first and second terminals, a transistor having third and fourth terminals and a control terminal, the third terminal being electrically connected to the second terminal, and a driver electrically connected to the first and fourth terminals, applying one of a first potential and a second potential to the first terminal and the other of the first and second potentials to the fourth terminal in writing, and applying one of the first and second potentials to the first terminal and the other of the first and second potentials to the fourth terminal in reading.

Abstract: Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.

Abstract: According to one embodiment, a logical operation circuit includes a magnetic tunnel junction (MTJ) element and driver. The MTJ element includes a first magnetic layer, a second magnetic layer, and an intermediate layer between the first and second magnetic layers. An orientation of magnetization of the second magnetic layer flips by a first current which flows through the MTJ element in a first state from the second magnetic layer to the first magnetic layer. The driver is coupled to the first magnetic layer without a magnetic layer interposed and coupled to the second magnetic layer, and passes a second current through the MTJ element in the first state from the second magnetic layer to the first magnetic layer. A magnitude of the second current is larger than 1.5 times a magnitude of the first current.

Abstract: A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter.