Abstract: A non-volatile storage device includes: a first electrode; a second electrode; a variable resistance element including a variable resistance layer having a resistance value which changes according to a voltage pulse applied between the first and second electrodes; a voltage pulse application circuit which applies the voltage pulse between the first and second electrodes; and a control circuit which controls the voltage pulse application circuit. Upon receiving an external instruction, the control circuit: reads a current resistance state of the variable resistance element; and when the current resistance state is the high resistance state, causes the voltage pulse application circuit to apply a first additional voltage pulse having a first polarity between the electrodes; and when the current resistance state is the low resistance state, causes the voltage pulse application circuit to apply, between the electrodes, a second additional voltage pulse having a second polarity different from the first polarity.

Abstract: An image sensor includes: a filter array, a reading circuit, a controller, a converter and an image output interface, wherein: the controller is coupled to the reading circuit, the converter and the image output interface; the filter array comprises a plurality of color filter array patterns; each color filter array pattern comprises color filters and at least one infrared (IR) filter; the color filters are configured to capture visible rays; the IR filters are configured to capture IR rays; the reading circuit is configured to read out IR signals from the IR filters only or read out IR signals from the IR filters and color signals from a part of the color filters under control of the controller; the converter is configured to convert the IR signals into IR digital signals; the image output interface is configured to output the IR digital signals.

Abstract: A magnetic memory includes magnetoresistance effect elements, each of which includes a first ferromagnetic metal layer in which a magnetization direction is fixed, a second ferromagnetic metal layer for a magnetization direction to be changed, and a nonmagnetic layer provided between the first ferromagnetic metal layer and the second ferromagnetic metal layer, a first wiring connected to the first ferromagnetic metal layer of at least one magnetoresistance effect element, spin-orbit torque wirings, each of which is connected to each of the second ferromagnetic metal layers of the magnetoresistance effect elements and extend in a direction intersecting a lamination direction of the magnetoresistance effect element, one first control element connected to the first wiring, one second control element connected to each of first connection points of the spin-orbit torque wirings, and first cell selection elements, each of which is connected to each of second connection points of the spin-orbit torque wirings.

Abstract: A magnetic memory according to an embodiment includes: first to third terminals; a nonmagnetic conductive layer including first to third regions, the second region being disposed between the first and third regions, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; and a magnetoresistive element disposed to correspond to the second region, including a first magnetic layer electrically connected to the third terminal, a second magnetic layer disposed between the first magnetic layer and the second region, and a nonmagnetic layer disposed between the first and second magnetic layers, the conductive layer including at least one of an alloy including Ir and Ta, an alloy including Ir and V, an alloy including Au and V, an alloy including Au and Nb, or an alloy including Pt and V, each of the alloys having an fcc structure.

Abstract: Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having large spin-orbit coupling strength and high electrical resistivity. Each lead of the plurality of leads may include a plurality of first portions and a plurality of second portions distinct from the first portions. The electrical resistivity of the second portions is less than that of the first portions, so the total electrical resistivity of the lead is reduced, leading to improved power efficiency and signal to noise ratio.

Abstract: Embodiments of the present invention provide flash-based storage with non-volatile memory components. MRAM is mainly used as a data buffer, and NOR flash is used to store metadata, such as FTL information, thereby providing non-volatile storage and significantly simplifying power failure mitigation. MRAM and NOR are jointly used to share the work performed by DRAM in existing SSDs based on the characteristics of the data stored, reducing the power consumption and cost of the SSD. The cache fault rate is reduced because both MRAM and NOR are immune from soft errors. Moreover, the working mechanisms are simplified and the power-up duration is significantly reduced because less data is copied from NAND flash, as there is no need to move all of the FTL information back to NAND flash at power off.

Abstract: A magnetic memory according to an embodiment includes: a first conductive layer including a first to third regions arranged along a first direction, the second region being disposed between the first region and the third region; a second conductive layer including a fourth to sixth regions arranged along the first direction, the fifth region being disposed between the fourth and sixth regions; a third conductive layer electrically connected to the third and fourth regions; a first magnetoresistance device disposed to correspond to the second region, including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second magnetoresistance device to correspond to the fifth region, including a third magnetic layer, a fourth magnetic layer, and a second nonmagnetic layer, a direction from the first region to the third region differing from a direction from the fourth region to the sixth region.

Abstract: Aspects of the disclosure provide magnetoresistive random access memory (MRAM) and methods. The MRAM generally includes a first magnetic tunnel junction (MTJ) storage element comprising a first fixed layer, a first insulating layer, and a first free layer, and a second MTJ storage element comprising a second fixed layer, a second insulating layer, and a second free layer. The MRAM further includes a conductive layer connected to a source line, first bit line, and a second bit line, wherein the first MTJ storage element is disposed above and connected to the conductive layer and the first bit line at a first end and connected to the first bit line at a second end, and wherein the second MTJ storage element is disposed above and connected to the conductive layer and the second bit line at a first end and connected to the second bit line at a second end.

Abstract: A ferroelectric memory device includes a first electrode layer disposed on a substrate, a first tunnel barrier layer disposed on the first electrode layer, a second electrode layer disposed on the first tunnel barrier layer, a second tunnel barrier layer disposed on the second electrode layer, and a third electrode layer disposed on the second tunnel barrier layer. Any one of the first and second tunnel barrier layers includes a ferroelectric material.

Abstract: In one embodiment, a spin torque device uses a thick (e.g., >1 nm, and preferably >=2-6 nm) ferrimagnet (FIM) layer, instead of a thin (e.g., <1-2 nm) FM layer in the device's stack. The FIM layer may be composed of a cobalt-gadolinium (Co—Gd) alloy, cobalt-terbium (Co—Tb) multilayers, or other materials that provide anti-ferromagnetic coupling between two sub-lattices. Negative exchange interaction between the two sub-lattices of the FIM may allow for low current switching. High thermal stability and external magnetic field resistance may also be achieved.

Abstract: A method for fabricating an improved magnetic tunneling junction (MTJ) structure is described. A bottom electrode is provided on a substrate. A MTJ stack is deposited on the bottom electrode. A top electrode is deposited on the MTJ stack. A first stress modulating layer is deposited between the bottom electrode and the MTJ stack, or a second stress modulating layer is deposited between the MTJ stack and the top electrode, or both a first stress modulating layer is deposited between the bottom electrode and the MTJ stack and a second stress modulating layer is deposited between the MTJ stack and the top electrode. The top electrode and MTJ stack are patterned and etched to form a MTJ device. The stress modulating layers reduce crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

Abstract: Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing. Including precharging in the sense amplifiers used to access the memory cells enables self-referenced read operations to be completed more quickly than is possible without precharging. Similarly, precharging can also be used in conjunction with write-back operations in order to allow the data state stored by magnetic tunnel junctions included in the memory cells to be changed more rapidly.

Abstract: Integrated circuits and methods of operating and producing the same are provided. In an exemplary embodiment, an integrated circuit includes a look up table with a first and second memory cell. The first memory cell includes a first magneto electric (ME) layer, a first free layer adjacent to the first ME layer, and a first fixed layer. The second memory cell includes a second ME layer, a second free layer adjacent to the second ME layer, and a second fixed layer. A first word line is in direct communication with the first and second free layers, wherein direct communication is a connection through zero, one, or more intervening components that are electrical conductors. A first bit line is in direct communication with the first ME layer, and a second bit line is in direct communication with the second ME layer.

Abstract: Double magnetic tunnel junctions and methods of forming the same include a bottom reference layer having a first fixed magnetization and a first thickness. A first tunnel barrier is formed on the bottom reference layer. A free layer is formed on the first tunnel barrier and has a changeable magnetization. A second tunnel barrier is formed on the free layer. A top reference layer is formed on the second tunnel barrier and has a second fixed magnetization that is opposite to the first fixed magnetization and a second thickness that is significantly smaller than the first thickness.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode and a base layer over the bottom electrode. The spin transfer torque magnetic random access memory structure further includes a fixed layer over the base layer. The fixed layer includes anti-parallel layers including cobalt tungsten/platinum (CoW/Pt) bilayers, cobalt molybdenum/platinum (CoMo/Pt) bilayers, or bilayers including a combination of at least two materials selected from cobalt (Co), tungsten (W), molybdenum (Mo), platinum (Pt), palladium (Pd) or iridium (Ir). Also, the spin transfer torque magnetic random access memory structure includes a magnetic tunnel junction (MTJ) element with a perpendicular orientation over the fixed layer and a top electrode over the MTJ element.

Abstract: Techniques for configuring the layers included in the free portion of a spin-torque magnetoresistive device are presented that allow for characteristics of the free portion to be tuned to meet the needs of various applications. In one embodiment, high data retention is achieved by balancing the perpendicular magnetic anisotropy of the ferromagnetic layers in the free portion. In other embodiments, imbalanced ferromagnetic layers provide for lower switching current for the magnetoresistive device. In various embodiments, different coupling layers can be used to provide exchange coupling between the ferromagnetic layers in the free portion, including oscillatory coupling layers, ferromagnetic coupling layers using materials that can alloy with the neighboring ferromagnetic layers, and discontinuous layers of dielectric material such as MgO that result in limited coupling between the ferromagnetic layers and increases perpendicular magnetic anisotropy (PMA) at the interface with those layers.

Abstract: Integrated circuits including memory cells and methods for operating memory cells are provided. In an embodiment, a method is provided for operating a memory including a plurality of operational memory cells. The method includes providing a word line voltage on a selected word line corresponding to a selected operational memory cell of the plurality of operational memory cells and to a corresponding reference memory cell. The method includes applying an operational bias current on an operational bit line to the selected operational memory cell. Also, the method includes scanning a reference bias current from a first value to a second value on a reference bit line to the reference memory cell. Further, the method includes comparing reference cell currents on the reference bit line with an operational cell current on the operational bit line to determine a logic state of the selected operational memory cell.

Abstract: Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory. The MRAM includes an MRAM array comprising an MRAM data array of data MRAM bit cells and an MRAM PUF array comprising PUF MRAM bit cells to form an integrated MRAM PUF array in the MRAM array. A resistance sensed from the PUF MRAM bit cells is compared to a reference resistance between the reference MRAM bit cells in the accessed MRAM bit cell row circuit in response to a read operation to cancel or mitigate the effect of process variations on MRAM bit cell resistance. The difference in sensed resistance and reference resistance is used to generate a random PUF output. By integrating the MRAM PUF array into an MRAM array containing an MRAM data array, access circuitry can be shared to control access to the MRAM data array and MRAM PUF, thus saving memory area.

Abstract: According to one embodiment, a magnetic memory includes: a memory cell including a first magnetoresistive effect element; a reference circuit including a second magnetoresistive effect element having a first resistance state and a third magnetoresistive effect element having a second resistance state; and a read circuit configured to read data in the memory cell based on a first signal based on an output from the memory cell and a second signal based on an output from the reference circuit. At a time of reading of the data, a first voltage is applied to the first magnetoresistive effect element, and a second voltage higher than the first voltage is applied to the second magnetoresistive effect element and the third magnetoresistive effect element.

Abstract: A magnetoresistive random access memory (MRAM) and associated apparatus and methods are described. The MRAM generally includes a heavy metal layer coupled to a source line, and a plurality of bit cells coupled to a word line, a plurality of bit lines, and the heavy metal layer, such that the heavy metal layer is a continuous layer coupling the bit cells to the source line, wherein each of the bit cells comprises a magnetic tunnel junction (MTJ) and a transistor, a gate of the transistor being coupled to the word line, and at least one of a source or a drain of the transistor being coupled to the MTJ or at least one of the bit lines.

Abstract: An apparatus has a reference magnetic tunnel junction with a high aspect ratio including a reference layer with magnetization along a minor axis and a storage layer with magnetization along a major axis. The storage layer magnetization is substantially perpendicular to the magnetization along the minor axis. The magnetization orientation between the minor axis and the major axis is maintained by shape anisotropy caused by the high aspect ratio.

Abstract: Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are disclosed. An MLC NVM matrix circuit includes a plurality of NVM storage string circuits that each include a plurality of MLC NVM storage circuits each containing a plurality of NVM bit cell circuits each configured to store 1-bit memory state. Thus, each MLC NVM storage circuit stores a multi-bit memory state according to memory states of its respective NVM bit cell circuits. Each NVM bit cell circuit includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector. Activation of the gate node of a given NVM bit cell circuit in an MLC NVM storage circuit controls whether its resistance is contributed to total resistance of an MLC NVM storage circuit coupled to a respective source line.

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion extending in a first direction, a first magnetic layer, and a first nonmagnetic layer provided between the first magnetic layer and a portion of the first magnetic portion. The first magnetic portion has a first surface. The first surface includes bottom portions, and top portions. The bottom portions and the top portions are arranged alternately in the first direction. The bottom portions include a first bottom portion, a second bottom portion adjacent to the first bottom portion in the first direction, a third bottom portion, and a fourth bottom portion adjacent to the third bottom portion in the first direction. The top portions include a first top portion provided between the first bottom portion and the second bottom portion, and a second top portion provided between the third bottom portion and the fourth bottom portion.

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, a first nonmagnetic layer, and a controller. The conductive layer includes first and second portions, and a third portion between the first and second portions. The conductive layer includes a first metal and boron. The first magnetic layer is separated from the third portion in a first direction crossing a second direction. The second magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first and second magnetic layers. The controller is electrically connected to the first and second portions. The controller supplies a current to the conductive layer. The first metal includes at least one selected from the group consisting of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic (SyAF) layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, SyAF layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the SyAF layers to grow in the FCC (111) direction.

Abstract: In one example, a current limited device is coupled between a source line of a memory cell array and a supply voltage, and configured to operate in a constant current mode during an access operation of a memory cell.

Abstract: A method of manufacturing a magnetoresistive random access memory cell includes the following steps. A first dielectric layer including a first metal line therein is formed on a substrate. A patterned second dielectric layer is formed over the first dielectric layer, wherein the patterned second dielectric layer includes a recess exposing the first metal line. A barrier layer conformally covers the recess and the patterned second dielectric layer. A metal fills up the recess and on the barrier layer. The metal is planarized until the barrier layer being exposed by serving the barrier layer as a stop layer. A magnetic tunneling junction and a top electrode over the metal are formed, thereby a magnetoresistive random access memory cell being formed.

Abstract: A magnetic device comprising having a first magnetic layer having a first magnetization direction, a second magnetic layer having a second magnetization direction, a first coupling layer interposed between the first and second magnetic layers, a third magnetic layer having a third magnetization direction, a first magnetoresistive layer interposed between the third magnetic layer and the second magnetic layer, and a circuit connected to one or more of the layers of the magnetic device by at least a pair of leads. The circuit is configured to determine a change in resistance between the pair of leads. The change in resistance is based at least in part on a change in an angular relationship between the third magnetization direction and the second magnetization direction caused by an external magnetic field or a current passing through at least a portion of the device.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode, a seed layer over the bottom electrode, a hard layer over the seed layer, a magnetically continuous transition layer over the hard layer, a reference layer over the magnetically continuous transition layer, a tunnel barrier layer over the reference layer, a storage layer formed over the tunnel barrier layer, and a top electrode. The reference layer, the tunnel barrier layer, and the storage layer form a magnetic tunnel junction (MTJ) element with a perpendicular orientation.

Abstract: A semiconductor storage device includes a plurality of first memory elements in a first region and a plurality of second memory elements in a second region. The second memory elements each have a physical volume that is greater than a physical volume of the first memory elements. A controller is configured to first write data to the plurality of first memory elements and then transfer the data written to plurality of first memory elements to the plurality of second memory elements when at least one of an elapsed time since initial writing or a data reading frequency exceeds a threshold value. In general, the first memory elements and the second memory elements are variable resistance elements.

Abstract: An integrated logic device includes a channel having an interconnect section and a pair of spin-orbit segments connected to the interconnect section at either end of the interconnect section. A P structure includes a P magnet disposed on a surface of a spin-orbit segment. A tunneling barrier is disposed between the P magnet and a Rp magnetic reference layer. A Q structure includes a Q magnet disposed on a surface of the other spin-orbit segment. A tunneling barrier is disposed between the Q magnet and a Rq magnetic reference layer. A method of integrated logic spin-orbit perpendicular-anisotropy (SOPE) gate device operation is also described.

Abstract: A physical unclonable function code generating method includes: providing a plurality of non-volatile memory cell pairs including a first non-volatile memory cell and a second non-volatile memory cell; comparing an initial state of the first non-volatile memory cell with an initial state of the second non-volatile memory cell, and generating a first physical unclonable function code according to a comparison result of the state; calculating a formation ratio difference of a logical level in the first physical unclonable function code; and adjusting the formation ratio difference by interactively performing forming operations on the first non-volatile memory cell and the second non-volatile memory cell when the formation ratio difference is greater than or equal to a ratio threshold.

Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.

Abstract: A Magnetic Tunnel Junction (MTJ) device can include an array of cells. The array of cells can include a plurality of source lines disposed in columns, set of selectors coupled to respective source lines, MJT structures coupled to respective selectors and a plurality of bit lines disposed in rows and coupled to respective sets of MTJ structures. The array of cells can also include buffers coupled between respective selectors and respective MTJ structures. In addition, multiple arrays can be stacked on top of each other to implement vertical three-dimensional (3D) MTJ devices.

Abstract: Various memory devices and associated methods of operation are disclosed herein. An exemplary method includes flowing a current through an electrode of a memory device. The current exerts a spin-torque for orienting a magnetic field of a magnetic layer of the memory device and produces a magnetic field in the electrode that assists in orienting the magnetic field of the magnetic layer. The current can produce the magnetic field in the electrode when flowing through a region of the electrode having a winding orientation that is substantially perpendicular to a longitudinal axis of the memory device. In some implementations, flowing the current through the electrode includes storing data in the memory device.

Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data is written and generate a second voltage, and determine data stored in the memory cell at the time of the first read based on the first voltage and the second voltage, wherein when writing the first data, the first circuit electrically sets a generation unit configured to generate the second voltage in a floating state.

Abstract: A magnetoresistive memory device includes a memory cell including a magnetic tunnel junction element, a detector to detect a current value writable in units of the memory cell, a current value storage area, and a current controller. The current value storage area stores at least one of a maximum value and a minimum value of the writable current value detected by the detector. The current controller performs at least one control operation of an operation of controlling a write current value of the memory cell based on the maximum value and an operation of controlling a read current value of the memory cell based on the minimum value.

Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.

Abstract: According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel.

Abstract: According to one embodiment, a nonvolatile memory includes a conductive line including a first portion, a second portion and a third portion therebetween, a storage element including a first magnetic layer, a second magnetic layer and a nonmagnetic layer therebetween, and the first magnetic layer being connected to the third portion, and a circuit flowing a write current between the first and second portions, applying a first potential to the second magnetic layer, and blocking the write current flowing between the first and second portions after changing the second magnetic layer from the first potential to a second potential.

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

Abstract: Disclosed herein are layered Heusler alloys. The layered Heusler alloys can comprise a first layer comprising a first Heusler alloy with a face-centered cubic (fcc) crystal structure and a second layer comprising a second Heusler alloy with a fcc crystal structure, the second Heusler alloy being different than the first Heusler alloy, wherein the first layer and the second layer are layered along a layering direction, the layering direction being the [110] or [111] direction of the fcc crystal structure, thereby forming the layered Heusler alloy.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.

Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.

Abstract: A memory cell apparatus is provided. The apparatus comprises two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ having a second magnetic characteristic and a second electrical characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The apparatus further comprises a transistor having three terminals, where the first MTJ is coupled to a first terminal of the three terminals and a metallic separator coupling the first MTJ with the second MTJ. The first MTJ and the second MTJ are arranged in series.

Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portion of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portions of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

Abstract: A memory device comprising an array of memory cells wherein each memory cell comprises a respective magnetic random access memory (MRAM) element, a respective gating transistor, and a common wordline coupled to gates of gating transistors of said array of memory cells. The memory device further comprises a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells, and a plurality of bit lines which are routed parallel to each other and connected to the drains of said gating transistors, wherein each bit line is associated with a respective memory cell of said array of memory cells.

Abstract: A memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A sacrificial circuit element is coupled to a sacrificial bit line, coupled to the common word line and coupled to the common source line, wherein the sacrificial circuit element is operable to provide a desired voltage to the common source line wherein the desired voltage originates from the sacrificial bit line.

Abstract: A semiconductor storage device includes at least two nonvolatile semiconductor memories, a buffer in which data received from a host and to be written to the nonvolatile semiconductor memories in response to a write command received from the host can be temporarily stored, and a controller connected to the nonvolatile semiconductor memories and configured to transfer data stored in the buffer to a number N of the nonvolatile semiconductor memories in parallel. The number N is set according to a reception of data from the host, and N is greater than or equal to 1 and less than or equal to m, which is the number of nonvolatile semiconductor memories connected to the controller.

Abstract: A ferromagnetic thin-film based digital memory having a plurality of bit structures interconnected with manipulation circuitry having a plurality of transistors so that each bit structure has transistors electrically coupled thereto that selectively substantially prevents current in at least one direction along a current path through that bit structure and permits selecting a direction of current flow through the bit structure if current is permitted to be established therein. A bit structure has a nonmagnetic intermediate layer with two major surfaces on opposite sides thereof and a memory film of an anisotropic ferromagnetic material on each of the intermediate layer major surfaces with an electrically insulative intermediate layer is provided on the memory film on which a magnetization reference layer is provided having a fixed magnetization direction.