Abstract: A nonvolatile memory device includes memory banks and write block circuits. Each of the memory banks includes an array of memory cells. Each of the memory cells is disposed in a region of the memory banks in which bit lines and word lines intersect. The write block circuits are connected to the memory banks. Each of the write block circuits includes write drivers, that are each connected to the bit lines. The write block circuits provide a write current of the memory cells to the bit lines. A total number of write block circuits is used to determine the number of memory banks that are simultaneously provided with a write command from a host. A total number of write drivers that are activated is based on a predetermined reference value.

Abstract: A magnetic memory including a plurality of magnetic junctions and at least one spin-orbit interaction (SO) active layer is described. Each of the magnetic junctions includes a pinned layer, a free layer and a nonmagnetic spacer layer between reference and free layers. The free layer has at least one of a tilted easy axis and a high damping constant. The tilted easy axis is at a nonzero acute angle from a direction perpendicular-to-plane. The high damping constant is at least 0.02. The at least one SO active layer is adjacent to the free layer and carries a current in-plane. The at least one SO active layer exerts a SO torque on the free layer due to the current. The free layer is switchable using the SO torque.

Abstract: Provided are a semiconductor device including a plurality of transistors and a plurality of memory cells. Each of the transistors includes a gate structure and a source/drain region. The memory cells are respectively located over the gate structures. A lower electrode of each of the memory cells and an upper electrode of an adjacent memory cell are electrically connected to the source/drain region between corresponding two transistors.

Abstract: A magnetic memory device including a plurality of magnetic units, each unit including a first and second magnetic tunnel junctions—electrically connected in series by a current line and a strap. Each junction includes a first and second storage layer having a first and second storage magnetization and a first sense magnetic layer having a first and second senses magnetization. A field line is configured to provide an input signal generating a first and second magnetic field for varying the first and second sense magnetization. Each magnetic unit is provided with a data state such that the first and second storage magnetizations are aligned in opposed directions. The first and second magnetic field are adapted for varying respectively the first and second sense magnetization in a first and second direction opposed to the first direction.

Abstract: A logic gate module for performing logic functions including a MRAM cell including a magnetic tunnel junction comprising a sense layer, a storage layer, and a spacer layer. The MRAM cell has a junction resistance determined by the degree of alignment between a sense magnetization of the sense layer and the storage magnetization of the storage layer. The storage magnetization and the sense magnetization are switchable between m directions to store data corresponding to one of m logic states, with m>2, such that the MRAM cell is usable as a n-bit cell with n?2. The logic gate module further includes a comparator for comparing the junction resistance with a reference value and outputting a digital signal indicating a difference between the junction resistance and the reference value, such that logic functions can be performed.

Abstract: A magnetic memory according to an embodiment includes: a conductive layer including a first and second terminals; a plurality of magnetoresistive elements separately disposed on the conductive layer between the first and second terminals, each magnetoresistive element including a reference layer, a storage layer between the reference layer and the conductive layer, and a nonmagnetic layer between the storage layer and the reference layer; and a circuit configured to apply a first potential to the reference layers of the magnetoresistive elements and to flow a first write current between the first and second terminals, and configured to apply a second potential to the reference layer or the reference layers of one or more of the magnetoresistive elements to which data is to be written, and to flow a second write current between the first and second terminals in an opposite direction to the first write current.

Abstract: According to one embodiment, there is provided a magnetoresistive element, including a first magnetic layer, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer, wherein one of the first and second magnetic layers include one of Co and Fe, and a material having a higher standard electrode potential than Co and Fe.

Abstract: Back gate biasing magneto-resistive random access memory (MRAM) bit cells to reduce or avoid write operation failures caused by source degeneration are disclosed. In one aspect, an MRAM bit cell includes a magnetic tunnel junction (MTJ) device and an access transistor used to control reading and writing of the MRAM bit cell. To reduce or avoid source degeneration caused by a voltage at a source region of the access transistor in response to a write operation, a back gate bias voltage is applied to a back gate electrode of the access transistor, the back gate bias voltage controlled to be greater than or equal to a back gate voltage associated with the access transistor having a nominal threshold voltage corresponding to operation without source degeneration plus a voltage corresponding to the source region of the access transistor.

Abstract: A magnetic memory includes: a first and second terminals; a conductive layer including first to fourth regions, the first and fourth regions being electrically connected to the first and second terminals respectively; a first magnetoresistive element including: a first and second magnetic layers; a first nonmagnetic layer between the first and second magnetic layers; and a third terminal electrically connected to the first magnetic layer; a second magnetoresistive element including: a third and fourth magnetic layers; a second nonmagnetic layer between the third and fourth magnetic layers; and a fourth terminal electrically connected to the third magnetic layer; and a circuit configured to apply a write current between the first terminal and the second terminal and apply a first and second potentials to the third and fourth terminals respectively to write the first and second magnetoresistive elements, the first and second potentials being different from each other.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate including a first region and a second region separated from the first region; an interlayer dielectric layer formed over the substrate including first and second regions; a first contact plug located over the first region and formed through the interlayer dielectric layer; a second contact plug located over the second region and formed through the interlayer dielectric layer, wherein the first and the second contact plugs having different structures in the first and second regions, respectively; and a variable resistance element formed over the interlayer dielectric layer over the first region so as to be in contact with the first contact plug.

Abstract: Aspects of a biosensor platform system and method are described. In one embodiment, the biosensor platform system includes a fluidic system and tunneling biosensor interface coupled to the fluidic system. The tunneling biosensor interface may include a transducing electrode array having at least one dielectric thin film deposited on an electrode array. The biosensor platform system may further include processing logic operatively coupled to the transducing electrode array. In operation, the application of an electromagnetic field at an interface between an electrode and an electrolyte in the system, for example, may result in the transfer of charge across the interface. The transfer of charge is, in turn, characterized by electromagnetic field-mediated tunneling of electrons that may be assisted by exchange of energy with thermal vibrations at the interface. By analysis of the transfer of charge, the identify of various analytes, for example, or other compositions.

Abstract: In one example, a current limited device is coupled between a source line of a memory cell array and a supply voltage, and configured to operate in a constant current mode during an access operation of a memory cell.

Abstract: According to one embodiment, a magnetic memory includes: a first magnetoresistive effect element having a first resistance state or a second resistance state; and a read circuit. A read circuit is configured to apply the first read voltage to the first magnetoresistive effect element, hold a first charging potential caused by the first read voltage, apply a second read voltage higher than the first read voltage to the first magnetoresistive effect element, hold a second charging potential caused by the second read voltage, and determine whether the first magnetoresistive effect element is in the first resistance state or the second resistance state based on a comparison result between the first charging potential and the second charging potential.

Abstract: A circuit for calculating power consumption of a phase change memory (PCM) device may be provided. The circuit may include a plurality of pipelines and an arithmetic logic circuit. The plurality of pipelines may be configured to correspond to a plurality of write periods exhibiting different power consumption values during a write operation of the PCM device executed by a write command. The plurality of pipelines may shift or transmit data in synchronization with a clock signal. The arithmetic logic circuit may be configured to perform an adding operation of all of deviations of the power consumption values at a point of time that data transmission between at least two of the plurality of pipelines occurs, to thus generate a total power consumption value.

Abstract: A three-dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes.

Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.

Abstract: The invention relates to a three dimensional magnetic memory device (1) employing pure spin currents to write information into magnetic bits. The magnetic memory device (1) is formed of one or more stack of two storage layers (13) placed between two reference layers (9). The stacks are connected to each other through common reference electrodes (12) formed by connecting reference electrodes (11) placed on bottom of a first stack and on top of the second stack positioned under the first stack.

Abstract: A bit line sense amplifier with an enhanced sensing margin is provided. The bit line sense amplifier includes a sensing amplification circuit connected to a bit line and a complementary bit line and configured to sense a voltage change of the bit line and adjust voltages of a sensing bit line. Also provided is a complementary sensing bit line based on the sensed voltage change, wherein the sensing amplification circuit includes a first transistor connected between the complementary sensing bit line and a first high-voltage node and controlled by the voltage change of the bit line. A second transistor is connected between the sensing bit line and a second high-voltage node and controlled by a voltage change of the complementary bit line.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: Technologies for a physically unclonable function with magnetic tunnel junctions (MTJs) is disclosed. An MTJ may have a fixed layer and a free layer. The MTJ may have two stable states: one in which the orientation of the magnetization of the fixed layer is parallel to the free layer, and one in which it is antiparallel. If the magnetic tunnel junction has a voltage-controlled magnetic anisotropy, when a voltage is applied across the MTJ, the orientation of the magnetic field of the free layer of the MTJ may be perpendicular to that of the fixed layer. When the voltage is removed, the orientation of the magnetization of the free layer relaxes back to one of the two stable configurations. Which state the free layer ends up at may not be predictable at the time of manufacture, but may be repeatable due to influences from variations in the manufacturing process.

Abstract: A device is disclosed that includes a driver, a sinker and a memory column. The memory column includes a plurality of resistive memory cells each being electrically connected between the driver and the sinker through a first line and a second line. When one of the resistive memory cells is conducted, at least one of the driver and the sinker is configured to be controlled to have a resistance depending on a row location of the conducted resistive memory cell in the memory column.

Abstract: According to one embodiment, an operation program of a nonvolatile semiconductor memory device includes: a first step for determining whether data has been sufficiently written to all of a plurality of addresses to which data is to be written; and a second step for writing data to an address to which data has not been sufficiently written among the plurality of addresses to which data is to be written and not writing data to an address to which data has been sufficiently written. The first step and the second step are repeated a predetermined number of times.

Abstract: A magnetic tunnel junction based memory device comprising a magnetic tunnel junction element and writing circuitry. The magnetic tunnel junction element includes a free layer, a pinned layer, and a tunnel barrier. The free layer is spaced apart along a vertical direction from the pinned layer by the tunnel barrier. The writing circuitry is configured to receive an instruction to set the magnetic tunnel junction element to a target state of three of more states of the magnetic tunnel junction element and provide electrical current to modify a position of a domain wall of the free layer along both a first horizontal direction and a second horizontal direction to correspond to the target state.

Abstract: In one implementation, an electronic device is provided to include a semiconductor memory, wherein the semiconductor memory may include: a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a changeable magnetization direction free layer, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, and the electronic device may further include, in a first direction in which the free layer, the tunnel barrier layer and the pinned layer are arranged, a first permanent magnet having a first surface facing a first surface of the variable resistance element and spaced from the variable resistance element, wherein a magnetic field generated by the first permanent magnet may have a direction which offsets or reduces an influence of a stray field generated by the pinned layer.

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.

Abstract: According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.

Abstract: According to one embodiment, a magnetoresistive memory device, includes first wirings arranged parallel to each other in or on a substrate, second wirings arranged parallel to each other above the substrate to cross the first wirings when viewed in a direction perpendicular to a surface of the substrate, and magnetoresistive elements provided corresponding to intersections of the first and second wirings, respectively, and divided into layers.

Abstract: A magnetoresistive effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic metal layer interposed between the first ferromagnetic layer and the second ferromagnetic layer. The first ferromagnetic layer and the second ferromagnetic layer include a Heusler alloy consisting of a CoMnSi alloy. A ratio x of Mn with respect to Co2 in each of the first ferromagnetic layer and the second ferromagnetic layer is 0.7?x?1.7. Compositions of the first ferromagnetic layer and the second ferromagnetic layer are different from each other.

Abstract: According to one embodiment, a semiconductor memory device comprises: first to fourth memory cells, each of which is configured to have a first resistance state or a second resistance state; and a first circuit configured to output first data based on a first signal representing a resistance state of the first memory cell and a second signal representing a resistance state of the second memory cell, output second data based on the second signal and a third signal representing a resistance state of the third memory cell, and output third data based on the third signal and a fourth signal representing a resistance state of the fourth memory cell.

Abstract: Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing. Including precharging in the sense amplifiers used to access the memory cells enables self-referenced read operations to be completed more quickly than is possible without precharging. Similarly, precharging can also be used in conjunction with write-back operations in order to allow the data state stored by magnetic tunnel junctions included in the memory cells to be changed more rapidly.

Abstract: A complementary bit cell includes a first magnetic tunnel junction (MTJ) device having a free layer coupled to a first access transistor and having a pinned layer coupled to a bit line. The complementary bit cell also includes a second MTJ device having a free layer coupled to the same bit line and having a pinned layer coupled to a second access transistor.

Abstract: The present invention is directed to a spin-orbitronics device including an array of MTJs with each of the MTJs coupled to a respective one of a plurality of selection transistors; a plurality of transverse polarizing lines with each of the transverse polarizing lines coupled to a row of the MTJs along a first direction; a plurality of word lines with each of the word lines coupled to gates of a row of the selection transistors along a second direction; and a plurality of source lines with each of the source lines coupled to a row of the selection transistors along a direction substantially perpendicular to the second direction. Each MTJ includes a magnetic comparison layer structure having a pseudo-invariable magnetization direction, which is configured to switch between two stable states by passing a comparison current through one of the plurality of transverse polarizing lines formed adjacent to the magnetic comparison layer structure.

Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction resides on a substrate and is usable in a magnetic device. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The free layer has a free layer perpendicular magnetic anisotropy energy greater than a free layer out-of-plane demagnetization energy. The free layer also includes a diluted magnetic layer having an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy greater than the out-of-plane demagnetization energy. The diluted magnetic layer includes at least one magnetic material and at least one nonmagnetic material. The diluted magnetic layer has an exchange stiffness that is at least eighty percent of an exchange stiffness for the magnetic material(s).

Abstract: Higher word line voltages facilitate write operations in spin-torque magnetic memory devices, but overdriving the gate of a selection transistor with such higher word line voltages can damage the selection transistor if the gate-to-source voltage for the selection transistor is too high. Therefore in order to support the word line voltage needed on the gate of the select transistor for an up-current write operation without exceeding limits on the gate-to-source voltage for the select transistor, the gate of the selection transistor can be driven in a two-step process. The gate of the selection transistor is first driven to a lower voltage within the limits of the gate-to-source voltage for the transistor when the source of the transistor is grounded or at a voltage near ground. A voltage is then applied across the memory cell, which results in the source of the selection transistor being raised above its initial ground or near-ground state.

Abstract: A magnetic sensor cell includes a magnetic tunnel junction including a reference layer having a reference magnetization oriented parallel to the plane of the reference layer, a sense layer having a sense magnetization, and a tunnel barrier layer between the sense and reference layers. A magnetic device is configured for providing a sense magnetic field for aligning the sense magnetization. The sense layer magnetization is orientable between a direction parallel to the plane of the sense layer and a direction perpendicular to the plane of the sense layer when the sense magnetic field is provided. The magnetic sensor cell can be used for sensing an external magnetic field including a component oriented parallel to the plane of the sense layer and a component oriented perpendicular to the plane of the sense layer.

Abstract: A determination can be made as to whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.

Abstract: A spin electronic memory of the present invention includes: a pair of electrodes 1, 2, recording layers 6a, 6b, and 6c between the electrodes 1 and 2, the recording layer being formed by laminating first alloy layer 5 and second alloy layer 4, the first alloy layer 5 being formed to contain any one of SbTe, Sb2Te3, BiTe, Bi2Te3, BiSe, and Bi2Se3 as a principal component and to have a thickness of 2 nm to 10 nm, the second alloy layer 4 being formed to contain an alloy expressed by general formula (1) as a principal component; and spin injection layer 7 formed with a magnetic material to inject a spin into the recording layer with the magnetic material being magnetized, M1-xTex??(1) where M represents an atom selected from atoms of Ge, Al, and Si, and x represents a value of 0.5 or more and less than 1.

Abstract: A magnetic memory of an embodiment includes: a first to third terminals; a magnetoresistive element including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second nonmagnetic layer including a first to third portions, the first portion being located between the second and the third portions, the second and third portions being electrically connected to the second and third terminals respectively, the first magnetic layer being disposed between the first portion and the first nonmagnetic layer; and a third nonmagnetic layer including a fourth to sixth portions, the fourth portion being located between the first portion and the first magnetic layer, the fifth portion including a first region extending from the magnetoresistive element to the second terminal, the sixth portion including a second region extending from the magnetoresistive element to the third terminal.

Abstract: Robust magnetoelectric junctions (MEJs) are disclosed. In one embodiment, an MEJ includes: a first fixed layer; a free layer; a seed layer; a cap layer; and a dielectric layer disposed between the first fixed layer and the free layer; where: one of the seed layer and the cap layer is disposed adjacently to a ferromagnetic layer; the first fixed layer is magnetized in a first direction; the free layer can adopt a magnetization direction that is either substantially parallel with or substantially antiparallel with the first direction; when a potential difference is applied across the MEJ, the coercivity of the free layer is reduced for the duration of the application of the potential difference; and at least one of the seed layer and the cap layer includes one of: Molybdenum, Tungsten, Iridium, Bismuth, Rhenium, and Gold.

Abstract: A spin-torque oscillator includes: a driving reference layer having a fixed magnetization; a nonmagnetic spacer layer; and a free layer having a changeable magnetization exhibiting an easy-cone magnetic anisotropy, the nonmagnetic spacer layer being between the driving reference layer and the free layer, a magnetic anisotropy energy of the free layer having a local maximum along an axis, a local minimum at an angle from the axis, and a global maximum different from the local maximum, the angle being greater than zero degrees, wherein the spin-torque oscillator is configured such that the changeable magnetization of the free layer precesses around the axis.

Abstract: Embodiments are directed to a magnetic tunnel junction (MTJ) memory cell that includes a reference layer formed from a perpendicular magnetic anisotropy (PMA) reference layer and an interfacial reference layer. The MTJ further includes a free layer and a tunnel barrier positioned between the interfacial reference layer and the free layer. The tunnel barrier is configured to enable electrons to tunnel through the tunnel barrier between the interfacial reference layer and the free layer. A first in-situ alignment is provided between a tunnel barrier lattice structure of the tunnel barrier and an interfacial reference layer lattice structure of the interfacial reference layer. A second in-situ alignment is provided between the tunnel barrier lattice structure of the tunnel barrier and a free layer lattice structure of the free layer. The PMA reference layer lattice structure is not aligned with the interfacial reference layer lattice structure.

Abstract: A magneto-resistance random access memory (MRAM) cell includes a transistor, a wire and a magnetic tunnel junction (MTJ). The MTJ includes a fixed layer of fixed magnetic polarity electrically connected with the transistor, a free layer of variable magnetic polarity electrically connected with the wire and an insulator between the fixed and free layers. First current passed through the wire destabilizes the variable magnetic polarity of the free layer. Second current passed through the transistor in one of two directions during first current passage through the wire directs the variable magnetic polarity of the free layer toward a parallel or anti-parallel condition with respect to the fixed magnetic polarity of the fixed layer. A ceasing of the first current prior to a ceasing of the second current sets the variable magnetic polarity of the free layer in the parallel or anti-parallel condition.

Abstract: Data is initially programmed in a portion of ReRAM in parallel. Subsequently, one or more ReRAM cells in the portion are determined to contain first data that is to be modified while remaining ReRAM cells in the portion contain second data that is not to be modified. First conditions are applied to the one or more ReRAM cells thereby modifying the first data, while second conditions are applied to the remaining ReRAM cells, the second conditions maintaining the second data in the remaining ReRAM cells without significant change.

Abstract: Three-terminal magnetic circuits and devices based on the spin-transfer torque (STT) effect via a combination of injection of spin-polarized electrons or charged particles by using a charge current in a spin Hall effect metal layer coupled to a free magnetic layer and application of a gate voltage to the free magnetic layer to manipulate the magnetization of the free magnetic layer for various applications, including nonvolatile memory functions, logic functions and others. The charge current is applied to the spin Hall effect metal layer via first and second electrical terminals and the gate voltage is applied between a third electrical terminal and either of the first and second electrical terminals. The spin Hall effect metal layer can be adjacent to the free magnetic layer or in direct contact with the free magnetic layer to allow a spin-polarized current generated via a spin Hall effect under the charge current to enter the free magnetic layer.

Abstract: A magnetoresistive effect device includes at least one magnetoresistive effect element including a magnetization fixed layer, a spacer layer, and a magnetization free layer, a first port, a second port, a first signal line which is connected to the first port and through which high-frequency current corresponding to a high-frequency signal input into the first port flows, a second signal line, and a direct-current input terminal. The magnetoresistive effect element is arranged so that a high-frequency magnetic field occurring from the first signal line is applied to the magnetization free layer. The magnetoresistive effect element is connected to the second port via the second signal line. The direct-current input terminal is connected to the magnetoresistive effect element.

Abstract: Devices and methods for determining resistive states of resistive change elements in resistive change element arrays are disclosed. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements by sensing current flow. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements without the need for in situ selection devices or other current controlling devices. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can reduce the impact of sneak current when determining resistive states of resistive change elements.

Abstract: A magnetoresistive memory device includes a variable resistance element and a read circuit. The resistance element has a resistance state, which is one of switchable first and second resistance states. The first and second resistance states exhibit different resistances. Each of the first and second resistance states is reached by a current flowing through the variable resistance element in one of opposing first and second directions. The read circuit passes a read current through the variable resistance element autonomously in the first or second direction in accordance with the resistance state of the variable resistance element.

Abstract: Perpendicular magnetic anisotropy (PMA) type magnetic random access memory cells are constructed with a composite PMA layer to provide a magnetic tunnel junction (MTJ) with an acceptable thermal barrier. A PMA coupling layer is deposited between a first PMA layer and a second PMA layer to form the composite PMA layer. The composite PMA layer may be incorporated in PMA type MRAM cells or in-plane type MRAM cells.

Abstract: Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory bit-cell via access devices; a second sense amplifier coupled to the first sense amplifier and to the complementary resistive memory bit-cell via the access devices, wherein the second sense amplifier is operable to detect an error in the complementary resistive memory bit-cell.

Abstract: According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data “0” and data “1” in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance middle at a level in between an admittance of a variable resistance element storing data “0” and an admittance of a variable resistance element storing data “1”, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.