Abstract: Disclosed is an improved sense amplifier/bit driver circuit including first and second transistors connected in a current mirror configuration. A bit line connected to a plurality of memory cells is connected to the collector of the first of the two transistors while the second of the transistors provides an output at its collector. A current source is connected to the base regions of both the first and second transistors for supplying current when a bit line is to be selected. Current flow through the second transistor is supplied to additional circuitry including a driver circuit, a clamping circuit and a zero filter circuit. Also disclosed is a reference voltage generator which accurately tracks the sense amplifier circuit and provides a reference voltage at or near the midpoint between a binary 1 and binary 0 level. The sense amplifier substantially senses current rather than voltage and also acts as a high power over driven bit driver.
Type:
Grant
Filed:
August 21, 1978
Date of Patent:
April 1, 1980
Assignee:
International Business Machines Corporation
Abstract: The present invention relates to a memory circuit including an array of inversion controlled switches arranged in an arbitrary number of rows and columns. Each inversion controlled switch is provided with emitter, base and collector terminals, and is characterized by first and second impedance states between its emitter and collector terminals.
Abstract: A static RAM cell, including two vertical, multiple-Schottky-collector switching transistors wherein a first collector of each is coupled to first and second sources of read/write data, respectively, and wherein a second collector of each transistor is cross-coupled with the base of the other transistor. The cell is implemented with I.sup.2 L technology, and also includes a complementary inverted multiple-collector NPN load transistor having its base electrically common with the emitters of the switching transistors, a first collector merged with the base of one switching transistor, and a second collector merged with the base of the other switching transistor.
Abstract: A surface acoustic wave device utilizing a piezoelectric substrate capable of propagating traveling acoustic waves along a surface thereof and a semiconductive substrate positioned adjacent such surface, the latter substrate having an array of diodes, preferably Schottky diodes, disposed in the surface thereof opposite the piezoelectric substrate to form an interaction region. Application of a signal uniformly over the interaction region will charge the diodes uniformly and a traveling acoustic wave will interact with the uniformly applied signal to alter the charging pattern of the array in accordance with the acoustic wave amplitude to produce a corresponding altered conductivity pattern in the semiconductor substrate representing the interaction of the uniformly applied signal and the traveling wave signal.
Type:
Grant
Filed:
May 27, 1976
Date of Patent:
July 18, 1978
Assignee:
Massachusetts Institute of Technology
Inventors:
Kjell A. Ingebrigtsen, Abraham Bers, John H. Cafarella
Abstract: The invention relates to a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases.This is accomplished through coupling the storage cell to both read/write circuits and restore/recovery circuits via the bit lines and by selective pulsing of the cell with the read/write circuits and the restore/recovery circuits.This permits high speed, low operating current, large scale memory systems to be built.
Type:
Grant
Filed:
March 1, 1976
Date of Patent:
May 16, 1978
Assignee:
International Business Machines Corporation
Inventors:
Horst H. Berger, Klaus Heuber, Wilfried Klein, Knut Najmann, Siegfried Wiedmann
Abstract: A bipolar read-only memory comprising a matrix circuit having selection input lines, digit output lines and Schottky barrier diodes connected between the selection input lines and the digit input lines according to information contained in the memory, a selection input circuit of an I.sup.2 L construction electrically associated with the selection input lines and a digit output circuit of an I.sup.2 L construction electrically associated with the digit output lines.
Abstract: A surface acoustic wave device utilizing a piezoelectric substrate capable of propagating traveling acoustic waves along a surface thereof and a semiconductive substrate positioned adjacent such surface, the latter substrate having an array of Schottky diodes and associated islands of highly resistive material, such as polycrystalline silicon material, disposed in the surface thereof opposite the piezoelectric substrate to form an interaction region. Application of a signal uniformly over the interaction region will charge the diodes uniformly and an acoustic wave traveling along a selected surface of the piezoelectric substrate will interact with the uniformly applied signal to alter the charging pattern of the Schottky diode array in accordance therewith to produce a corresponding altered conductivity pattern stored in the semiconductor substrate and representing the interaction of the uniformly applied signal and the traveling wave signal.