Abstract: A read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions, which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.

Abstract: An integrated circuit (IC) has a number of memory cells, each of which has a diode structure coupled between a bitline and a wordline that are selected when programming that cell. A target memory cell of the IC is programmed while simultaneously floating a number of unselected bitlines and wordlines in the IC.

Abstract: An electrically addressable device for recording, addressing and reading of data, includes a storage array unit having multiple layers of data storage medium. An electrical marking device is disposed on at least one of the layers of storage medium of the storage array unit to provide a display indicating any pre-selected information, such as the nature of the content of the data stored on the storage array unit. The electrical marking device may comprise at least one layer functioning as a display layer that is partially visually altered to provide a display of information, such as to display the subject matter and name of the content of the data and the amount of memory storage that has been used. The display layer comprises a plurality of information storage cells, each representing the value of at least one data bit, wherein the visual appearance of each of the information storage cell is varied depending on the value of the data bit.

Abstract: Each memory cell of a cell configuration includes at least one memory transistor. To write first or second information on the memory cell, a gate electrode of the memory transistor is charged such that a first voltage or a second voltage is applied in the memory transistor. A reading voltage is applied in a second source/drain area of the memory transistor to read first information and second information respectively. The first voltage is applied between the second voltage and the reading voltage. The reading voltage is applied between the first voltage less a threshold voltage of the memory transistor and the second voltage less the threshold voltage of the memory transistor.

Abstract: In nonvolatile memory capable of erasing, writing and reading data, simplified in structure of memory cells, and enabling high-density information recording, each memory cell is composed of a thin film phase change material having two stable phases, “high-temperature phase” and “low-temperature phase” under the room temperature, and an np junction made by a p+-type region and an n+-type region, serially connected to the thin film phase change material. By applying a predetermined voltage to the upper electrode and the lower electrode to have a current flow in a memory cell (MC1l) and change the phase of the thin film phase change material, data is written. By flowing a current in the memory cell (M1l) and thereby reading the current phase of the thin film phase change material, data is read out.

Abstract: Systems and methods that enable the state of a memory cell to be determined with greater accuracy are described. In one memory cell sensing approach, a memory cell is addressed, an input signal is applied to the addressed memory cell over a range of values, and the state of the memory cell is read based upon a discontinuity in a sensed electrical response to the applied input signal values.

Abstract: The invention relates to a damascene chalcogenide memory cell structure. The damascene chalcogenide memory cell structure is fabricated under conditions that simplify previous process flows. The damascene chalcogenide memory cell structure also prevents volatilization of the chalcogenide memory material.

Abstract: Each memory cell of a cell configuration includes at least one memory transistor. To write first or second information on the memory cell, a gate electrode of the memory transistor is charged such that a first voltage or a second voltage is applied in the memory transistor. A reading voltage is applied in a second source/drain area of the memory transistor to read first information and second information respectively. The first voltage is applied between the second voltage and the reading voltage. The reading voltage is applied between the first voltage less a threshold voltage of the memory transistor and the second voltage less the threshold voltage of the memory transistor.

Abstract: The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.

Abstract: A static random access memory (SRAM) cell is formed by a tunnel switched diode (TSD) and a pair of transistors. The TSD has a characteristic I-V curve exhibiting a negative differential resistance region that allows the TSD to function as a bi-stable storage device. NMOS and PMOS transistors coupled between the TSD and word and bit lines function to access the TSD for purposes of address, read and write functions of the cell. The cells can be connected in high density, high performance arrays. The TSD's are formed from layered materials that result in small cell size while allowing for high level of cell current.

Abstract: A memory circuit includes a cross-point memory array having first and second sets of transverse electrodes with respective memory elements formed at the crossing-points of the first and second set electrodes. Each of the memory elements is formed to include, in at least one of its binary states, a diode element. The memory circuit also includes an addressing circuit coupled to the memory array. The addressing circuit has a first set of address lines with first diode connections between the first set address lines and the first set memory array electrodes, with the first diode connections coupling each memory array electrode in the first set to a respective unique subset of the first set address lines.

Abstract: CMOS semiconductor latch and register (500) circuitry is disclosed, comprising a first tunneling structure latch circuit (502); data input circuitry (506), coupled and adapted to pass data to (504) said first tunneling structure latch circuit (502), a second tunneling structure latch circuit (514), data transmission circuitry (516), coupled between said first and second tunneling structure latch circuits, and adapted to transfer data from said first tunneling structure latch circuit to said second tunneling structure latch circuit, and data output circuitry (518), coupled to (512) said second tunneling structure latch circuit (514).

Abstract: A molecular-wire crossbar interconnect for signal routing and communications between a first level and a second level in a molecular-wire crossbar is provided. The molecular wire crossbar comprises a two-dimensional array of a plurality of nanometer-scale switches. Each switch is reconfigurable and self-assembling and comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting the pair of crossed wires in the junction. The connector species comprises a bi-stable molecule. Each level comprises at least one group of switches and each group of switches comprises at least one switch, with each group in the first level connected to all other groups in the second level in an all-to-all configuration to provide a scalable, defect-tolerant, fat-tree networking scheme. The primary advantage is ease of fabrication, because an active switch is formed any time two wires cross.

Abstract: A negative resistance device (NRD) has a MOSFET-like structure, and is biased by shorting the gate and source together at a fixed applied potential and applying a different fixed potential to the drain, and sweeping the bulk potential towards the drain potential, causing the bulk current to exhibit a negative resistance characteristic. The NRD may be used in a memory circuit (10) in which a resistor (R) is connected between the bulk (2) and a fixed potential. Two States of the circuit at which the current through the resistor matches that through the bulk of the NRD are stable, providing for bistable memory operation.

Abstract: A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (Vf) of the tunnel diode (32) controls the Vgs transfer curve (56) of the load transistor. The tunnel diode (32) may be formed at a junction between a mono-crystalline silicon layer (88) at a region (98, 100) which also serves as a source or drain of a transistor (36, 54) and a poly-crystalline silicon layer (106). The poly-crystalline silicon layer (106) also serves as a non-metallic, conductive interconnection (55) to save space.

Abstract: A spin injected diode suitable for nonvolatile memory applications is made of a semiconducting channel capable of carrying current, a single ferromagnetic layer, and a barrier layer between the semiconducting channel and the ferromagnetic layer to protect the integrity of the semiconducting layer and to inhibit interdiffusion of the ferromagnetic material and the semiconductor. During diode readout the output modulation of the diode can be sensed either as the interface resistance between the semiconducting channel and the ferromagnetic layer, or as the output voltage between the semiconducting channel and the ferromagnetic layer when flowing current through the channel and not through the interface. Two of these spin injected diodes can be combined to form a spin injected field effect transistor. This transistor has a first ferromagnetic layer having a first coercivity and a second ferromagnetic layer having a second coercivity smaller than the first coercivity which are spaced apart.

Abstract: A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE<ICB according to a voltage applied across a base and emitter where IBE is the base current flowing through a base-emitter path in a forward direction, and ICB is the base current flowing through a collector-base path in a reverse direction.

Abstract: A two-dimensional memory comprises a matrix of multi-valued resonant tunneling diodes (RTD). Each memory cell has two series RTDs with hysteretic folding V-I characteristics. The memory state is determined by the node voltage between the two RTDs and the series current. Each memory cell has two terminals connected to two bit lines through word line switches. The two bit lines are fed with two sets of multi-valued data and are written into the cell by two consecutive pulses to set the operating point. The two sets of multi-valued data are converted by two D/A converters from two sub-words of the binary digital word. The memory state is read by the sensing the voltages at the two terminals, or voltage at one terminal and the current through the other terminal.

Abstract: Provided is a semiconductor memory cell which requires no refreshing operation for retaining information. The semiconductor memory cell comprises a first transistor TR1 having a first conductivity type, a second transistor TR2 having a second conductivity type and a MIS type diode DT for retaining information, wherein one source/drain region of the first transistor TR1 corresponds to the channel forming region CH2 of the second transistor TR2, one source/drain region of the second transistor TR2 corresponds to the channel forming region CH1 of the first transistor TR1, one end of the MIS type diode DT is formed of an extending portion of the channel forming region CH1 of the first transistor TR1, and the other end of the MIS type diode DT is constituted of an electrode which is formed of an electrically conductive material and connected to a third line having a predetermined potential.

Abstract: A SRAM memory cell including two tunnel diodes coupled in series and a MOS FET. A first of the tunnel diodes may be formed in a shallow trench. A second of the tunnel diodes may be formed in a source or drain contact region of the FET. The FET acts as a pass gate to allow data to be read from or written to the memory cell when the gate of the FET is biased to turn the FET ON. The FET otherwise acts to prevent the datum stored in the memory cell from being altered when the FET is turned OFF. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.

Abstract: A magnetic random access memory circuit comprises first and second row decoders receiving a part of a given address, first and second column decoders receiving the other part of a given address, a plurality of pairs of sense lines connected between output terminals of the first row decoder and output terminals of the second row decoder, each pair of sense lines being located adjacent to each other, a plurality of word lines connected between output terminals of the first column decoder and output terminals of the second column decoder, and extending to intersect the sense lines so that intersections of the sense lines and the word lines are located in the form of a matrix. A memory array includes a plurality of cell pairs distributed over the matrix, each cell pair including a memory cell and a reference cell located adjacent to each other. Each of the memory cell and the reference cell includes a magneto-resistive element.

Abstract: A static memory cell having no more than three transistors. A static memory cell comprises a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain; and alternating layers of insulative and conductive material formed proximate the source, including two conductive layers and two insulative layers, one of the insulative layers being in junction relation to the source.

Abstract: The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.

Abstract: The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.

Abstract: The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.

Abstract: A semiconductor device of the present invention is a semiconductor device of a complementary MIS field effect transistor, wherein an anode of a first diode is connected to a silicon substrate of a first conduction type while a cathode of the first diode is connected to a first power supply while a cathode of a second diode is connected to a well of the other conduction type and an anode of the second diode is connected to a second power supply.

Abstract: The present invention provides a semiconductor memory capable of retaining information after removing a power supply and of storing information with an optical input. A memory cell is comprising an n-InP substrate, a first semiconductor (n-InGaAs) layer, a second semiconductor (i-InGaAs) layer, a third semiconductor (p-InGaAs) layer, a fourth semiconductor (i-InGaAs) layer and a fifth semiconductor (n-InGaAs) layer. The first to fifth semiconductor layers are stacked in this order on the n-InP substrate. A bias voltage is applied between the n-InP substrate and the fifth semiconductor layer to control a height of a TBD formed in the above multi-layer structure so that carriers may move and electrons can be stored in one of the second and fourth semiconductor layers.

Abstract: Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes gates which are pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.

Abstract: A non-volatile semiconductor memory device is provided with a circuit that protects a tunnel oxide film from the charging phenomenon. This circuit comprises a first junction diode including an N.sup.+ -type diffusion layer and a P-type well, and a second junction diode including a P-type well and an N-type well. When a voltage applied to the control gate is greater than all of a write voltage, a read voltage, and an erasure voltage that would be applied to the control gate, a current is guided through that circuit.

Abstract: Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.

Abstract: A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (V.sub.f) of the tunnel diode (32) controls the V.sub.gs transfer curve (56) of the load transistor.

Abstract: Quantum random address memory apparatus including a low dimensional plurality of address ports, a plurality of nano-memory elements, nano-diodes coupling the address ports to a high dimensional plurality of the plurality of nano-memory elements, and data output ports and structure coupled to the plurality of nano-memory elements. The high dimensional plurality of nano-memory elements is greater than the low dimensional plurality of address ports by a number resulting in substantially error free memory recalls.

Abstract: A SEU hardening circuit for use with a data storage circuit is described. The SEU hardening circuit may use a transmission gate to provide full rail drive during a write operation. The SEU hardening circuit may also be configured so that the transistors of the SEU hardening circuit are not susceptible to parasitic bipolar turn-on particularly during a radiation event, which can increase the SEU protection provided by the circuit.

Abstract: An electrically addressable passive device for registration, storage and/or processing of data comprises a functional medium (1) in the form of a continuous or patterned structure (S) which may undergo a physical or chemical change of state. The functional medium (1) comprises individually addressable cells (2) which represent a registered or detected value or are assigned a predetermined logical value for the cell. The cell (2) is provided between the anode (3) and cathode (4) in an electrode means (E) which contacts the function medium in the cell and causes an electrical coupling therethrough, the functional medium having a non-linear impedance characteristic, whereby the cell (2) directly can be supplied with energy which effects a change in the state of the cell. In a method for electrical addressing of the passive device wherein the addressing comprises operations for i.a.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: Quantum random address memory apparatus including a low dimensional plurality of address ports, a plurality of nano-memory elements, mixer elements coupling the address ports to a high dimensional plurality of the plurality of nano-memory elements, and data output ports and structure coupled to the plurality of nano-memory elements. The high dimensional plurality of nano-memory elements is greater than the low dimensional plurality of address ports by a number resulting in substantially error free memory recalls.

Abstract: The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.

Abstract: A semiconductor device of the present invention is a semiconductor device of a complementary MIS field effect transistor, wherein an anode of a first diode is connected to a silicon substrate of a first conduction type while a cathode of the first diode is connected to a first power supply while a cathode of a second diode is connected to a well of the other conduction type and an anode of the second diode is connected to a second power supply.

Abstract: A variable resistance material-based memory cell is disclosed for use in an electronic memory. The memory cell includes a MOS diode for delivering large amounts of current to the variable resistance material, as needed during programming of the memory cell. In one embodiment, a buried contact under the gate is used as the drain of the device. The buried contact allows formation of a very short channel, causing a "snapback" phenomenon in the MOS diode and thereby greatly increasing the amount of current flow across the device. This buried contact construction has the additional advantage of reducing the area needed for the memory cell. Additionally, the processing is simple and may be performed using the same techniques normally used during the fabrication of electronic memories.

Abstract: Provided is a semiconductor device, including: a semiconductor substrate; a first conductive type well which is formed on the semiconductor substrate; first and second field oxide layers which are formed on the well, defining the active region of the device; a node junction, where second conductive type impurity ions are heavily doped, making contact with the field oxide layer in the well; a gate electrode formed by interposing a gate oxide layer between the second field oxide layer and the node junction on the well; a switching device made from an interlevel insulating layer, for covering the gate electrode, and having a contact hole exposing the node junction on the semiconductor substrate; a storage electrode which makes contact with the node junction through the contact hole; a dielectric layer formed on the storage electrode; and a memory device made of a plate electrode which is formed on the dielectric layer.

Abstract: The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.

Abstract: A read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented. The diode-based structure also allows the packing density of the memory cells on the ROM device to be dependent on the line width of the polysilicon layers in the ROM device.

Abstract: A mask ROM is so configured as to read out information through the utilization of a cumulative time delay involved when a read-out signal applied to memory elements making connection between a word line WL1 and bit lines BL1 crossing the word line is passed through delay elements R1 to R7, that is, as to read out stored information on a time base, in which the conductions of switching transistors T1 to T8 are controlled by the outputs of the delay elements R1 to R7 and the information appearing at the bit line BL1 is sequentially read out at a predetermined time corresponding to a time delay resulting from the delay elements R1 to R7.

Abstract: In a semiconductor memory including first and second bit lines complementary to each other and provided for each one memory cell column, and a sense amplifier connected to the first and second bit lines, for sensing and amplifying a voltage difference between the first and second bit lines, a first pull-up circuit is connected to the first bit line, for pulling up, in accordance with a potential of the second bit line, the first bit line to a high voltage supply potential. A second pull-up circuit is connected to the second bit line, for pulling up, in accordance with a potential of the second bit line, the second bit line to a high level potential lower than that the high voltage supply potential by a predetermined potential difference.

Abstract: A memory system is organized as a matrix including a memory cell at each intersection of a bit line with write and read word lines. Each memory cell comprises a first FET 20 having its gate coupled to a write word line and its drain coupled to a bit line, a second FET 22 having its source coupled to the bit line and its drain coupled to a read word line, and first and second negative resistnce devices 24,26 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the source of the first FET and to the gate of the second FET. Preferably, the first FET 20 is a p-channel device, the second FET 22 is an n-channel device, and the first and second negative resistance devices 24,26 are RTDs. In a second embodiment, a memory system has a memory cell at each intersection of a bit line with a word line.

Abstract: A diode type read only memory (ROM) includes a diode as a memory cell. The diode is a logic level "on" memory cell and coupled to one of the word lines and one of the bit lines of the ROM. A relative high voltage is given to the bit line coupled to the diode and a relative high voltage is given to the corresponding word line. Therefore, the data saved in the diode can be read out.

Abstract: A nonvolatile memory cell (600) has a read device (510), program device (515), and tunnel diode (535). A write control line (WC) is directly coupled to the tunnel diode (535). The memory cell (500) may be used to form compact arrays of memory cells to store logical data. During programming of a selected memory cell, half-select voltages are used on the write control (WC) and control gate lines (CG) for unselected memory cells to prevent disturb and minimize oxide stress.

Abstract: A memory cell architecture utilizing a dual access gate and dual wordlines is disclosed. The cell is comprised of a first transistor connected between a digitline and a cellplate. The transistor is responsive to a read wordline to enable the cell to be read. An active device, such as a second transistor, is provided for modifying at least one conductive characteristic of the first transistor according to the state of a signal on the digitline. The conductive characteristic that is modified may be, for example, the threshold voltage or the transistor's channel resistance. Modification of the first transistor's characteristics is representative of writing information to the memory cell. A circuit structure for implementing the circuit architecture is also disclosed together with a method of operating a memory cell.

Abstract: A process and structure are disclosed for a programmable array for use in a read-only memory comprising diode elements and shorted diode elements. The elements are connected across bit and wordlines. The invention utilizes lateral polysilicon diodes and metal silicide layer bridging the junction of pre-selected diodes to short pre-selected diode elements. Programming is accomplished by either forming the silicide layer across the junctions of pre-selected diodes or removing the silicide layer from the junctions of pre-selected diodes.

Abstract: A digital-data-transmission-line circuit for actively clamping transmission signal and signal-complement amplitudes so as to reduce pattern-related jitter at a receiver/analyzer. The circuit includes a pair of opposing diode devices, where each diode device is coupled across the pair of conducting wires that make up the transmission line. The diode devices clamp the difference in potential between the two transmission lines so that the signal amplitude seen at the receiver will not vary to significantly with the number of like pulses that are transmitted in succession. In this manner, the present invention reduces pattern-dependent jitter in the cross-over from HIGH to LOW as seen at the receiver. By means of the parasitic capacitance accompanying the diode devices, the circuit of the present invention additionally provides some high-frequency filtering and smoothing of the waveform of the received signal.