Abstract: A reference cell for reading EEPROM memory devices, capable of discharging any charges present in its own floating gate without varying the geometry of the cell with respect to that of the associated memory cells and without requiring specific manufacturing steps. For this purpose, a switch element, for example a diode, is provided between the floating gate and the substrate of the device and discharges any charges present in the floating gate toward the substrate during the cell idle state in the absence of read signals.

Abstract: A semiconductor memory circuit comprises memory cells, word lines, digit line pairs, load elements, a data bus line pair and a sense amplifier. The load elements are diode type semiconductor elements, and the information of the memory cell is read by using potential difference in forward voltages of the elements.

Abstract: An improved ferroelectric, non-volatile memory comprises an array of ferroelectric capacitors with each capacitor connected to one row and one column select line through a network of diodes. The select lines are connected to a power supply or ground to access one of the cells. The diodes are configured to provide a conducting path between a power supply and ground including the accessed cell while isolating all other cells from the power supply and ground.

Abstract: Disclosed is a semiconductor memory device comprising an SOI substrate in which a semiconductor film is formed on a semiconductor substrate with an insulating film interposed therebetween. A memory cell structure is formed by a switching MOS transistor formed in the SOI substrate and an Esaki diode is positioned on the MOS transistor. The memory device also comprises a memory cell provided with a plurality of tunnel diodes connected to one of the impurity regions constituting the FET formed in the semiconductor substrate, and another memory cell provided with an Esaki diode formed in an self-alignment by a solid phase diffusion. In manufacturing the semiconductor memory device, the MOS transistor and the Esaki diode, which collectively form a memory cell, are integratedly formed one upon the other. The MOS transistor is formed in a semiconductor substrate using an SOI structure so as to prepare a memory cell which does not include a parasitic pn-junction.

Abstract: A compact SRAM cell and method for its fabrication are disclosed. The small size of the SRAM cell is achieved by fabricating a diode load immediately above the gate electrode of each of the cross coupled transistors of the cell. In accordance with one embodiment, the gate electrode and diode structure include, in sequence, an N-type doped polycrystalline silicon layer, an electrically conductive diffusion barrier layer, a P-type doped polycrystalline silicon layer and an N-type doped polycrystalline layer.

Abstract: A three-dimensional memory element comprises a multilayer tunnel switch portion formed by alternately stacking conductive films and insulating films, both the ends of the switch portion consisting of insulating films, a write electrode formed on the insulating film as one end of the multilayer tunnel switch portion, a read electrode formed on the insulating film as the other end of the multilayer tunnel switch portion, and charge accumulating capacitors respectively connected to the conductive films of the multilayer tunnel switch portion.

Abstract: A transistor memory cell is disclosed of the type wherein an unclamped conducting transistor in each of a plurality of memory cells connected to a given word line is driven into saturation when storing data. The cell is equipped with controlled active devices for discharging the saturation capacitance of the conducting transistors prior to writing new data into the cells. Each active device is characterized with a forward low-impedance current direction and reverse high impedance current direction therethrough for each saturation transistor. Each active device is connected to discharge an associated saturation transistor in its forward current direction. In one embodiment, each active device discharges to a word line when the line is brought to an appropriate control potential. In another embodiment, each active device discharges to a separate discharge line not connected to the work line when the former line is brought to an appropriate control potential. The active devices may be diodes.

Abstract: A read only memory circuit comprises bit lines, word lines and cells connected between the bit lines and word lines. The read only memory circuit also comprises a discharge circuit. The discharge circuit is used for discharging all the bit lines except for one of the bit lines designated in order to read out a datum stored in a cell connected to the designated one bit line.

Abstract: A semiconductor memory device having a number of memory cells. Each of the memory cells comprises a diode having a first electrode connected to a bit line. The diode has a second electrode connected at a point to one terminal of a storage capacitor, the other terminal of which is connected to a word line. A reset circuit is provided for resetting the point to a predetermined potential.

Abstract: An improved Schottky barrier diode for increasing the alpha particle resistance of static random access memories includes an extra implanted N-type region at the surface of the epitaxial layer to increase the impurity concentration there to about 1.times.10.sup.19 atoms per cubic centimeter. In one device, arsenic is employed to overcompensate a guard ring where the Schottky diode is to be formed, while in another device phosphorus is employed and the guard ring is not overcompensated. The resulting Schottky diodes, when employed in the static random access memory cells, dramatically increase the alpha particle resistance of such cells, while also substantially decreasing the access time.

Abstract: An apparatus for programming an ECL PROM comprises conventional ECL row and column address circuits for selecting a particular fuse in the ECL PROM. The selection of a particular fuse in the ECL PROM generates a control signal in the address decoders corresponding thereto which enables a current drive gate and a current sink gate coupled thereto. A row program control circuit and a column program circuit are then enabled by an increase of potential applied thereto for turning on the current drive gate and the current sink gate coupled to the selected fuse. The turning on of the current drive gate and the current sink gate coupled to the selected fuse causes 50 to 10 milliamps to flow through the selected fuse, blowing the fuse.

Abstract: A monolithic integrated circuit memory control operating through the use of MOS field-effect transistors with diode or bipolar circuit arrangement for the bit line column switching.

Abstract: A semiconductor memory cell includes cross coupled bipolar transistors operated in the forward current mode with power fed to the base of the transistor through Schottky diodes from separate word lines. Bit lines are connected to the transistors' emitters and a high differential current is sensed between the bit lines during read operations. No resistors are included within the cell.

Abstract: Exclusive diode-FET logic circuitry capable of providing functional programmable logic array output logic signals within one-gate delay from an initial input logic signal, and functional read-only memory output data signals within two- or three-gate delay from an initial input address signal. The OR and AND functions of the circuit are performed by diode configurations thus resulting in high packing density, easy logic array programming, low power dissipation, and high speed operations. The invention may utilize Schottky diodes and metal semiconductor FETs thereby allowing the implementation of high speed gallium arsenide integrated circuit technology.

Abstract: A GaAs SCFL RAM having a unique three-voltage-level write circuit, direct-read circuitry with only one gate delay, diode-coupled FET logic cells, and peripheral circuitry with SCFL gates. The memory module architecture and plan of the RAM allow for several design options which may include 1K.times.16 and 16K.times.1 memory configurations. The RAM incorporates strobe circuitry for powering down selected memory modules, without loss of data, thus reducing power dissipation. The SCFL circuitry of the RAM functions with closely matched complementary signals for fast switching with minimum current spiking. The RAM has a wide range of threshold voltage tolerance, excellent noise margin, and a very high level of radioactive radiation hardness.

Abstract: A semiconductor memory device is provided such as the type having flip-flop memory cells each including two bipolar transistors in cross connection with each other. In certain embodiments, at least a part of a Schottky barrier diode or capacitor in the memory cell is formed under a digit line. This memory device is greatly reduced in its required area, and the Schottky barrier diode and capacitor are negligibly influenced by the digit line. In other embodiments, it is arranged to provide different electrodes for the Schottky barrier diode and the capacitor to optimize construction in a minimized space.

Abstract: In a junction-shorting type PROM, including transistors, a highly doped region having the same conductivity type as a base is provided between a pair of memory cells. This region is a base contact region which commonly connects paired bases at a surface terminal connected to a word line. The base contact region also extends into the substrate, which is a collector, and prevents minority carries in each of the paired bases from diffusing into an adjacent base, and thus, prevents influence between the paired memory cells. The base contact region may be isolated from emitter regions by a narrow groove filled with insulation material. The narrow groove is deeper than the emitter regions but shallower than the substrate. A memory cell block composed of the paired cells and the base contact region is isolated at its circumference by the narrow groove.

Abstract: A computer memory device (10) for storing identified associations between data items of a data collection comprises an array (15) of signal flow pathways (1,2,3 etc) which are respectively rendered representative of data items by an indexing component (12) and input/output circuitry (18) connected to the array (15). Controllable interconnect elements (A,B,C,D,E, etc) selectively interconnect the pathways (1,2,3 etc) in one or more pairs and effect directional control of signal flow between each interconnected pair in accordance with the identified association between the respectively represented data items of the data collection. The interconnect elements (A,B,C etc) are status controlled by signals delivered thereto over respective channels (20A,20B,20C etc) from respective control devices (22A,22B,22C etc) which are contained in a memory (17) which is externally addressable by component (11).

Abstract: In a semiconductor memory device comprising row decoders, word line drivers, word lines, memory cells, a d.c. power source for a write mode, and a d.c. power source for a read mode, one of the word line drivers comprises a first circuit for supplying a write voltage from the d.c. power source for the write mode to one of the word lines selected by the row decoders when predetermined data is written into one of the memory cells connected to the selected word line and a second circuit for supplying a current from the selected word line to the d.c. power source for the read mode when the predetermined data is to be verified after the predetermined data has been written into one of the memory cells; the second circuit comprises a depletion type transistor and a one-directional conductive element connected in parallel to the depletion type transistor.

Abstract: A circuit is described that provides a quick charge and discharge of a row of memory cells. A first transistor has its collector-emitter path coupled between a first voltage and a row of memory cells, and a base coupled to an input terminal. A second transistor has its collector-emitter path coupled to the first voltage by a resistor and to a voltage level setting device, and a base coupled to the input terminal. A third transistor has its collector-emitter path coupled between the row of memory cells and a second voltage, and a base coupled to a voltage level shifting device. As the row of memory cells are selected, the third transistor becomes less conductive, thereby sinking less current from the row of memory cells and allowing the inherent capacitance of the row of memory cells to charge more quickly. As the row of memory cells are deselected, the third transistor becomes more conductive, thereby sinking more current from the row of memory cells and discharging the inherent capacitance more quickly.

Abstract: A CMOS memory cell is provided having separate read and write bit lines and coupling devices associated therewith which provide improved read and write times for the cell. The separate read line is coupled to the cell via a bipolar transistor which supplies increased drive current to the read bit line thereby decreasing the read time. The separate write line is coupled to the cell via a low impedance diode which reduces the write time.

Abstract: An apparatus for displaying in real-time a previously recorded video sequence includes a main memory wherein digitized video gray-scale information is stored for selected non-interlaced fields of video images to be displayed. The memory unit is formed of interconnected substrates. Each substrate is a ROM which includes storage elements and a layer of amorphous silicon alloy which forms an array of diode isolation elements. Column select and read-out circuitry as well as row select circuitry for each of the substrates are formed, on each corresponding substrate, utilizing the same amorphous silicon alloy. Digitized fields of presorted information are read out and stored in pairs in an interpolator circuit which is used to form interlaced fields to be displayed timewise between the digitally stored fields. The digitized fields are converted by a digital-to-analog converter and added to sync signals to form a composite analog video signal adapted to drive a raster scan display unit.

Abstract: An integrated Schottky logic (ISL) read only memory (ROM) uses ISL drivers and decoders connected to wordlines and data bitlines. The pattern of data stored in the ISL is determined by Schottky diodes which are connected between selected data bitlines and wordlines. Improved performance is achieved by using a leakage current compensation source (such as a wordline pullup resistor) connected to each wordline, and by using a programmable dummy load (such as one or more dummy bitlines). The pullup resistors compensate for bitline loading sensitivity caused by leakage currents of the workline drivers. The dummy bitlines are selectively connected to those wordlines which are lightly loaded to compensate for wordline loading sensitivity and thus equalize access time and improve wordline decoder noise margins.

Abstract: An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emitter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to couple the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.

Abstract: A semiconductor memory device composed of bipolar transistors is disclosed. A read/write control circuit includes a voltage producing section which produces a reading-out voltage used for reading out the data stored in the selected memory cell. The voltage producing section includes a first transistor of an emitter follower type as its output stage, and the data-read operation is thus attained in a high speed. The voltage producing section further includes a diode whose ON voltage is substantially equal to that of a clamping diode provided in a memory cell and a second transistor having an emitter resistor and a collector resistor and supplying the collector resistor with a current determined by the ON voltage of the diode and the emitter resistor. The potential at the collector of the second transistor is applied to the first transistor.

Abstract: An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emitter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to couple the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.

Abstract: A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PH junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

Abstract: A high density, low power dissipating semiconductor memory cell is provided by connecting first and second inputs of a means for maintaining current in one of two conditions to first and second bit lines, by first and second diodes, respectively. Conveniently, the means for maintaining the current in one of two conditions includes first and second transistors operating in the normal current mode. Standby current is provided to the base of the first transistor through the first bit line and first diode, and to the base of the second transistor through the second bit line and second diode.

Abstract: The disclosure is directed to an improved random access memory (RAM). More particularly to improved bit selection circuitry for use in an array preferably employing unclamped CTS (Complementary Transistor Switch) type memory cells.

Abstract: A random access memory circuit for use with positive and negative supply voltages, a read enable line, an output line, and write "1" and "0" lines includes first, second, third, and fourth level shifting diodes. A first input isolation diode is connected between the write "1" line and the first level shifting diode. A second input isolation diode is connected between the write "0" line and the cathode of the third level shifting diode. The drain of a first write FET is connected to the anode of the third diode, the source is connected to the read enable line, and the gate is connected to the cathode of the second level shifting diode. A second write FET has its drain connected to the anode of the first level shifting diode, its source connected to the read enable line, and its gate connected to the cathode of the fourth diode. An output buffer FET is connected by its source to the read enable line, by its gate to the cathode of the fourth diode.

Abstract: A semiconductor memory device has at least one memory cell which includes first and second tunnel diodes connected in series in a forward-bias direction between first and second power source terminals. The first and second power source terminals are held at constant potentials. A switching MOS transistor is connected at one end to a connection point between the first and second tunnel diodes. The potential at the connection point between the first and second tunnel diodes is determined by the potential at the other end of the switching MOS transistor.

Abstract: A bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10. Metal silicide 30 overlies strips 34 and 35 of doped polycrystalline silicon 25, 28, 37, and 38 to cross-couple the bases and collectors of the two transistors Q1 and Q2 forming the memory cell. The metal silicide 30 shorts PN junctions 29 in polycrystalline 23. Two further strips 50 and 52, each comprising a sandwich of P type polycrystalline silicon 42, metal silicide 45, and N conductivity type polycrystalline silicon 47, are formed to couple the cross-coupled bases and collectors to respective diodes 60 and 65. The diodes 60 and 65 are formed by depositing metal 62 and 64 in electrical contact with the underlying N type polycrystalline silicon 47.

Abstract: A bipolar ROM having a polysilicon PN junction diode as the matrix element for each bit of storage, wherein the diode is constructed laterally to the associated word line of the array. The word line and diode are implanted with impurities, then metal is deposited on the exposed surfaces of the polysilicon and the structure undergoes a sintering process. A layer of oxide covers the structure and a metal bit line connection is made to the diode P-type section, while the word line and other section of the diode are N-type. P and N type regions may be interchanged, as the polarity of a bit line or word line is a function of drive and sense circuitry. This combination of structure and method allows the use of polysilicon because of the lower sheet resistance and higher speed. Also, the use of PN junction diodes is possible instead of a design requiring Schottky diodes or transistors as matrix elements.

Abstract: The logic circuit comprises two field effect transistors in series, whose gates are connected to the supply voltage by a first load. The source of the first field effect transistor is connected to earth. The drain of the second field effect transistor is connected on the one hand to the supply voltage by a second load and to the gate of a third field effect transistor, whose drain is connected to the supply voltage and whose source is connected to the common point constituted by the drain of the first field effect transistor and the source of the second field effect transistor via a Schottky diode.

Abstract: A non-volatile semiconductor memory and switching device employing a Schottky barrier junction and a dual layered dielectric system for entrapping charges adjacent thereto. The dual layered dielectric system typically comprises a layer of nitride on a layer of oxide arranged such that trapped charges within the oxide and at the nitride-oxide interface act to alter the depletion region beneath, and in the vicinity of, the Schottky contact. Trapped charges may be made to selectively modify the Schottky barrier depletion region and vary its conductivity characteristics between a diode characteristic (OFF) at one extreme and ohmic contact (ON) at the other, all in accordance with the magnitude and sign of the trapped charges.

Abstract: A semiconductor memory device includes at least, a memory cell including a first Schottky diode therein, a word line, a bit line, a first constant-current circuit for the word line, a second constant-current circuit for the bit line, and a bias circuit for biasing the first and second constant-current circuits. The bias circuit contains therein a second Schottky barrier diode. A forward voltage V.sub.F of the second Schottky barrier diode is substantially the same as that of the first Schottky barrier diode.

Abstract: A bit line powered translinear memory cell includes a pair of NPN transistors Q101 and Q102 having cross-coupled bases and collectors. Diode loads D101 and D102 couple the NPN transistors Q101 and Q102 to the bit lines 301 and 302. The emitters of the two transistors Q101 and Q102 are coupled together and to a word line 103. Cell parasitic capacitances C101 and C102 are used to maintain data in nonaddressed memory cells during reading of other cells coupled to the same word line 103.

Abstract: In the disclosed memory, address decode means are integrated into a surface of a substrate, for addressing cells in the memory; an insulating layer covers the address decode means and the substrate; an array of spaced-apart memory cell select lines lie on the insulating layer; and outputs from the address decode means respectively couple through the insulating layer to the select lines. Each cell of the memory is comprised of a pair of the select lines and further includes a resistive means between that pair which irreversibly switches from a relatively high resistance state to a relatively low resistance state upon the application of a threshold voltage thereacross, and the resistance states are representative of the information in the cell.

Abstract: A semiconductor memory cell for a programmable read-only memory includes a polysilicon layer formed with laterally spaced surface regions which differ in impurity concentration and which form two back-to-back series diodes functioning as a programmable diode and an isolating diode. Because of the different impurity concentration, the diodes have different reverse-bias breakdown voltages. The programmable diode has the lower reverse-bias breakdown voltage. The high reverse-bias breakdown voltage of the isolating diode has the effect of blocking the parasitic current drain on the programming current.

Abstract: A two state memory cell includes a bipolar transistor and a tunnel diode shunted across the base-collector junction thereof. A constant operating current is established through the transistor and the tunnel diode. The voltage across the tunnel diode may thus be maintained at one of two stable levels, while the bipolar transistor is kept on regardless of the tunnel diode voltage, which determines the ZERO or ONE state of the cell. Since the transistor is not switched on and off when the memory state (corresponding to the two tunnel diode voltage levels) changes, memory cell switching speed is not degraded by transistor switching delay. Moreover, since the current in the tunnel diode is maintained constant, preferably at a value midway between the tunnel diode peak and valley currents, the noise margin of the memory cell is enhanced and the possibility of false switching reduced.

Abstract: A semiconductor read-only-memory (ROM) device having an array of punch-through devices as memory cells. The cells are formed at the crossing points of two pluralities of parallel elongated regions, the two pluralities being perpendicular to each other. One plurality is located in subsurface regions of a semiconductor body and is of a conductivity type opposite that of the surrounding body. The other plurality is located at a surface of the semiconductor body and is of the same conductivity type as the subsurface plurality. The device is programmed by implanting impurities of the same conductivity type as the semiconductor body between selected crossing points. No contacts exists in the array.

Abstract: A static memory cell uses a micro-tunnel diode as load to a switching circuit involving field effect transistors. Another field effect transistor circuit is used as gate for read-address and read-out. The stationary current through the tunnel diode at logic zero is kept barely above the valley current to prevent aging. Close control of two threshold levels for the transistors in the memory cell is achieved by using the same dopant distribution in their channels in conjunction with a Schottky gate and a p-n junction gate.

Abstract: This matrix has high barrier Schottky diodes at Read or Reproduce Only Storage (ROS) matrix crossovers to represent 1's (the absence of diodes representing 0's) and low barrier Schottky diodes connected to select individual column lines (bit lines) of the ROS matrix. A current sink is connected to each column. Any unselected column causes the current in that column to be diverted through the respective low barrier diode, thus preventing that current from flowing into the selected word line. The only current that flows into the selected word line of a matrix depends from the single selected column current source.

Abstract: In a memory array wherein each cell includes an emitter follower, a diode is formed on the emitter by a thin layer which is capable of being shorted by vertical migration of bit line atoms through the layer and into the emitter region. The thin layer is fabricated by epitaxially growing the thin layer over the wafer with the emitter diffusion aperture open, oxidizing the epitaxial layer, selectively removing portions of the polycrystalline epitaxial layer and removing the oxide from the remaining epitaxial layer in the emitter diffusion aperture.

Abstract: A programmable non-volatile semiconductor memory cell consisting of an n-channel insulated gate field effect transistor comprising a gate electrode which is floating with respect to potential, and enclosed on all sides by an insulating material and which, in its surface expansion, extends with electrode parts beyond a channel region of the insulated gate field effect transistor, which channel region is arranged on a surface of a monocrystalline semiconductor substrate, and which gate electrode is coupled capacitively by means of two electrode parts of different size via an insulated gate, to respective programming electrodes wherein an erase electrode to which an erase signal is capable of being applied, is created by a first planar zone forming a pn-junction with the semiconductor substrate and which, together with a first electrode part of the gate electrode, forms a first capacitance which is substantially smaller than a second capacitance between a second electrode part and a write electrode to which a wr

Abstract: In a semiconductor memory device having a plurality of memory cells located at a cross position of a plurality of bit lines and a plurality of word lines, the memory cell comprising a series circuit of an information storing element such as a diode or a fuse and a PNP type transistor. An N type epitaxial layer is used as a word line and the P type semiconductor substrate is used as a collector output line.

Abstract: A read-only memory in which each memory cell is formed by two back-to-back diodes across which a connection can be formed by means of punch-through. Since cross-talk between adjacent cells is impossible, the packing density may be very large. Additionally, the cycle time of the memory is low due to the very short reverse recovery time of the invented structure.

Abstract: A unidirectional conducting element is series connected between an input terminal and the source electrode of an insulated-gate field-effect transistor (IGFET) having an electrically floating substrate. The unidirectional conducting element is poled to conduct in a direction which is opposite to the forward direction of the source-to-substrate junction in order to isolate the substrate of the IGFET and its associated capacitance from a signal source connected to the input terminal. The invention is particularly useful in high density, high speed, random access memories (RAMs) to prevent the loading of bit lines by non-selected memory cells.

Abstract: Disclosed herein is a small-sized semiconductor memory device, wherein an N.sup.+ (P.sup.+)-type single region having an input function and an output function and an electrode for controlling the electrical potential in a P(N)-type Si substrate are provided on the top surface of the P(N)-type Si substrate. In order to store carriers, i.e., an information, in the bulk of the substrate, an N (P)-type buried layer is formed below the N.sup.+ (P.sup.+)-type input-output region, mentioned above. Information is quickly transferred from or into the buried layer by means of the punch-through effect, which is realized by spreading a depletion layer formed at a PN junction between the input-output region and the Si substrate. Since the carriers are stored in the bulk of the substrate, the size of the memory device is reduced and the surface property of the device does not exert a harmful influence on the carriers.

Abstract: Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry.