Bioplar And Fet Patents (Class 365/177)
  • Patent number: 10489327
    Abstract: A method and apparatus of a network element that includes a line card without retimers between an ASIC and either a network connector or mid-plane connector is described. In an exemplary embodiment, the network element includes a line card coupled to a fabric card. The line card includes a plurality of mid-place connectors, a plurality of network connectors, and a plurality of application-specific integrated circuits (ASICs). In addition, one of plurality the mid-plane connectors couple the line card with the fabric card. Furthermore, the plurality of network connectors to communicate data with devices coupled to the network element and each of the plurality of ASICs process the data.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: November 26, 2019
    Assignee: ARISTA NETWORKS, INC.
    Inventor: Alexander Lubivy
  • Patent number: 10491430
    Abstract: A device includes one or more memory banks configured to store data. The device also includes a data receiver configured to receive distorted input data as part of a data stream, apply a correction factor to the distorted input data to offset inter-symbol interference from the data stream on the distorted input data, and generate the data by applying the correction factor to the distorted data. The device further includes a test circuit internal to the device, wherein the test circuit is configured to generate the data stream.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Raghukiran Sreeramaneni, Jennifer E. Taylor, Liang Liu
  • Patent number: 10340276
    Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 2, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 10291275
    Abstract: A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: May 14, 2019
    Assignee: Samsung Electronics Co., LTD.
    Inventors: Seon-Kyoo Lee, Byung-Hoon Jeong, Jeong-Don Ihm, Young-Don Choi
  • Patent number: 10276253
    Abstract: Apparatuses and methods including anti-fuses and for reading and programming same are disclosed herein. An example apparatus may include an anti-fuse element comprising first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistors. The second transistor is configured to be operated such that a punch-through current flows through the second transistor to indicate that the anti-fuse element has been programmed.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shinichi Miyatake
  • Patent number: 10181344
    Abstract: Devices and methods include, for a memory device, generating a main input-output line signal on a main input-output line using driving circuitry. The main input-output line is coupled to multiple sensing amplifiers. Each of the sensing amplifiers each locally generate a local data line from the main data line. Each of the sensing amplifiers also includes multiple local sensing amplifiers that are selectively coupled to the generated local data line for overwriting data in the respective local sensing amplifiers.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Harish N. Venkata
  • Patent number: 9859016
    Abstract: A semiconductor device (1001) includes: a memory cell; and a writing control circuit (107), wherein the memory cell includes a memory transistor (10A) which has an active layer (7A), the active layer (7A) including a metal oxide, the memory transistor (10A) is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs, and the writing control circuit (107) is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode such that Vgs?Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor (10A) and Vds is a drain-source voltage of the memory transistor (10A), whereby writing in the memory transistor (10A) is performed.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: January 2, 2018
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Sumio Katoh, Naoki Ueda
  • Patent number: 9761589
    Abstract: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: September 12, 2017
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 9704870
    Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: July 11, 2017
    Assignee: Zeno Semiconductors, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 9552876
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 24, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Ferdinando Bedeschi
  • Patent number: 9514803
    Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: December 6, 2016
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 9466355
    Abstract: A memory architecture includes K first wordlines, M groups of second wordlines, a memory cell array and M switch circuits. K and M are positive integers. Each group of second wordlines includes a plurality of second wordlines. The memory cell array includes M memory banks. The M memory banks are coupled to the M groups of second wordlines respectively, and receive independent M sets of second wordline signals through the M groups of second wordlines respectively. M switch circuits are disposed in correspondence with the M memory banks respectively. Each switch circuit selectively couples the K first wordlines to a corresponding memory bank so that the corresponding memory bank receives a shared set of first wordline signals through the K first wordline. Each memory bank performs a data access operation according to the received set of first wordline signals and a corresponding set of second wordline signals.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: October 11, 2016
    Assignee: Piecemakers Technology, Inc.
    Inventors: Tah-Kang Joseph Ting, Gyh-Bin Wang
  • Patent number: 9450090
    Abstract: An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: September 20, 2016
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 9379119
    Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells further includes: a gate structure on the substrate, a plurality of fin structures disposed on the substrate, where each fin structure is arranged perpendicular to the arrangement direction of the gate structure, a first interlayer dielectric (ILD) layer around the gate structure, a first contact plug in the first ILD layer, where the first contact plug is strip-shaped and contacts two different fin structures; and a second ILD layer on the first ILD layer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Yu-Hsiang Hung, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 9368228
    Abstract: According to an embodiment, a semiconductor memory includes word lines, a plurality of sets of a pair of bit lines, memory cells, a writing/reading circuit, and a word line selection circuit. In a state where inverted data of program data has been written to the memory cells, a stress is applied and the program data is programmed to the memory cells. The writing/reading circuit writes the inverted data of the same program data to a unit memory cell group made of memory cells connected to a set of a pair of bit lines at a time of programming, and reads data from the unit memory cell group by detecting a signal level of the pair of bit lines at a time of reading. The word line selection circuit simultaneously selects and drives two or more word lines of the word lines connected to the unit memory cell group.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: June 14, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Atsushi Kawasumi
  • Patent number: 9281371
    Abstract: A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: March 8, 2016
    Assignee: Tela Innovations, Inc.
    Inventor: Michael C. Smayling
  • Patent number: 9219067
    Abstract: An array of memory cells on an integrated circuit device includes a plurality of memory cells arranged in at least one column. Each of the memory cells includes a plurality of transistors forming two complementary memory nodes. Each of the complementary memory nodes is connected to a respective pair of pull-up or pull-down transistors, which are connected in series and have a shared node between them. For a particular one of the memory cells, one of the shared nodes associated with one of the complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a second one of the memory cells, and another of the shared nodes associated with another of the complementary memory nodes is directly connected to a corresponding shared node associated with a corresponding complementary memory node in a third one of the memory cells.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: December 22, 2015
    Assignee: Altera Corporation
    Inventor: Rajiv Kumar
  • Patent number: 9208840
    Abstract: A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: December 8, 2015
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 9183928
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: November 10, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Ferdinando Bedeschi
  • Patent number: 9165633
    Abstract: A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant. The common node can be constant at a source voltage if a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) is used in the CNT memory device, or the common node can be constant at a supply voltage if an n-channel MOSFET is used in the CNT memory device.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: October 20, 2015
    Assignee: Honeywell International Inc.
    Inventors: Keith W. Golke, David K. Nelson
  • Patent number: 9123724
    Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
  • Patent number: 9093155
    Abstract: A semiconductor memory device includes a memory cell array in which memory cells are arranged, and a first wiring connected to the memory cells. A discharging circuit discharges the voltage of the first wiring according to a first current. In addition, a charging circuit charges the voltage of the first wiring according to a second current. A control circuit detects the voltage of the first wiring and controls a magnitude of the second current based on the detected voltage. A current detection unit generates a third current proportional to the second current and generates a detection result based on a magnitude of the third current. The discharging circuit is configured to control a magnitude of the first current in accordance with the detection result.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: July 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsuaki Sakurai
  • Patent number: 9030867
    Abstract: A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: May 12, 2015
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Hongyue Liu, Maroun Khoury, Yiran Chen
  • Publication number: 20150092485
    Abstract: A two transistor ternary random access memory (TTTRAM) circuit includes an voltage/current input, an input/output switch, a first transistor, a first pull up resistor, a second transistor, and a second pull up resistor. The first transistor has a first emitter, a first collector connected to the input/output switch, and a first base. The first pull up resistor is connected to the first emitter and the voltage/current input. The second transistor has a second emitter connected to ground, a second collector, and a second base connected to the input/output switch. The second pull up resistor is connected to the first base, the second collector, and the voltage/current input.
    Type: Application
    Filed: September 29, 2014
    Publication date: April 2, 2015
    Inventor: Simon Peter Tsaoussis
  • Publication number: 20150092486
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Application
    Filed: December 8, 2014
    Publication date: April 2, 2015
    Inventor: Yuniarto Widjaja
  • Publication number: 20150036425
    Abstract: Techniques are disclosed for writing, programming, holding, maintaining, sampling, sensing, reading and/or determining a data state of a memory cell of a memory cell array, such as a memory cell array having a plurality of memory cells each comprising an electrically floating body transistor. In one aspect, the techniques are directed to controlling and/or operating a semiconductor memory cell having an electrically floating body transistor in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the techniques may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 5, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Serguei OKHONIN, Mikhail NAGOGA
  • Patent number: 8934296
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 13, 2015
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 8929133
    Abstract: A memory array that includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.
    Type: Grant
    Filed: December 2, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Leland Chang, Jeffrey W. Sleight
  • Patent number: 8917547
    Abstract: A memory array that includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Leland Chang, Jeffrey W. Sleight
  • Patent number: 8873283
    Abstract: A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Serguei Okhonin, Mikhail Nagoga
  • Patent number: 8867284
    Abstract: A semiconductor element and an operating method thereof are provided. The semiconductor element comprises a first metal oxide semiconductor (MOS) and a second MOS. The second MOS is electrically connected to the first MOS. The second MOS includes a floating bipolar junction transistor (BJT).
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: October 21, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Chin-Fu Chen
  • Patent number: 8835990
    Abstract: A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: September 16, 2014
    Assignee: Winbond Electronics Corp.
    Inventor: Wen-Yueh Jang
  • Patent number: 8797819
    Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Eric Carman, Mikhail Nagoga, Serguei Okhonin
  • Patent number: 8767458
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Grant
    Filed: October 6, 2013
    Date of Patent: July 1, 2014
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Publication number: 20140153328
    Abstract: An example embodiment is a memory array. The memory array includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.
    Type: Application
    Filed: December 2, 2012
    Publication date: June 5, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin Cai, Leland Chang, Jeffrey W. Sleight
  • Patent number: 8737124
    Abstract: There is provided a semiconductor device including a word line, a bit line, a power supply node, a memory element, and a capacitor. The memory element includes at least first and second regions that form a PN junction between the bit line and the power supply node, and a third region that forms a PN junction with the second region. The capacitor includes a first electrode provided independently from the second region of the memory element and electrically connected to the second region of the memory element, and a second electrode connected to the word line.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: May 27, 2014
    Inventors: Shuichi Tsukada, Yasuhiro Uchiyama
  • Patent number: 8711614
    Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Irfan Rahim, Lu Zhou, Madhuri Mailavaram, Srinivas Perisetty
  • Publication number: 20140036577
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Application
    Filed: October 6, 2013
    Publication date: February 6, 2014
    Inventor: Yuniarto Widjaja
  • Patent number: 8630113
    Abstract: An integrated circuit (IC) includes a memory circuit. The memory circuit includes a plurality of thyristors. The plurality of thyristors are coupled in tandem.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: January 14, 2014
    Assignee: Altera Corporation
    Inventors: Yanzhong Xu, Jeffrey T. Watt
  • Patent number: 8624665
    Abstract: Provided is a method of operating a semiconductor device, wherein an operating mode is set by adjusting timing of a voltage pulse or by adjusting a voltage level of the voltage pulse.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-moo Choi, Won-joo Kim, Tae-hee Lee, Dae-kil Cha
  • Patent number: 8625374
    Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 7, 2014
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen
  • Patent number: 8587988
    Abstract: Disclosed is a memory element, a stack, and a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V0, this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V1, it can be transferred into the likewise high-impedance state 1. By applying a read voltage VR, the magnitude of which is smaller than the write voltages V0 and V1, the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching.
    Type: Grant
    Filed: May 8, 2010
    Date of Patent: November 19, 2013
    Assignees: Forschungszentrum Juelich GmbH, Rheinish-Westfaelische Technische Hochschule Aachen (RWTH)
    Inventors: Eike Linn, Carsten Kuegeler, Roland Daniel Rosezin, Rainer Waser
  • Patent number: 8537609
    Abstract: A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: September 17, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Hsiu Lee, Chieh-Fang Chen
  • Patent number: 8531861
    Abstract: One time programming memory and methods of storage and manufacture of the same are provided. Examples relate to microelectronic memory technology and manufacture. The one time programming memory includes a diode (10) having a unidirectional conducting rectification characteristic and a variable-resistance memory (20) having a bipolar conversion characteristic. The diode (10) having the unidirectional conducting rectification characteristic and the variable-resistance memory (20) having the bipolar conversion characteristic are connected in series. The one time programming memory device of this example takes the bipolar variable-resistance memory (20) as a storage unit, programming the bipolar variable-resistance memory (20) into different resistance states so as to carry out multilevel storage, and takes the unidirectional conducting rectification diode (10) as a gating unit.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: September 10, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Ming Liu, Qingyun Zuo, Shibing Long, Changqing Xie, Zongliang Huo
  • Patent number: 8531904
    Abstract: Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a signal from the thermal sensor. Other aspects are also provided.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: September 10, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Tyler J. Thorp, Roy E. Scheuerlein
  • Patent number: 8526220
    Abstract: An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element.
    Type: Grant
    Filed: June 12, 2011
    Date of Patent: September 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning
  • Patent number: 8514613
    Abstract: Integrated circuits may include configurable-port memory cells. The configurable-port memory cells may be operable in single-port mode and multiport mode. Each configurable-port memory cell may be coupled to first and second pairs of data lines. The configurable-port memory cell may include a first latching circuit having a first data storage node and a second latching circuit having a second data storage node. The first latching circuit may be coupled to the first pair of data lines through a first set of access transistors, whereas the second latching circuit may be coupled to the second pair of data lines through a second set of access transistors. An additional transistor may be coupled between the first and second data storage nodes. The configurable-port memory cell is configured in the single-port mode if the additional transistor is turned off and is configured in the dual-port mode if the additional transistor is turned on.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: August 20, 2013
    Assignee: Altera Corporation
    Inventor: David Lewis
  • Patent number: 8482974
    Abstract: A semiconductor device includes a first signal line, a second signal line, a memory cell, and a potential converter circuit. The memory cell includes a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and a capacitor. The first channel formation region and the second channel formation region include different semiconductor materials. The second drain electrode, one electrode of the capacitor, and the first gate electrode are electrically connected to one another. The second gate electrode is electrically connected to the potential converter circuit through the second signal line.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: July 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Saito, Takanori Matsuzaki, Shuhei Nagatsuka, Hiroki Inoue
  • Patent number: 8467240
    Abstract: Nonvolatile memory element circuitry is provided that is based on metal-oxide-semiconductor transistor structures. A nonvolatile memory element may be based on a metal-oxide-semiconductor transistor structure that has a gate, a drain, a source, and a body. During programming operations, control circuitry floats the body while applying a positive voltage to the drain and a negative voltage to the source. This causes the drain and source, which serve as the collector and emitter in a parasitic bipolar transistor, to break down. The drain-to-source (collector-to-emitter) breakdown causes sufficient current to flow through the source to alter the source electrode and thereby increase the resistance of the source significantly. During sensing operations, control circuitry may apply a voltage across the drain and source while grounding the body to determine whether the memory element has been programmed.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: June 18, 2013
    Assignee: Altera Corporation
    Inventors: Albert Ratnakumar, Shuang Xie, Cheng-Hsiung Huang, Yow-Juang Bill Liu
  • Patent number: 8451657
    Abstract: A nonvolatile semiconductor memory device includes an MIS transistor having nodes, a control circuit configured to apply a first set of potentials to the nodes to cause an irreversible change in transistor characteristics, to apply a second set of potentials to the nodes to cause a first current to flow through the MIS transistor in a first direction, and to apply the second set of potentials to the nodes to cause a second current to flow through the MIS transistor in a second direction opposite the first direction, and a sense circuit configured to produce a signal responsive to a difference between the first current and the second current.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: May 28, 2013
    Assignee: NSCore, Inc.
    Inventor: Tadahiko Horiuchi