Bioplar And Fet Patents (Class 365/177)
  • Patent number: 12170110
    Abstract: A memory including a memory array having a plurality of bit-line inputs and a plurality of word-line inputs; a bit-line decoder; and a control circuit is provided. The bit-line decoder includes a first circuit and a second circuit including a plurality of low-voltage field effect transistors (FET). The control circuit provides control signals to the plurality of low-voltage FETs in a sequence of a pre-pulse phase, a pulse phase, and a post-pulse phase, wherein at the pulse phase, the first circuit and the second circuit receives a desired voltage. The control circuit provide control signals the plurality of low-voltage FETs a voltage no greater than a low-voltage at the pre-pulse phase and the post-pulse phase. In silicon-on-insulator (SOI) technologies, use of low-voltage FETs in the bit-line and word-line decoders reduces the area of the periphery circuits of the memory array without requiring change to the memory array itself.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: December 17, 2024
    Assignee: Weebit Nano Ltd.
    Inventor: Lior Dagan
  • Patent number: 12069868
    Abstract: A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin
  • Patent number: 12062606
    Abstract: A memory device includes: a memory cell region including gate electrodes spaced apart from each other on a first semiconductor substrate to be stacked, and channel structures; and a peripheral circuit region including upper metal lines disposed above a second semiconductor substrate, disposed below the memory cell region. The first semiconductor substrate includes first regions, having a first value corresponding to a distance between the first semiconductor substrate and the upper metal lines, and second regions having a second value, lower than the first value. A reference voltage for operating the memory device is transmitted to at least one of the first upper metal lines, disposed below the first region. Accordingly, coupling capacitance for a significant signal may be reduced while maintaining a length of a connection portion and the magnitude of resistance of a common source line. Furthermore, an error rate of the memory device may be reduced.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: August 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sujeong Kim, Inmo Kim
  • Patent number: 11848062
    Abstract: A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: December 19, 2023
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Yan Wang, Peijian Zhang, Mingyuan Xu, Xian Chen, Feiyu Jiang, Xiyi Liao, Sheng Qiu, Zhengyuan Zhang, Ruzhang Li, Hequan Jiang, Yonghong Dai
  • Patent number: 11825220
    Abstract: An imaging device including a miniaturized pixel is provided. A pixel is provided with a photoelectric conversion element, a first transistor, a second transistor, and a capacitor. One electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. The gate of the second transistor is electrically connected to one electrode of the capacitor. In a first period, a first potential is supplied to the other electrode of the capacitor and the first transistor is set in an on state so that imaging data corresponding to illuminance of light delivered to the photoelectric conversion element is written to the pixel. Furthermore, in a second period, a second potential is supplied to the other electrode of the capacitor so that the imaging data is read from the pixel.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: November 21, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazunori Watanabe, Susumu Kawashima
  • Patent number: 11749320
    Abstract: A storage device including a cell array and a disturb-free circuit is provided. The cell array includes a first cell and a second cell. The first cell is coupled to a first conductive line and a specific conductive line. The second cell is coupled to a second conductive line and the specific conductive line. The disturb-free circuit performs a first write operation on the first cell and performs a verification operation on the second cell. The verification operation determines whether data stored in the second cell is disturbed by the first write operation. In response to the data stored in the second cell being disturbed by the first write operation, the disturb-free circuit performs a second write operation.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: September 5, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Po-Yuan Tang, Yang-Sen Yeh, Hsuan-Chi Su
  • Patent number: 11690303
    Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: June 27, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Remy Berthelon, Franck Arnaud
  • Patent number: 11515313
    Abstract: A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin
  • Patent number: 11468934
    Abstract: Methods, systems, and devices for access line disturbance mitigation are described to, for example, reduce voltage disturbances on deselected digit lines during a read or write operation. Memory cells of a memory device may be couplable with a write circuit including a level shifter circuit, such that changes in voltage on a selected digit line may be controlled via a level shifter circuit of a write circuit associated with a selected memory cell. The write circuit may write a logic state to the memory cell after completing a read operation. One or more write voltages may be applied to or removed from the memory cell via the level shifter circuit, which may control a slew rate of one or more voltage changes on the selected digit line. The slew rate(s) may be controlled via a current driver circuit coupled with a pull-up circuit or a pull-down circuit of the level shifter circuit.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Xinwei Guo
  • Patent number: 11437102
    Abstract: A memory array with memory cells may have one or more heaters integrated into the memory array between the memory cells. A processor in communication with the heater may notify the heater to activate when a trigger event occurs.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: September 6, 2022
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Takashi Ando, Nanbo Gong
  • Patent number: 11348923
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: May 31, 2022
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 11276697
    Abstract: Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a semiconductor well, a source area and a drain area next to the semiconductor well, a gate electrode, and a base terminal. The gate electrode may be coupled to the base terminal, hence forming a floating body MOSFET. A junction may exist between the drain area and the semiconductor well. A first resistance may exist between the source area and the drain area through the semiconductor well. A programming operation may be performed when the gate electrode is coupled to a high impedance, a programming voltage is applied at the source area, and the drain area is coupled to a ground voltage to break the junction between the drain area and the semiconductor well to generate a current between the source area, the semiconductor well, and the drain area. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Yu-Lin Chao, Sarvesh H. Kulkarni
  • Patent number: 11250923
    Abstract: A layout method includes: forming a layout structure of a memory array having a first row, wherein the first row comprises a plurality of storage cells; disposing a word line; disposing a plurality of control electrodes for connecting the plurality of storage cells of the first row to the word line; and disposing a first cut layer on a first portion of a first control electrode of the plurality of control electrodes.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Sheng Chang, Yao-Jen Yang, Shao-Yu Chou, Yih Wang
  • Patent number: 11200943
    Abstract: A memory device includes a plurality of sub-word line drivers with, each sub-word line driver configured to receive a main word line signal and configured to drive a respective local word line to at least one of an active state, a soft-landing state, an off state based on the main word line signal and a phase signal. The memory device also includes a plurality of phase drivers with each phase driver configured to generate the respective phase signal. The memory device can further include a processing device configured to drive the respective local word line to the soft-landing state prior to entering the off state when transitioning from the active state to the off state so as to provide row hammer stress mitigation between adjacent local word lines corresponding to the plurality of sub-word line drivers. Each sub-word line driver includes a diode-connected transistor.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kyuseok Lee
  • Patent number: 11024373
    Abstract: Circuits and methods are disclosed for voltage-mode bit line precharge for random-access memory cells. A circuit includes an array of random access memory cells; a low-impedance voltage source configured to provide a precharge voltage; and a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: June 1, 2021
    Assignee: Hefei Reliance Memory Limited
    Inventor: Danut Manea
  • Patent number: 10950295
    Abstract: According to one embodiment, a semiconductor memory includes a first bit line; a second bit line; a source line; a first memory cell electrically connected between the first bit line and the source line and including a first transistor and a first capacitor; a second memory cell electrically connected between the second bit line and the source line and including a second transistor and a second capacitor; a third transistor electrically connected to the source line; and a sense amplifier circuit including a first node electrically connected to the first bit line and a second node electrically connected to the second bit line.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chika Tanaka, Keiji Ikeda
  • Patent number: 10727253
    Abstract: Structures for a memory cell and methods associated with forming and using such structures. The structure includes a silicon-on-insulator wafer including a device layer, a substrate, and a buried insulator layer between the device layer and the substrate. The structure further includes a field-effect transistor having first and second source/drain regions and a gate electrode that are over the buried insulator layer. A moat region is arranged in the substrate beneath the field-effect transistor, a well is arranged in the substrate beneath the moat region, and an isolation region extends through the device layer and the buried insulator layer into the substrate. The isolation region is arranged to surround a portion of the device layer defining an active region for the field-effect transistor and a portion of the moat region. A fence region, which extends between the well and the isolation region, surrounds the portion of the moat region.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Edward J. Nowak
  • Patent number: 10489327
    Abstract: A method and apparatus of a network element that includes a line card without retimers between an ASIC and either a network connector or mid-plane connector is described. In an exemplary embodiment, the network element includes a line card coupled to a fabric card. The line card includes a plurality of mid-place connectors, a plurality of network connectors, and a plurality of application-specific integrated circuits (ASICs). In addition, one of plurality the mid-plane connectors couple the line card with the fabric card. Furthermore, the plurality of network connectors to communicate data with devices coupled to the network element and each of the plurality of ASICs process the data.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: November 26, 2019
    Assignee: ARISTA NETWORKS, INC.
    Inventor: Alexander Lubivy
  • Patent number: 10491430
    Abstract: A device includes one or more memory banks configured to store data. The device also includes a data receiver configured to receive distorted input data as part of a data stream, apply a correction factor to the distorted input data to offset inter-symbol interference from the data stream on the distorted input data, and generate the data by applying the correction factor to the distorted data. The device further includes a test circuit internal to the device, wherein the test circuit is configured to generate the data stream.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Raghukiran Sreeramaneni, Jennifer E. Taylor, Liang Liu
  • Patent number: 10340276
    Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 2, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 10291275
    Abstract: A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: May 14, 2019
    Assignee: Samsung Electronics Co., LTD.
    Inventors: Seon-Kyoo Lee, Byung-Hoon Jeong, Jeong-Don Ihm, Young-Don Choi
  • Patent number: 10276253
    Abstract: Apparatuses and methods including anti-fuses and for reading and programming same are disclosed herein. An example apparatus may include an anti-fuse element comprising first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistors. The second transistor is configured to be operated such that a punch-through current flows through the second transistor to indicate that the anti-fuse element has been programmed.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shinichi Miyatake
  • Patent number: 10181344
    Abstract: Devices and methods include, for a memory device, generating a main input-output line signal on a main input-output line using driving circuitry. The main input-output line is coupled to multiple sensing amplifiers. Each of the sensing amplifiers each locally generate a local data line from the main data line. Each of the sensing amplifiers also includes multiple local sensing amplifiers that are selectively coupled to the generated local data line for overwriting data in the respective local sensing amplifiers.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Harish N. Venkata
  • Patent number: 9859016
    Abstract: A semiconductor device (1001) includes: a memory cell; and a writing control circuit (107), wherein the memory cell includes a memory transistor (10A) which has an active layer (7A), the active layer (7A) including a metal oxide, the memory transistor (10A) is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs, and the writing control circuit (107) is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode such that Vgs?Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor (10A) and Vds is a drain-source voltage of the memory transistor (10A), whereby writing in the memory transistor (10A) is performed.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: January 2, 2018
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Sumio Katoh, Naoki Ueda
  • Patent number: 9761589
    Abstract: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: September 12, 2017
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 9704870
    Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: July 11, 2017
    Assignee: Zeno Semiconductors, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 9552876
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 24, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Ferdinando Bedeschi
  • Patent number: 9514803
    Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: December 6, 2016
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 9466355
    Abstract: A memory architecture includes K first wordlines, M groups of second wordlines, a memory cell array and M switch circuits. K and M are positive integers. Each group of second wordlines includes a plurality of second wordlines. The memory cell array includes M memory banks. The M memory banks are coupled to the M groups of second wordlines respectively, and receive independent M sets of second wordline signals through the M groups of second wordlines respectively. M switch circuits are disposed in correspondence with the M memory banks respectively. Each switch circuit selectively couples the K first wordlines to a corresponding memory bank so that the corresponding memory bank receives a shared set of first wordline signals through the K first wordline. Each memory bank performs a data access operation according to the received set of first wordline signals and a corresponding set of second wordline signals.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: October 11, 2016
    Assignee: Piecemakers Technology, Inc.
    Inventors: Tah-Kang Joseph Ting, Gyh-Bin Wang
  • Patent number: 9450090
    Abstract: An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: September 20, 2016
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 9379119
    Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells further includes: a gate structure on the substrate, a plurality of fin structures disposed on the substrate, where each fin structure is arranged perpendicular to the arrangement direction of the gate structure, a first interlayer dielectric (ILD) layer around the gate structure, a first contact plug in the first ILD layer, where the first contact plug is strip-shaped and contacts two different fin structures; and a second ILD layer on the first ILD layer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Yu-Hsiang Hung, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 9368228
    Abstract: According to an embodiment, a semiconductor memory includes word lines, a plurality of sets of a pair of bit lines, memory cells, a writing/reading circuit, and a word line selection circuit. In a state where inverted data of program data has been written to the memory cells, a stress is applied and the program data is programmed to the memory cells. The writing/reading circuit writes the inverted data of the same program data to a unit memory cell group made of memory cells connected to a set of a pair of bit lines at a time of programming, and reads data from the unit memory cell group by detecting a signal level of the pair of bit lines at a time of reading. The word line selection circuit simultaneously selects and drives two or more word lines of the word lines connected to the unit memory cell group.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: June 14, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Atsushi Kawasumi
  • Patent number: 9281371
    Abstract: A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: March 8, 2016
    Assignee: Tela Innovations, Inc.
    Inventor: Michael C. Smayling
  • Patent number: 9219067
    Abstract: An array of memory cells on an integrated circuit device includes a plurality of memory cells arranged in at least one column. Each of the memory cells includes a plurality of transistors forming two complementary memory nodes. Each of the complementary memory nodes is connected to a respective pair of pull-up or pull-down transistors, which are connected in series and have a shared node between them. For a particular one of the memory cells, one of the shared nodes associated with one of the complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a second one of the memory cells, and another of the shared nodes associated with another of the complementary memory nodes is directly connected to a corresponding shared node associated with a corresponding complementary memory node in a third one of the memory cells.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: December 22, 2015
    Assignee: Altera Corporation
    Inventor: Rajiv Kumar
  • Patent number: 9208840
    Abstract: A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: December 8, 2015
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 9183928
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: November 10, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Ferdinando Bedeschi
  • Patent number: 9165633
    Abstract: A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant. The common node can be constant at a source voltage if a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) is used in the CNT memory device, or the common node can be constant at a supply voltage if an n-channel MOSFET is used in the CNT memory device.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: October 20, 2015
    Assignee: Honeywell International Inc.
    Inventors: Keith W. Golke, David K. Nelson
  • Patent number: 9123724
    Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
  • Patent number: 9093155
    Abstract: A semiconductor memory device includes a memory cell array in which memory cells are arranged, and a first wiring connected to the memory cells. A discharging circuit discharges the voltage of the first wiring according to a first current. In addition, a charging circuit charges the voltage of the first wiring according to a second current. A control circuit detects the voltage of the first wiring and controls a magnitude of the second current based on the detected voltage. A current detection unit generates a third current proportional to the second current and generates a detection result based on a magnitude of the third current. The discharging circuit is configured to control a magnitude of the first current in accordance with the detection result.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: July 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsuaki Sakurai
  • Patent number: 9030867
    Abstract: A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: May 12, 2015
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Hongyue Liu, Maroun Khoury, Yiran Chen
  • Publication number: 20150092486
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Application
    Filed: December 8, 2014
    Publication date: April 2, 2015
    Inventor: Yuniarto Widjaja
  • Publication number: 20150092485
    Abstract: A two transistor ternary random access memory (TTTRAM) circuit includes an voltage/current input, an input/output switch, a first transistor, a first pull up resistor, a second transistor, and a second pull up resistor. The first transistor has a first emitter, a first collector connected to the input/output switch, and a first base. The first pull up resistor is connected to the first emitter and the voltage/current input. The second transistor has a second emitter connected to ground, a second collector, and a second base connected to the input/output switch. The second pull up resistor is connected to the first base, the second collector, and the voltage/current input.
    Type: Application
    Filed: September 29, 2014
    Publication date: April 2, 2015
    Inventor: Simon Peter Tsaoussis
  • Publication number: 20150036425
    Abstract: Techniques are disclosed for writing, programming, holding, maintaining, sampling, sensing, reading and/or determining a data state of a memory cell of a memory cell array, such as a memory cell array having a plurality of memory cells each comprising an electrically floating body transistor. In one aspect, the techniques are directed to controlling and/or operating a semiconductor memory cell having an electrically floating body transistor in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the techniques may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 5, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Serguei OKHONIN, Mikhail NAGOGA
  • Patent number: 8934296
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 13, 2015
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 8929133
    Abstract: A memory array that includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.
    Type: Grant
    Filed: December 2, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Leland Chang, Jeffrey W. Sleight
  • Patent number: 8917547
    Abstract: A memory array that includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Leland Chang, Jeffrey W. Sleight
  • Patent number: 8873283
    Abstract: A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Serguei Okhonin, Mikhail Nagoga
  • Patent number: 8867284
    Abstract: A semiconductor element and an operating method thereof are provided. The semiconductor element comprises a first metal oxide semiconductor (MOS) and a second MOS. The second MOS is electrically connected to the first MOS. The second MOS includes a floating bipolar junction transistor (BJT).
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: October 21, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Chin-Fu Chen
  • Patent number: 8835990
    Abstract: A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: September 16, 2014
    Assignee: Winbond Electronics Corp.
    Inventor: Wen-Yueh Jang
  • Patent number: 8797819
    Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Eric Carman, Mikhail Nagoga, Serguei Okhonin