Bioplar And Fet Patents (Class 365/177)
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Patent number: 7180767Abstract: A multilevel memory core includes a word line and a bit line. The multilevel memory core also includes a core cell in electrical communication with the word line and the bit line. The core cell includes a threshold changing material. The threshold changing material is programmed to define multiple levels for storage where each of the multiple levels for storage is associated with a corresponding threshold voltage. Methods for reading the multilevel memory core also are described.Type: GrantFiled: June 18, 2003Date of Patent: February 20, 2007Assignee: Macronix International Co., Ltd.Inventors: Yi Chou Chen, Chih-Yuan Lu
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Patent number: 7164597Abstract: A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.Type: GrantFiled: August 5, 2005Date of Patent: January 16, 2007Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7154778Abstract: Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions. A gate insulator is formed opposing the channel region. The gate insulator includes a number of high work function nanoparticles. A gate is formed on the gate insulator. A plug is coupled to the first source/drain region and couples the first source/drain region to an array plate. A transmission line is coupled to the second source/drain region. The MOSFET is a programmed MOSFET having a charge trapped in the number of high work function nanoparticles in the gate insulator adjacent to the first source/drain region.Type: GrantFiled: February 14, 2005Date of Patent: December 26, 2006Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7130212Abstract: A field effect device (2) includes a source electrode (14), a drain electrode (16), a channel (24) formed between the source electrode (14) and the drain electrode (16), and a gate electrode (22) separated from the channel (24) by an insulating layer (20), wherein the channel (24) comprises a switching material reversibly switchable between a lower conductivity state and a higher conductivity state, each of the conductivity states being persistent.Type: GrantFiled: November 12, 2004Date of Patent: October 31, 2006Assignee: International Business Machines CorporationInventors: Georg J. Bednorz, David J. Gundlach, Siegfried F. Karg, Gerhard I. Meijer, Heike E. Riel, Walter H. Riess
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Patent number: 7116570Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.Type: GrantFiled: October 26, 2005Date of Patent: October 3, 2006Assignee: Micron Technology, Inc.Inventor: David A. Zimlich
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Switching element method of driving switching element rewritable logic integrated circuit and memory
Patent number: 7116573Abstract: A switching element has an ion conductor capable of conducting metal ions for use in an electrochemical reaction therein, a first electrode and a second electrode which are disposed in contact with said ion conductor and spaced a predetermined distance from each other, and a third electrode disposed in contact with the ion conductor. When a voltage for causing the switching element to transit to an on state is applied to the third electrode, metal is precipitated between the first electrode and the second electrode by metal ions, electrically interconnecting the first electrode and the second electrode. When a voltage for causing the switching element to transit to an off state is applied to the third electrode, the precipitated metal is dissolved to electrically disconnect the first electrode and the second electrode from each other.Type: GrantFiled: July 16, 2004Date of Patent: October 3, 2006Assignee: NEC CorporationInventors: Toshitsugu Sakamoto, Hisao Kawaura, Hiroshi Sunamura -
Patent number: 7113426Abstract: Non-Volatile RAM Cell and Array using Nanotube Switch Position for Information State. A non-volatile memory array includes a plurality of memory cells, each cell receiving a bit line, word line, and release line. Each memory cell includes a cell selection transistor with first, second and third nodes. The first and second nodes are in respective electrical communication with the bit line and the word line. Each cell further includes an electromechanically deflectable switch, having a first, second and third node. The first node is in electrical communication with the release line, and a third node is in electrical communication with the third node of the cell selection transistor. The electromechanically deflectable switch includes a nanotube switching element physically positioned between the first and third nodes of the switch and in electrical communication with the second node of the switch. The second node of the switch is in communication with a reference signal.Type: GrantFiled: March 26, 2004Date of Patent: September 26, 2006Assignee: Nantero, Inc.Inventors: Thomas Rueckes, Brent M. Segal, Bernard Vogeli, Darren Brock, Venkatachalam C. Jaiprakash, Claude L. Bertin
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Patent number: 7113425Abstract: A nonvolatile memory device includes a bit line, a pair of data lines and a plurality of scalable two transistor memory (STTM) cells. The memory cells are arranged between a pair of datalines so as to share the bit line. The memory device further includes a data line selection circuit and a sense amplification circuit. The data line selection circuit selects one of a pair of data lines, and the sense amplification circuit senses and amplifies a voltage difference between the bit line and the selected data line. Operation speed is increased, while improving device cell array structure.Type: GrantFiled: October 29, 2004Date of Patent: September 26, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Yeong Cho, Byung-Gil Choi
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Patent number: 7092273Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.Type: GrantFiled: February 14, 2006Date of Patent: August 15, 2006Assignee: Xilinx Inc.Inventor: Kevin T. Look
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Patent number: 7057927Abstract: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.Type: GrantFiled: November 30, 2005Date of Patent: June 6, 2006Assignee: Intel CorporationInventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien Lu, Vivek K. De
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Patent number: 7057926Abstract: A semiconductor memory comprises a semiconductor substrate including a semiconductor film on a first insulating film; a memory cell that stores data by charging or discharging a body region formed in said semiconductor film, the memory cell including a source layer on one side of said body region and a drain layer on another side of said body region; a memory cell array in which a plurality of said memory cells are arranged in a matrix; a second insulating film provided on said body region of said memory cell; a first word line provided on said second insulating film; a bit line connected to the drain layer of said memory cell, and having a reference potential when said memory cell is in a data retaining state; a source line connected to the source layer of said memory cell, and having the reference potential; and a second word line buried in said first insulating film, and provided below said body region of said memory cell, wherein a potential VBWLH of said second word line when said memory cell is in the dType: GrantFiled: January 13, 2005Date of Patent: June 6, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Takashi Ohsawa
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Patent number: 7031203Abstract: A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.Type: GrantFiled: February 28, 2005Date of Patent: April 18, 2006Assignee: Intel CorporationInventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Vivek De
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Patent number: 7031898Abstract: A mechanism is disclosed for recognizing and functionally abstracting a column of memory cells. According to one embodiment, a column of n (where n is an integer greater than 1) memory cells is identified in a description of a circuit. One of the n memory cells is selected as a representative memory cell. Then, the column of n memory cells is represented as a single-memory-cell column comprising the representative memory cell. The column is thereafter functionally abstracted to derive a logic-level representation of the memory cell. After that is done, n?1 additional instances of the logic-level representation are generated. In this manner, the column of n memory cells is functionally abstracted as a column of n logic-level representations of the representative memory cell.Type: GrantFiled: December 21, 2001Date of Patent: April 18, 2006Assignee: Cadence Design Systems, Inc.Inventors: Alok Jain, Erich Marschner, Swapnajit Chakraborti
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Patent number: 7026692Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.Type: GrantFiled: November 12, 2003Date of Patent: April 11, 2006Assignee: Xilinx, Inc.Inventor: Kevin T. Look
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Patent number: 7027316Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.Type: GrantFiled: December 29, 2003Date of Patent: April 11, 2006Assignee: Micron Technology, Inc.Inventor: David A. Zimlich
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Patent number: 7023751Abstract: The required refresh rate of a DRAM is reduced by biasing active digit lines to a slight positive voltage to reduce the sub threshold current leakage of access transistors in memory cells that are not being accessed. The slight positive voltage is provided by a voltage regulator circuit using one or more bipolar transistors fabricated in a well that electrically isolates the bipolar transistors from the remainder of the substrate. The voltage provided by the voltage regulator is preferably coupled to the access transistors by powering each of the n-sense amplifiers in the DRAM with the voltage from the voltage regulator.Type: GrantFiled: January 19, 2005Date of Patent: April 4, 2006Assignee: Micron Technology, Inc.Inventor: Howard C. Kirsch
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Patent number: 7016224Abstract: A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate a type of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.Type: GrantFiled: July 2, 2004Date of Patent: March 21, 2006Inventor: Tsu-Jae King
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Patent number: 7002842Abstract: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.Type: GrantFiled: November 26, 2003Date of Patent: February 21, 2006Assignee: Intel CorporationInventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien Lu, Vivek K. De
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Patent number: 7002841Abstract: An MRAM having improved integration density and ability to use a magnetic tunneling junction (MTJ) layer having a low MR ratio, and methods for manufacturing and driving the same, are disclosed. The MRAM includes a semiconductor substrate having a bipolar junction transistor (BJT) formed thereon, a bit line coupled to an emitter of the BJT, an MTJ layer coupled to the BJT, a word line coupled to the MTJ layer, a plate line coupled to the BJT so as to be spaced apart from the MTJ layer, and an interlayer dielectric formed between components of the MRAM, wherein the MTJ layer is coupled to a base and a collector of the BJT, the plate line is coupled to the collector, and an amplifying unit for amplifying a signal while data is read out from the MTJ layer is coupled to the bit line, thereby allowing precise reading of the data.Type: GrantFiled: November 6, 2003Date of Patent: February 21, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: In-Kyeong Yoo, Wan-jun Park
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Patent number: 6992925Abstract: A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed p+ region to form a p-n diode in the substrate underlying the gate of the transistor. Further, the wordline is formed from a buried diffusion N+ layer while the column bitline is formed from a counterdoped polysilicon layer.Type: GrantFiled: March 10, 2004Date of Patent: January 31, 2006Assignee: Kilopass Technologies, Inc.Inventor: Jack Zezhong Peng
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Patent number: 6990016Abstract: A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.Type: GrantFiled: July 2, 2004Date of Patent: January 24, 2006Assignee: Progressant Technologies, Inc.Inventor: Tsu-Jae King
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Patent number: 6982903Abstract: Field effect devices having a source controlled via a nanotube switching element. Under one embodiment, a field effect device includes a source region and a drain region of a first semiconductor type and a channel region disposed therebetween of a second semiconductor type. The drain region is connected to a corresponding terminal. A gate structure is disposed over the channel region and connected to a corresponding terminal. A nanotube switching element is responsive to a first control terminal and a second control terminal and is electrically positioned in series between the source region and a terminal corresponding to the source region. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the source region and its corresponding terminal.Type: GrantFiled: June 9, 2004Date of Patent: January 3, 2006Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal, Frank Guo
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Patent number: 6977840Abstract: A few times programmable (FTP) storage element is provided. The FTP storage element includes a set of N elementary memory units and multiple selection circuits. Each of the elementary memory units includes an address bus for connection to a main address bus and a data bus for connection to a main data bus. The selection circuits generate successive selection signals for successively selecting one of the elementary memory units in order to give exclusive access to the one selected elementary memory unit. The selection circuits operate so as to automatically select a next one of the elementary memory units upon detection of a predetermined condition. In preferred embodiments, each of the elementary memory units is programmable.Type: GrantFiled: June 3, 2003Date of Patent: December 20, 2005Assignee: STMicroelectronics S.A.Inventors: Richard Fournel, Jean-Pierre Schoellkopf, Philippe Candelier
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Patent number: 6977837Abstract: A semiconductor memory is formed of first, second, third, fourth, fifth and sixth field effect transistors. The first and second transistors have a first line as gates, one ends of current paths of the first and second transistors are connected to a reference potential electrode. The third and fourth transistors have a second line as gates, and one ends of current paths of the third and fourth transistors are connected to the reference electrode. The fifth transistor has a first word line as a gate, and one end of a current path of the fifth transistor is connected to the other ends of the current paths of the first and second transistors. The sixth transistor having a second word line as a gate, and one end of a current path of the sixth transistor is connected to the other ends of the current paths of the third and fourth transistors.Type: GrantFiled: March 18, 2004Date of Patent: December 20, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Watanabe, Kazunari Ishimaru
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Patent number: 6967866Abstract: A dummy MOSFET including a dummy gate separates nMOSFETs included in adjacent memory cells arranged in the direction in which bit lines extend. This configuration reduces a stress applied from an STI to the channel regions of the nMOSFETs. Accordingly, decrease of drive currents of the nMOSFETs is suppressed.Type: GrantFiled: March 16, 2004Date of Patent: November 22, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akio Hirata, Toshiyuki Moriwaki, Tetsurou Toubou, Nana Okamoto, Mitsuaki Hayashi
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Patent number: 6961262Abstract: Device and method for memory cell isolation. The memory cell includes a resistive component, such as a magnetic random access memory (MRAM) cell, and an isolation component, such as a four-layer diode. The memory cell may be included in a memory array. The method includes rapidly applying a forward bias across the isolation element to activate the isolation element.Type: GrantFiled: August 13, 2003Date of Patent: November 1, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventor: Frederick A. Perner
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Patent number: 6944054Abstract: A non-volatile memory array includes a plurality of memory cells, each cell receiving a bit line, word line, and release line. Each memory cell includes a cell selection transistor and a restore transistor with first, second and third nodes. Each cell further includes an electromechanically deflectable switch, the position of which manifests the logical state of the cell. Each cell is bit selectable for read and write operations.Type: GrantFiled: March 26, 2004Date of Patent: September 13, 2005Assignee: Nantero, Inc.Inventors: Thomas Rueckes, Brent M. Segal, Bernhard Vogeli, Darren K. Brock, Venkatachalam C. Jaiprakash, Claude L. Bertin
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Patent number: 6940751Abstract: A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor. Further, a gate dielectric of the transistor has a higher breakdown voltage near the source connected to the row wordline than its drain.Type: GrantFiled: January 26, 2004Date of Patent: September 6, 2005Assignee: Kilopass Technologies, Inc.Inventors: Jack Zezhong Peng, Michael David Fliesler
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Patent number: 6927997Abstract: The present invention relates to an OTP ROM using a CMOS gate oxide antifuse.Type: GrantFiled: June 14, 2004Date of Patent: August 9, 2005Assignee: Korea Advance Institute of Science and TechnologyInventors: Kwyro Lee, Jinbong Kim, Hyouk-Kyu Cha
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Patent number: 6922356Abstract: A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold voltage values for operation. During reading of the transistor, a gate threshold voltage between the two values is applied and the status of the transistor as on or off is determined to determine the program state of the transistor. The program state of the transistor can be determined by a simple latch circuit.Type: GrantFiled: April 2, 2004Date of Patent: July 26, 2005Assignee: Micron Technology, Inc.Inventor: Greg A. Blodgett
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Patent number: 6903966Abstract: Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the amplified current to an associated read data line.Type: GrantFiled: June 9, 2004Date of Patent: June 7, 2005Assignee: Hitachi, Ltd.Inventors: Takeshi Sakata, Satoru Hanzawa, Hideyuki Matsuoka, Katsuro Watanabe, Kenchi Ito
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Patent number: 6903967Abstract: A memory having gate structures adjacent opposing sidewalls of a semiconductor structure including a channel region and a plurality of charge storage locations between the gate structures and the opposing sidewalls. The channel region is located between two current terminal regions, which in one example serve as the source/drain regions. A memory cell can be implemented in an array of memory cells wherein one gate structure is coupled to one word line and the other gate structure is coupled to another word line. In one example, each cell includes four charge storage locations, each for storing one bit of data.Type: GrantFiled: May 22, 2003Date of Patent: June 7, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Leo Mathew, Robert F. Steimle, Ramachandran Muralidhar
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Patent number: 6898098Abstract: A method for configuring an associative array within a molecular-junction-nanowire crossbar, and nanoscale associative arrays configured by the method Keys are encoded as field-effect transistors selectively configured within the molecular-junction-nanowire crossbar, and values associated with keys are encoded as diodes selectively configured at molecular-junction-nanowire-crossbar junctions. Keys input into key registers result in a current signal indicating whether or not the key is stored within the associative array as part of a key/value pair and, if stored in the associative array, the value associated with the input key is output.Type: GrantFiled: January 31, 2003Date of Patent: May 24, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Greg Snider, Philip J Kuekes
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Patent number: 6898116Abstract: A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor. Further, the row wordline is formed from a buried N+ layer allowing for higher density integration.Type: GrantFiled: October 2, 2003Date of Patent: May 24, 2005Assignee: Kilopass Technologies, Inc.Inventor: Jack Zezhong Peng
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Patent number: 6888739Abstract: Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions. A gate insulator is formed opposing the channel region. The gate insulator includes a number of high work function nanoparticles. A gate is formed on the gate insulator. A plug is coupled to the first source/drain region and couples the first source/drain region to an array plate. A transmission line is coupled to the second source/drain region. The MOSFET is a programmed MOSFET having a charge trapped in the number of high work function nanoparticles in the gate insulator adjacent to the first source/drain region.Type: GrantFiled: June 21, 2002Date of Patent: May 3, 2005Assignee: Micron Technology Inc.Inventor: Leonard Forbes
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Patent number: 6888740Abstract: A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.Type: GrantFiled: July 23, 2002Date of Patent: May 3, 2005Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 6888770Abstract: A semiconductor memory device includes: a device substrate having a semiconductor layer separated by a dielectric layer from a base substrate; a memory cell array having a plurality of memory cells formed and arranged on the semiconductor layer of the device substrate, each the memory cell having a MOS transistor structure with a body in an electrically floating state to store data based on a majority carrier accumulation state of the body; and a sense amplifier circuit configured to perform data read out of the memory cell array, the sense amplifier circuit including a bipolar transistor for performing current amplification of a memory cell selected during data reading.Type: GrantFiled: July 11, 2003Date of Patent: May 3, 2005Assignee: Kabushiki Kaisha ToshibaInventor: Tamio Ikehashi
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Patent number: 6888769Abstract: The required refresh rate of a DRAM is reduced by biasing active digit lines to a slight positive voltage to reduce the sub threshold current leakage of access transistors in memory cells that are not being accessed. The slight positive voltage is provided by a voltage regulator circuit using one or more bipolar transistors fabricated in a well that electrically isolates the bipolar transistors from the remainder of the substrate. The voltage provided by the voltage regulator is preferably coupled to the access transistors by powering each of the n-sense amplifiers in the DRAM with the voltage from the voltage regulator.Type: GrantFiled: August 29, 2002Date of Patent: May 3, 2005Assignee: Micron Technology, Inc.Inventor: Howard C. Kirsch
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Patent number: 6888748Abstract: A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold voltage values for operation. During reading of the transistor, a gate threshold voltage between the two values is applied and the status of the transistor as on or off is determined to determine the program state of the transistor. The program state of the transistor can be determined by a simple latch circuit.Type: GrantFiled: July 7, 2003Date of Patent: May 3, 2005Assignee: Micron Technology, Inc.Inventor: Greg A. Blodgett
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Patent number: 6882576Abstract: A semiconductor memory device includes a memory cell array in which memory cells each having six transistors 11a, 11b, 12a, 12b, 13a and 13b are arranged two-dimensionally on a semiconductor substrate. The semiconductor memory device also includes a plurality of word lines connected to each of the memory cells, and arranged on a parallel to each other along a first direction, a plurality of bit lines connected to each of the memory cells and arranged on a parallel to each other along a second direction perpendicular to the first direction, and at least two gate electrodes provided on the semiconductor substrate such that each of the gate electrodes is connected to at least one transistor of the six transistors, all of the gate electrodes 3a, 3b, 3c and 3d being arranged on the same straight line parallel to the first direction.Type: GrantFiled: July 9, 2003Date of Patent: April 19, 2005Assignee: Renesas Technology Corp.Inventor: Hidemoto Tomita
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Patent number: 6879509Abstract: The present invention provides a read-only memory (ROM) architecture. An exemplary ROM array includes a plurality of columns, a plurality of rows, a first plurality of transistors or other switches representing a “0” data state or low voltage state, and a second plurality of transistors or other switches representing a “1” data state or high voltage state. Each transistor has a corresponding drain coupled to a column and a gate coupled to a row. Each transistor of the first plurality has a source coupled to a source voltage bus, and each transistor of the second plurality has a source not coupled to the source voltage bus, through use of a programmable contact window during fabrication. In various embodiments, for a selected column, drains of pair-wise adjacent transistors share a common drain-column contact and common diffusion region.Type: GrantFiled: May 21, 2003Date of Patent: April 12, 2005Assignee: Agere Systems, Inc.Inventors: Donald A. Evans, Ross Alan Kohler, Nghia Q. Lam, Richard Joseph McPartland, Hai Quang Pham
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Patent number: 6856540Abstract: A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+region in the substrate underlying the gate of the transistor.Type: GrantFiled: May 30, 2003Date of Patent: February 15, 2005Assignee: Kilopass Technologies, Inc.Inventors: Jack Zezhong Peng, David Fong
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Patent number: 6853587Abstract: Structures and methods for vertical memory cell. The vertical memory cell includes a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate. The MOSFET has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A first transmission line is coupled to the first source/drain region. A second transmission line is coupled to the second source/drain region. The MOSFET is adapted to be programmed to have a charge trapped in at least one of a first storage region and a second storage region in the gate insulator and operated with either the first source/drain region or the second source/drain region serving as the source region.Type: GrantFiled: June 21, 2002Date of Patent: February 8, 2005Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 6845032Abstract: Non-volatile latch circuit 10 of the present invention comprises ferroelectric capacitor 1 provided with a first electrode 1a, second electrode 1b, and ferroelectric film 1c that lies between these electrodes; reset terminal Tre that is connected to first electrode 1a and a CMOS inverter element 2 that is connected to second electrode 1b of ferroelectric capacitor 1; voltage switching terminal Tpl that applies a voltage to second electrode 1b; switching element 5 that is connected between second electrode 1b and second input terminal Tpl and switches a voltage applied to second electrode 1b; and set terminal Tse that applies a voltage for switching on or off switching element 5, wherein the voltage generated in second electrode 1b caused by polarization retained by ferroelectric film 1c is higher than the threshold voltage Vtn of NMISFET 4 of CMOS inverter element 2.Type: GrantFiled: February 25, 2004Date of Patent: January 18, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Toyoda, Takashi Ohtsuka, Kiyoshi Morimoto
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Patent number: 6842370Abstract: Structures and methods for vertical memory cell. The vertical memory cell includes a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate. The MOSFET has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A first transmission line is coupled to the first source/drain region. A second transmission line is coupled to the second source/drain region. The MOSFET is adapted to be programmed to have a charge trapped in at least one of a first storage region and a second storage region in the gate insulator and operated with either the first source/drain region or the second source/drain region serving as the source region.Type: GrantFiled: May 4, 2004Date of Patent: January 11, 2005Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Publication number: 20040246778Abstract: A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate a type of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.Type: ApplicationFiled: July 2, 2004Publication date: December 9, 2004Inventor: Tsu-Jae King
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Patent number: 6813180Abstract: A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.Type: GrantFiled: August 8, 2003Date of Patent: November 2, 2004Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 6804136Abstract: Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A plug couples the first source/drain region to an array plate. A bitline is coupled to the second source/drain region. The MOSFET can be programmed by operation in a reverse direction trapping charge in the gate insulator adjacent to the first source/drain region such that the programmed MOSFET operates at reduced drain source current when read in a forward direction.Type: GrantFiled: June 21, 2002Date of Patent: October 12, 2004Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 6801450Abstract: Device and method for memory cell isolation. The memory cell includes a resistive component, such as a magnetic random access memory (MRAM) cell, and an isolation component, such as a four-layer diode. The memory cell may be included in a memory array. The method includes rapidly applying a forward bias across the isolation element to activate the isolation element.Type: GrantFiled: May 22, 2002Date of Patent: October 5, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventor: Frederick A. Perner
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Patent number: 6798693Abstract: A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes.Type: GrantFiled: September 18, 2001Date of Patent: September 28, 2004Assignee: Kilopass Technologies, Inc.Inventor: Jack Zezhong Peng