Abstract: The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.

Abstract: A semiconductor device of the present invention is a semiconductor device of a complementary MIS field effect transistor, wherein an anode of a first diode is connected to a silicon substrate of a first conduction type while a cathode of the first diode is connected to a first power supply while a cathode of a second diode is connected to a well of the other conduction type and an anode of the second diode is connected to a second power supply.

Abstract: The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.

Abstract: In a method for operating an SRAM MOS transistor memory cell, the memory cell comprises a 6-transistor memory cell composed of two inverters with feedback, each of which is connected to a bit line via a selection transistor which is driven by a word line. Both selection transistors are switched on when writing information to the memory cell. Only the first selection transistor is switched on, the other selection transistor remaining switched off, when reading the contents of the cell. In this way, the charge on only one bit line is changed when reading.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: A memory cell includes driver transistors constituting a cross coupled type flipflop, access transistors driven in response to a signal potential on a word line, and bipolar transistors for connecting the memory cell to bit lines. For the bit lines, a read load circuit including diode coupled p channel MOS transistors and cross coupled p channel MOS transistors is provided, which supplies current when activated, and latches the bit line potentials after a prescribed time period. Stable data reading at high speed with low current consumption even under low power supply voltage is ensured, without causing data destruction.

Abstract: A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants.

Abstract: Memory cells which are adjacent to each other along a column direction share a bipolar transistor driving the potential level of a corresponding bit line. Other memory cells which are adjacent to each other in the column direction share another bipolar transistor driving the potential level of another corresponding bit line. Each bipolar transistor drives the potential level of the corresponding bit line in response to storage information of a selected memory cell, whereby data can be read at a high speed with a low power supply voltage.

Abstract: A read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented. The diode-based structure also allows the packing density of the memory cells on the ROM device to be dependent on the line width of the polysilicon layers in the ROM device.

Abstract: A memory device is described which has an n-channel FET access transistor coupled between a memory cell and a data communication line. An NPN bipolar access transistor is also coupled between the memory cell and the data communication line in parallel to the n-channel access transistor. A base connection of the NPN bipolar access transistor is described as coupled to a body of the n-channel access transistor to control threshold voltage variations of the n-channel FET access transistor. During operation the n-channel FET access transistor is used for writing data to a memory cell, while the NPN bipolar access transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.

Abstract: In a SRAM cell including a bipolar transistor and a cut transistor, the threshold Vtheff (Driver) of driver transistor and the threshold Vtheff (Cut) of cut transistor are set such that they satisfy the expressions,Vtheff(Driver).gtoreq.?{log(1 .mu.A)}-{log(Vcc/10R)}!.times.S(1)?{log(1 .mu.A)}-{log((Ie.times.(1/(hFE+1)))/10)}!.times.S.ltoreq.Vtheff(Cut).ltoreq.?{log(1 .mu.A)}-{log(Vcc/R)}!.times.S(2)Vtheff(Cut)-S.ltoreq.

Abstract: A bipolar transistor is formed by forming a base region continuing from a source/drain region of an MOS transistor, as a link base region, and forming an emitter region at a bit line contact hole by impurity implantation. Alternatively, the bipolar transistor is formed by forming an intrinsic base region and an emitter region at a bit line contact hole by impurity implantation. The intrinsic base region is made deeper than the source/drain region. Further, the impurity of the intrinsic base region is made different from that of the link base region.

Abstract: For high-speed single-ended sensing of the signal from a (multi-port) SRAM cell, a configurable half-latch with 2 PFET feedback pathes is proposed, which can be set up either as a bleeder device in the system mode or as keeper devices in the test modes, controlled by a DC signal (TEST). The bleeder and keepers are attached to the bit line and gated by a small ratioed inverter serving as sense amplifier. In case of system mode, a low control signal is applied to the source of the bleeder to limit the bit line up-level to a threshold below the supply voltage Vdd. Thus, discharging the bit line when reading a `0` is fast. Reading a `1` is also fast by skewing the inverter to a PFET/NFET ratio below 1. For chip testing, the control signal is set high to enable the keepers which restore the bit line close to the supply voltage, even when large subthreshold currents try to discharge it via the unselected cells. This turns off the PFET of the inverter, thereby minimizing the DC current.

Abstract: A static, in-circuit programmable memory device is provided where the storage element employed is a bi-layer programmable resistor. A specialized programming and readout circuit is provided for each storage element, allowing a known word-line/bit-line memory architecture (commonly used with fuse type memories) to be adapted to a memory element that conducts in both of two different states. The programming and readout circuit may take the form of a merged bipolar/FET device. A bipolar transistor is used for programming and also provides a diode action to prevent sneak path currents from flowing when a storage element is not selected. The bipolar transistor may be a parasitic bipolar transistor. An FET is used for readout. Storage elements are paired, one storage element of each pair functioning as a reference element.

Abstract: Architectures for a ferroelectric memory which avoids the half select phenomenon and the problems associated with destructive readout. Non-destructive readout is provided by measuring current through the ferroelectric memory as a measure of its resistance. Information is stored in the ferroelectric memory element by altering its resistance through a polarizing voltage. The half select phenomenon is avoided by using isolation techniques. In various embodiments, zener diodes or bipolar junction transistors are used for isolation.

Abstract: A nondestructive read, three device BICMOS gain cell for a DRAM memory having two FETs and one bipolar device. The gain cell has an improved access time (less latency), can operate for longer periods of time before a refresh operation is required, requires a smaller storage capacitance than a traditional DRAM cell, and can be produced commercially at lower costs than are presently available. In a preferred embodiment, the gain cell comprises an n channel metal oxide semiconductor field effect write transistor having its gate connected to a write word line WLw. Its drain is connected to a storage node Vs having a storage capacitance Cs associated therewith, and its source is connected to a write bit line BLw. An n channel metal oxide semiconductor field effect read transistor has its gate connected to the storage node Vs and its source connected to a read word line WLr. A PNP transistor has its base connected to the drain of the read transistor and its emitter connected to a read bit line BLr.

Abstract: An SRAM memory cell is provided in which a pair of cross-coupled n-type MOS pull-down transistors are coupled to respective parasitically formed bipolar pull-up transistors. The memory cell is formed within a semiconductor layer which extends over a buried layer. The bipolar transistors are formed parasitically from the buried layer and the semiconductor layer used to form the pull-down transistors. The bases of the bipolar transistors may also be dynamically controlled. An SRAM memory array having a plurality of such memory cells and a computer system incorporating the SRAM memory array are also provided.

Abstract: Bit lines (BL, /BL) are equally held low by a low-level precharge circuit (212) and an equalizing circuit (218) at time (t1) prior to a read operation. A read signal (/READ) and an equalization signal (EQ) go low at time (t2) when the read operation starts to provide "H" to word lines (WLU, WLL). If storage nodes (N1, N2) store "H" and "L" respectively, a bipolar transistor (BP2) is activated when the bit line (/BL) reaches a potential (+Vbe). Then, the potential of the bit line (/BL) does not rise to a power supply potential (VCC) but is held at the potential (+Vbe). Current flows to the bit line (/BL) through a reading load circuit (211) transiently (for a time period between times t2 and t3), but no current flows to the bit line (/BL) in a steady state (for a time period between times t3 and t4).

Abstract: A floating gate diode which can be used as a sourceless memory cell, and which may be arranged into an array of memory cells is disclosed. The floating gate diode comprises: a drain region formed in a substrate; an oxide overlying and associated with the drain region; and a floating gate overlying the oxide. Upon application of a voltage to the drain, a current between the drain and substrate is induced in proportion to an amount of electrons stored on the gate. The cells may be arranged into an array which comprises a substrate having a surface; a plurality of drain regions, one of said drain regions respectively corresponding to one of the plurality of cells, formed in the substrate; an oxide region overlying the plurality of drain regions on the surface of the substrate; and a plurality of floating gates overlying the oxide and respectively associated with the plurality of drain regions.

Abstract: In accordance with the teachings of the present invention, a programmable integrated transducer amplifier circuit is provided which receives differential outputs from a transducer, such as a pressure or accelerometer transducer. The programmable integrated transducer amplifier circuit includes binary adjustable circuits that are programmed in response to binary coded signals. The binary adjustable circuits generate binary weighted currents that are employed to adjust the operating characteristics of the amplifier circuit. The binary coded signals are received from a programmable memory array which includes a plurality of memory cells that store binary information. Each of the memory cells are programmed when coupled to a programming signal. Additionally, the memory array has pretest capability for testing outputs of the memory cells prior to permanently programming the respective memory cells.

Abstract: A memory cell includes first and second driver transistors, first and second access transistors and first and second load elements, and in addition, first and second bipolar transistors. Accordingly, static noise margin is enlarged. The first bipolar transistor has its emitter formed in one of the source/drain regions of the first access transistor. The collector of the first bipolar transistor is the backgate terminal of the first access transistor. One of the source/drain regions of the first access transistor functions as the base of the first bipolar transistor. The same applies to the second bipolar transistor and the second access transistor. As the memory cell is structured in the above described manner, lower power supply potential can be used without the problem of latch up or increased area.

Abstract: A current memory cell comprises a first bipolar transistor providing a current source and coupled to the emitters of a second and a third bipolar transistor, the latter forming the storage elements of the memory cell. The memory cell is calibrated, to avoid mismatch between the second and third transistors, by adjustment of the current source via a parallel arrangement of a resistor and a field effect transistor in the emitter circuit of the first transistor.

Abstract: A static RAM includes pre-amplifiers, which are made up solely of emitter-follower transistors having their collectors supplied with the power voltage, in one-to-one correspondence to sub common data line pairs which are connected by column switches to complementary data line pairs of memory arrays. The pre-amplifier is provided with a first switch which turns on during the selected state to connect the sub common data line pair to the bases of the transistors and a second switch which turns on during the unselected state to provide the bases with a certain bias voltage lower than the readout signal voltage on the sub common data line pair. The emitter-follower transistors have their emitters connected commonly to form common emitter lines, which are connected to pairs of input terminals of main amplifiers made up of CMOS transistors.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: A non-volatile semiconductor device can be obtained which is capable of enhancing integration level and performing accurate control of operations. A memory cell transistor of the semiconductor device in accordance with the present invention has a gate dielectric film including a ferroelectric film between a gate electrode and a semiconductor region. A back electrode is formed at the semiconductor region in a position corresponding to the gate electrode. A channel is formed at a channel formation region of the semiconductor region by applying a voltage to the back electrode, and the ferroelectric film is polarized as desired by the difference in potential between the channel and the gate electrode. Information can thus be written into the memory cell.

Abstract: A plurality of static memory cells including CMOS flip-flops and switching MOS transistors are connected in series, thereby forming a memory cell unit in which one end of data reading is connected to bit lines. A series of the memory cell units are arranged, thereby forming a memory cell array. Reset terminals are provided for releasing cell data and causing the cell to function temporarily as a transfer gate of data.

Abstract: A sense amplifier including a presense amplifier and a main sense amplifier. The presense amplifier detects a potential difference between a pair of bit lines based on information read from memory cells and outputs a pair of current signals in accordance with the detected potential difference. The main sense amplifier amplifies the pair of current signals from the presense amplifier to output a first pair of voltage signals. The main sense amplifier provides an output current which allows the first pair of current signals to flow through the presense amplifier. The main sense amplifier includes a current supply circuit for outputting a second pair of current signals based on the amount of the first pair of current signals output from the presense amplifier, and a converting circuit for converting the second pair of current signals from the current supply circuit to voltage signals and outputting the voltage signals.

Abstract: A semiconductor integrated circuit memory device has at least two logic blocks, each logic block including at least two logic units and each logic unit having a number of metal oxide semiconductor field effect transistors (MOS FET's) integrated therein. Bipolar transistors for driving the MOS FET's are selectively arranged between the logic blocks and/or the logic units so as to shorten a critical path of a logic block. The memory device may include a word driver circuit having a bipolar transistor connected to MOSFETs in an address decoder and memory cells of the memory device. The memory device may also include a sense circuit having a bipolar transistor for high speed discharge of a bit line, as well as an output buffer including a bipolar transistor for reducing signal transmission delays in driving a bus.

Abstract: A semiconductor memory includes a plurality of first memory cell arrays, a pair of first common data lines which are provided for the plurality of first memory cell arrays, and a sensing section including a pair of first bipolar transistors whose emitters are respectively connected to the first common data lines and first constant current sources. Each first memory cell arrays includes a plurality of second memory cell arrays, a pair of second common data lines, a first differential amplifier including a second constant current source and a pair of second bipolar transistors whose bases are respectively connected to the second common data lines, whose bases are connected to the second constant current source together, and whose collectors are connected to the first common data lines, and a third constant current source of a second differential amplifier.

Abstract: In a non-volatile semiconductor memory device having a writing power source voltage which is supplied thereto exceeding a withstand voltage of a field effect transistor, the object of the present invention is to reduce the number of kinds of field effect transistors constituting the non-volatile semiconductor memory device thereby reducing manufacturing cost. In a non-volatile semiconductor memory device which has a writing circuit 125 for controlling a connection of a writing load to a bit line designated by an output of a column decoder 117 in accordance with a signal of a writing data line 114, and a bias circuit 118 for outputting a bias voltage to set a cell writing voltage of a memory cell array by reducing the writing power source voltage.

Abstract: A pair of driving bipolar transistors of a lateral type T1 and T2 have emitters coupled to a ground potential, collectors connected to a pair of highly resistive elements R1 and R2. Highly resistive elements R1 and R2 have respective other ends coupled to power supply potential V.sub.CC, and bases and collectors of transistors T1 and T2 are cross-connected to each other, thereby forming a flipflop circuit. Access MOS transistors Q3 and Q4 having a gate potential controlled by word line WL are each connected to form a conduction path between one of storage nodes A and B and one of the pair of bit lines BL and /BL.

Abstract: An integrated circuit fuse circuit includes a plurality of fuses each connected to an output terminal, and a plurality of fuse programming circuits, a respective one of which is connected between a respective fuse and a reference voltage. Each of the fuse programming circuits includes a pair of complementary bipolar transistors and a field effect transistor. The pair of complementary bipolar transistors produce a large current through the associated fuse in response to a fuse programming signal which is applied to the field effect transistor. The fuse programming circuit may be fabricated in an integrated circuit by providing first and second spaced apart regions of second conductivity type in a well of first conductivity type, and a third region of the first conductivity type in the first region. An insulated gate is provided on the face between the first and second spaced apart regions. An insulated fuse is also provided on the face, electrically connected to the third region.

Abstract: A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states.

Abstract: A current amplification type mask-ROM having a bipolar junction transistor. The current amplification type mask-ROM includes a collector grounding part disposed in each of the plurality of bipolar junction transistors one by one, and a ground line for connecting the collector grounding part to a cell grounding part formed in one end of a cell array.

Abstract: Each of memory cells has one MOS transistor including a drain region, a source region, a channel region and a gate electrode. An impurity-introducing area of the channel region is varied in the width direction of the channel region to store data of plural bits in the memory cell.

Abstract: A SRAM includes an ECL input buffer connected between an address bus and a W-OR predecoder array. The logic output of the W-OR predecoder array is applied to a level translator array and level shifted. The level shifted output of the level translator array is supplied to a plurality of self-resetting word-line decoder and driver (WLDD) circuits. The WLDD circuits supply activation pulses to selected blocks of memory in a memory cell array. Sense amplifiers sense and latch-in the data stored in the activated selected blocks of memory. The design of the W-OR predecoder array, level translator array, WLDD circuits and sense amplifiers is such to reduce the overall power consumption of the SRAM.

Abstract: This invention presents a new SRAM cell comprising only two MOSFETs: one is the access device for data transfer; and the other is operated as a high gain gated lateral BJT in the reverse base current mode so as to constitute the role of the storage flip-flop or latch. This invention also requires only one-sided peripheral circuitry for Read/Write function. Thus the chip area is greatly saved. In addition, the invention is fully compatible with the existing low-cost, high-yield standard CMOS process.

Abstract: An improved memory type multi-ported data storage device is disclosed. The storage device operates to overcome the cell stability problems associated with the prior art by unidirectionally isolating memory cells of the multi-ported data storage device from read ports of the multi-ported data storage device. The unidirectional isolation operates to prevent external signals from the read ports and read port loading from influencing data stored in the memory cells, but continues to allow the memory cells to be read by the read ports associated therewith. The improved multi-ported data storage device not only allows simultaneous access to its memory cells by a large number of read ports without fear that cell stability will cause corruption of the memory cells, but also requires only a minimal amount of additional die area. Moreover, access time is independent of the number of ports being simultaneously accessed.

Abstract: A "zener-zap" memory cell with pretest capability for testing effects that would be realized from permanently programming the memory cell is provided. The memory cell is addressable and provides a binary signal at an output. The memory cell uses a zener diode as a memory element which is permanently programmed when selectively coupled to a programming voltage which exceeds the reverse breakdown voltage of the zener diode. The memory cell has a test circuit for generating the programmed binary signal at the output of the memory cell prior to permanently programming the zener diode and when coupled to a pretest voltage.

Abstract: A synchronous integrated circuit memory (30) has read global data lines shared between data read from a memory array (32) and data read from a data-in register (40) during a read-after-write. A comparator/latch (50) compares a new address to a previous address and generates an address match signal that is used to select match sense amplifiers (52) and deselect regular sense amplifiers (54). Relatively fast address comparison and address match signal generation is accomplished using a comparator/latch (50) for each column address signal, and emitter summing each match signal to provide the address match signal. The use of emitter summing reduces a number of gate delays, thus allowing the address match signal to be generated before the regular sense amplifiers (54) can be selected, and allowing the read global data lines to be shared without increasing the access time of the integrated circuit memory (30).

Abstract: In a memory cell array, memory cells are formed in a matrix. Bit lines are formed to be connected to prescribed memory cells. Emitters of bipolar transistors are connected to bit lines. Bipolar transistors have their bases connected to each other, and further to precharge signal control means. Collector regions of bipolar transistors are connected to a power supply node. Bipolar transistors have a base region formed by introducing a p type impurity to the entire main surface of the semiconductor substrate, and n type impurity concentration included in the collector region immediately below the base region is at most 5.times.10.sup.18 cm.sup.-1. Consequently, a semiconductor memory device having a bipolar transistor which is capable of high speed operation and having high reliability can be manufactured at low cost.

Abstract: A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Circuitry is provided so that all floating gate storage devices can be programmed to their target voltages individually or in parallel. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A transistor structure with a lightly doped drain is provided for control of the tunneling structure. A capacitor is connected to each floating gate node to provide control of the injection structure. A dynamic analog storage element is provided to store the target voltage for the floating gate storage device. A comparator is provided to monitor the floating gate voltage and target voltage and control tunneling and injection. A digital storage device is provided to statically store the output of the comparator.

Abstract: A buried layer which is highly doped and implanted with high energy in a lightly doped isolated well in which an array of flash EPROM cells are provided. The buried layer is doped with the same conductivity dopant as the well in which it is provided, for example a p.sup.+ -type buried implant is provided in a p-type well. The buried layer enables channel size of the flash EPROM cells to be reduced providing a higher array density. Channels of the flash EPROM cells are reduced because the buried layer provides a low resistance path between channels of the flash EPROM cells enabling erase to be performed by applying a voltage potential difference between the gate and substrate of a cell.

Abstract: A memory device that does not need to be refreshed and that has a relatively small size. The memory device includes a memory cell having a first PNP transistor, wherein an input voltage is provided to its base and its emitter is ground and a second NPN transistor having its base connected to the collector of the first transistor and its emitter connected to a power source, and wherein the collector of the second transistor is connected to the base of the first transistor.

Abstract: Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage.

Abstract: Disclosed is a data reading process as well as an improved semiconductor memory device. Input data supplied to the memory device is written in one of memory cells via a pair of bit lines when a write enable signal is active. After writing of the input data is completed, an equalizing circuit is activated to equalize the potential levels of bit lines used in data writing. An output circuit of the memory device is controlled such that the input data is forcibly output as output data from the memory device during the equalization immediately after writing of the input data is completed.

Abstract: An integrated circuit memory (30) having redundancy shares read, global data lines shared between a regular memory array (35) and a plurality of redundant columns (41). Redundant data and regular data are multiplexed onto the read global data lines by emitter summing bipolar transistors of regular sense amplifiers (46) with a redundant multiplexer (83). When a redundant column is used to replace a defective regular column, a match circuit (88) generates a match signal for selecting a redundant multiplexer circuit (84, 85, or 86) and for deselecting a corresponding regular sense amplifier (46). The match circuit (88) includes emitter summing circuits (230, 240) to rapidly generate the match signal.

Abstract: A semiconductor memory device has a plurality of memory cells arranged in rows and columns, a plurality of pairs of complementary first and second bit lines arranged corresponding to respective columns and connecting memory cells on a corresponding column, first and second read data lines, and a plurality of pairs of first and second bipolar transistor provided for respective pairs of first and second bit lines. Each first bipolar transistor is coupled to the first read data line and each second bipolar transistor is coupled to the second read data line and a plurality of first switching circuits transfer potentials of the first and second bit lines to respective bases of corresponding first and second bipolar transistors. A reference line transmits a non-selection level voltage and a plurality of second switching circuits, operating complementary to the corresponding first switching circuits, transfer the non-selection level voltage to bases of corresponding first and second bipolar transistors.

Abstract: A semiconductor memory device includes a current driving transistor composed of a bipolar transistor which is coupled to a corresponding bit line for increasing the bit line current. The collector of the current driving transistor is constituted by a well coupled to ground and the base is constituted by a common drain region of two adjacent string selecting transistors. The emitter of the current driving transistor is a separate polysilicon layer disposed from among a first interlayer insulating layer and a second interlayer insulating layer and the emitter is coupled to both the base region and the bit line through contact holes. Otherwise, the emitter of the current driving transistor is a doping region formed in the base region which serves as the common drains of two adjacent string selecting transistor.The memory device has the effect that the operation speed is increased and the integration density can be increased, so as to reduce the cost thereof.

Abstract: The present invention has an object to provide a memory device without the necessity of refreshment, whose circuit is small size.A memory device structuring a memory cell by connecting the follows: i) the first transistor of PNP type, having connection of input voltage to its base and grounding an emitter; ii) the second transistor of NPN type having connection of base to a collector of the first transistor, grounding collector and connection of power source to an emitter; and iii) the collector of the second transistor to the base of the first transistor.