Charge Coupled Patents (Class 365/183)
  • Patent number: 10185331
    Abstract: An enclosure design facilitates heat dissipation from a space-limited computer core device. An external computer platform is provided to connect the computer core device, the external computer platform including a fan that provides an air flow to the connected computer core device. The computer core device and the computing platform may be tightly connected by connectors located on their respective enclosure walls. Both the computer core device and the external computing platform are provided air inlets and outlets on their respective enclosures. When connected, an air inlet of the computer core device faces an air outlet of the external computing platform such that a single cooling air flow flows through the external computing platform and the computer core device. The external computing platform may include a built-in fan to blow air into or draw air from the matching air inlets and outlets.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: January 22, 2019
    Assignee: ICE COMPUTER, INC.
    Inventors: Shang-Che Cheng, Wei-Han Wu, Chia-Ming Lin
  • Patent number: 10111763
    Abstract: A non-contact capacitive sensing system for robotic lower-limb prosthesis, comprising a sensing front end, a signal sampling unit and a signal processing unit. The sensing front end is composed of capacitance electrodes inside the prosthetic socket, and the capacitance electrodes locate between the prosthetic socket and the stump sock. Each capacitance electrode forms a capacitor with the human body. The signal sampling unit is composed of the CTD module and the control module. The CTD module measures capacitance values by calculating the ratio of discharge-and-recharge cycles between the under-test capacitors and the reference capacitor. The signal processing unit comprises the filter module and the communication module. The capacitive sensing system is highly repeatable in signals, resistant to sweat, and reliably dressed on a human body. The system performs well regardless of residual limb length and residual muscle strength. It can be widely used in the field of robotic lower-limb prosthesis.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: October 30, 2018
    Assignee: Peking University
    Inventors: Enhao Zheng, Qining Wang, Kunlin Wei, Long Wang
  • Patent number: 9653128
    Abstract: The present disclosure provides systems and methods for storing, reading, and writing data using particle-based acoustic wave driven shift registers. The shift registers may physically shift particles along rows and/or columns of wells through the interactions of two parallel surfaces. A transducer may generate an acoustic wave to displace one or more of the two parallel surfaces. The particles may be transferred to and/or otherwise constrained by a buffer surface during at least a portion of the acoustic wave, such that the particles may be shifted during one or more cycles of the acoustic wave. In various embodiments, the amplitude of the acoustic wave may correspond to the spacing distance between each of the wells. The wells may be physical and/or potential wells.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: May 16, 2017
    Assignee: ELWHA LLC
    Inventors: Philip Lionel Barnes, Hon Wah Chin, Howard Lee Davidson, Kimberly D. A. Hallman, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Brian Lee, Richard T. Lord, Robert W. Lord, Craig J. Mundie, Nathan P. Myhrvold, Nicholas F. Pasch, Eric D. Rudder, Clarence T. Tegreene, Marc Tremblay, David B. Tuckerman, Charles Whitmer, Lowell L. Wood, Jr.
  • Patent number: 9484457
    Abstract: A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Till Schloesser
  • Patent number: 9422614
    Abstract: An Fe-based amorphous alloy of the present invention has a composition formula represented by Fe100-a-b-c-x-y-z-tNiaSnbCrcPxCyBzSit, and in the formula, 1 at %?a?10 at %, 0 at %?b?3 at %, 0 at %?c?6 at %, 6.8 at %?x?10.8 at %, 2.2 at %?y?9.8 at %, 0 at %?z?4.2 at %, and 0 at %?t?3.9 at % hold. Accordingly, an Fe-based amorphous alloy used for a powder core and/or a coil encapsulated powder core having a low glass transition temperature (Tg), a high conversion vitrification temperature (Tg/Tm), and excellent magnetization and corrosion resistance can be manufactured.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: August 23, 2016
    Assignee: ALPS GREEN DEVICES CO., LTD.
    Inventors: Keiko Tsuchiya, Hisato Koshiba, Kazuya Kaneko, Seiichi Abiko, Takao Mizushima
  • Patent number: 9093266
    Abstract: An isolation structure, such as a trench isolation structure, may be formed by forming an aperture in a semiconductor substrate and then filling the aperture with boron. In some embodiments, the aperture filling may use atomic layer deposition. In some cases, the boron may be amorphous boron. The aperture may be a high aspect ratio aperture, such as a trench, in some embodiments.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: July 28, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Silvia Borsari, Carla Maria Lazzari
  • Publication number: 20140104942
    Abstract: A recess gate transistor includes: a drain region and a source region in a semiconductor substrate and doped with first-type impurities; a recess region recessed in the semiconductor substrate between the drain region and the source region; a gate insulation layer on the recess region, a gate electrode on the gate insulation layer filling the recess region; and a charge pocket region below the recess region and doped with second-type impurities. A semiconductor chip includes a plurality of recess gate transistors, and an image sensor includes a semiconductor chip including a plurality of recess gate transistors.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 17, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Gu JIN, Ju Hwan JUNG, Yoon Dong PARK
  • Patent number: 8654566
    Abstract: The semiconductor device includes a memory cell including a first transistor including a first channel formation region, a first gate electrode, and first source and drain regions; a second transistor including a second channel formation region provided so as to overlap with at least part of either of the first source region or the first drain region, a second source electrode, a second drain electrode electrically connected to the first gate electrode, and a second gate electrode; and an insulating layer provided between the first transistor and the second transistor. In a period during which the second transistor needs in an off state, at least when a positive potential is supplied to the first source region or the first drain region, a negative potential is supplied to the second gate electrode.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: February 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shuhei Nagatsuka, Takanori Matsuzaki, Hiroki Inoue, Kiyoshi Kato
  • Patent number: 8634222
    Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: January 21, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Akira Goda
  • Patent number: 8559220
    Abstract: The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is formed on or in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: October 15, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 8537622
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells provided in a matrix and having a charge storage layer, a plurality of word lines provided on the charge storage layer, and an application section. When reading data from a selected memory cell selected from the plurality of memory cells, the application section applies a voltage having an opposite polarity to the voltage applied to a selected word line to non-selected word lines arranged on both adjacent sides of the selected word line.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: September 17, 2013
    Assignee: Spansion LLC
    Inventors: Fumiaki Toyama, Yukihiro Utsuno
  • Patent number: 8530000
    Abstract: Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. The charge-trapping zones may be incorporated into flash memory cells.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Patent number: 8315097
    Abstract: A memory string is configured by a plurality of memory transistors and a spare memory transistor connected in series. Word lines are connected to gates of the memory transistors. A spare word line is connected to a gate of the spare memory transistor. The memory string comprises a first semiconductor layer, a charge storage layer, a plurality of first conductive layers, and a second conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a substrate. The charge storage layer surrounds a side surface of the first semiconductor layer. The plurality of first conductive layers surround a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and function as the word lines. The second conductive layer surrounds a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and functions as the spare word line.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: November 20, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoo Hishida, Hitoshi Iwai, Yoshihisa Iwata
  • Patent number: 8305802
    Abstract: There is provided a technology which can allow a semiconductor chip formed with a nonvolatile memory to be sufficiently reduced in size. There is also provided a technology which can ensure the reliability of the nonvolatile memory. In a memory cell of the present invention, a boost gate electrode is formed over a control gate electrode via an insulating film. The boost gate electrode has the function of boosting a voltage applied to a memory gate electrode through capacitive coupling between the boost gate electrode and the memory gate electrode. That is, during a write operation or an erase operation to the memory cell, a high voltage is applied to the memory gate electrode and, to apply the high voltage to the memory gate electrode, the capacitive coupling using the boost gate electrode is subsidiarily used in the present invention.
    Type: Grant
    Filed: October 23, 2010
    Date of Patent: November 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Takashi Hashimoto
  • Patent number: 8233326
    Abstract: There is provided a semiconductor non-volatile memory including: plural memory sections, a voltage application section, and a control section that controls the voltage application section wherein the control section controlling voltage application such that, based on a value of current detected by a current detection section, in a region where the current flowing in a channel region is greater than a predetermined target value at which a amount of charge accumulated has become a specific value in at least one of a first charge accumulating section or a second charge accumulating section, when a value of current flowing in the channel region approaches a target value, a rate of increase in the charge accumulating amount per time is decreased at least once.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: July 31, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takashi Yuda
  • Patent number: 8213225
    Abstract: Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a source each formed in silicon and a gate positioned between the drain and the source. The memory cell may further include a bias gate recessed into the silicon and positioned between an isolation region and the transistor. In addition, the bias gate may be configured to be operably coupled to a bias voltage. The memory cell may also include a floating body within the silicon. The floating body may include a first portion adjacent the source and the drain and vertically offset from the bias gate and a second portion coupled to the first portion. Moreover, the bias gate may be formed adjacent to the second portion.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: July 3, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 8004901
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells that are provided in a matrix and that have a charge storage layer made of an insulating film that is provided on a semiconductor substrate and a plurality of word lines that are provided on the charge storage layer. A plurality of memory cells that are arranged in a single line among the plurality of memory cells arranged in the matrix are coupled to the same word line. The semiconductor device further includes an application section that when reading data from a selected memory cell selected from the plurality of memory cells, applies a voltage to a selected word line to be coupled to the selected memory cell among the plurality of word lines. The application section applies a voltage that has a polarity that is opposite to the voltage applied to the selected word line to non-selected word lines arranged on both adjacent sides of the selected word line.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: August 23, 2011
    Assignee: Spansion LLC
    Inventors: Fumiaki Toyama, Yukihiro Utsuno
  • Patent number: 7929343
    Abstract: Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a source each formed in silicon and a gate positioned between the drain and the source. The memory cell may further include a bias gate recessed into the silicon and positioned between an isolation region and the transistor. In addition, the bias gate may be configured to be operably coupled to a bias voltage. The memory cell may also include a floating body within the silicon. The floating body may include a first portion adjacent the source and the drain and vertically offset from the bias gate and a second portion coupled to the first portion. Moreover, the bias gate may be formed adjacent to the second portion.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: April 19, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 7715267
    Abstract: A driving circuit includes a first switch, a first driver and a second driver. The first switch has a first terminal coupled to a first voltage. The first driver includes a second switch and a third switch. The second switch has a first terminal coupled to a second terminal of the first switch, and a second terminal coupled to a first capacitor. The third switch has a first terminal coupled to the second terminal of the second switch, and a second terminal coupled to a second voltage. The second driver includes a fourth switch and a fifth switch. The fourth switch has a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to a second capacitor. The fifth switch has a first terminal coupled to the second terminal of the fourth switch, and a second terminal coupled to the second voltage.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: May 11, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Kuang Chen, Chun-Hsiung Hung
  • Patent number: 7480179
    Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: January 20, 2009
    Assignee: SanDisk Corporation
    Inventor: Yan Li
  • Patent number: 7443729
    Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: October 28, 2008
    Assignee: SanDisk Corporation
    Inventors: Yan Li, Yupin Fong
  • Patent number: 7002872
    Abstract: A semiconductor memory device includes a core block having sub-arrays and sense amplifier regions. First and second charge storing regions are disposed at sides of the core block. First and second decoupling capacitors are formed at the first and second charge storing regions, respectively. A plurality of first voltage supply lines are disposed to supply a power supply voltage to the sense amplifier regions and are connected to one electrode of each of the first and second decoupling capacitors. A plurality of second voltage supply lines are disposed to supply a ground voltage to the sense amplifier regions and are connected to the other electrode of each of the first and second decoupling capacitors.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: February 21, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyong-ryol Hwang, Young-hun Seo, Jae-yoon Sim
  • Patent number: 6807604
    Abstract: A method of refreshing a dynamic memory intended for storing variables involved in operations performed by a processor, includes a step of planning 10 in the course of which an order and a timing of the operations are established, a step of estimating 13 a retention time specific to each variable, a step of forecasting 14 at least one instant at which each variable must be refreshed, a step of placement 15 in the course of which the variables are placed in the memory, a step of refreshing 16 in the course of which the variables are refreshed at the instants defined during the forecasting step 14. The method allows a reduction in the latency times and in the consumption of current which are related to the refreshing. It is of particular benefit in systems where the real time constraint is important, for example, video data processing systems.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: October 19, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Marc Duranton
  • Patent number: 6759721
    Abstract: An integrated memory location structure includes an isolated semiconductor layer between the source region and the drain region of a transistor, and between the channel region and the control gate of the transistor. The isolated semiconductor layer includes two potential well zones separated by a potential barrier zone under the control gate of the transistor. A write circuit biases the memory location structure to confine charge carriers selectively in one of the two potential well zones. A read circuit biases the memory location structure to measure the drain current of the transistor and determine therefrom the stored logic state imposed by the position of the charges in one of the potential well zones.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: July 6, 2004
    Assignee: STMicroelectronics SA
    Inventors: Thomas Skotnicki, Alexandre Villaret
  • Patent number: 6426238
    Abstract: A charge transfer device is provided, capable of preventing degradation of the charge transfer efficiency when the channel width becomes narrower due to the narrow channel effect. The charge transfer device of the present invention is obtained by forming a charge transfer electric field in a channel below a boundary portion between a terminal storage electrode and a terminal barrier electrode, which constitute a pair of charge transfer electrodes located closest to the output electrode, to be higher than a charge transfer electric field in a channel below a boundary portions of pairs of storage electrodes and barrier electrodes, which constitute pairs of storage electrodes and barrier electrodes other than the pair of the terminal electrodes.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: July 30, 2002
    Assignee: NEC Corporation
    Inventor: Michihiro Morimoto
  • Patent number: 6319668
    Abstract: Combinations, called matrices with memories, of matrix materials that are encoded with an optically readable code are provided. The matrix materials are those that are used in as supports in solid phase chemical and biochemical syntheses, immunoassays and hybridization reactions. The matrix materials may additionally include fluophors or other luminescent moieties to produce luminescing matrices with memories. The memories include electronic and optical storage media and also include optical memories, such as bar codes and other machine-readable codes. By virtue of this combination, molecules and biological particles, such as phage and viral particles and cells, that are in proximity or in physical contact with the matrix combination can be labeled by programming the memory with identifying information and can be identified by retrieving the stored information. Combinations of matrix materials, memories, and linked molecules and biological materials are also provided.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: November 20, 2001
    Assignee: Discovery Partners International
    Inventors: Michael P. Nova, Hanan Potash, Xiao-Yi Xiao, Zahra Parandoosh, Gary S. David
  • Patent number: 6212095
    Abstract: A charge pump coupling circuit is described for more efficiently coupling a final capacitive stage of a charge pump to a capacitive load. The coupling circuit is has primarily resistive characteristics to allow for a greater load voltage. The resistive coupling circuit in one embodiment is included in a memory device for coupling a charge pump to a memory array word line. The resistive coupling circuit can be either a single resistor, a plurality of resistors, or a coupling circuit which has substantially resistive characteristics.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: April 3, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Christophe J. Chevallier
  • Patent number: 6181630
    Abstract: A system for preventing data loss when volatile memory is used to store data either internal or external to a host computer. In the preferred embodiment, the system provides uninterrupted power to the volatile memory and to a non-volatile storage device such as a magnetic disk drive or other non-volatile memory. Upon loss of commercial power, host computer shut down, or manual initiation, the data stored in the volatile memory will be automatically backed-up to the non-volatile storage device via a high bandwidth data path. Under normal conditions, data stored in volatile memory are accessible by the host computer using a high bandwidth data path.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: January 30, 2001
    Assignee: Genatek, Inc.
    Inventor: Jason Robert Caulkins
  • Patent number: 6040992
    Abstract: A charge pump coupling circuit is described for more efficiently coupling a final capacitive stage of a charge pump to a capacitive load. The coupling circuit is has primarily resistive characteristics to allow for a greater load voltage. The resistive coupling circuit in one embodiment is included in a memory device for coupling a charge pump to a memory array word line. The resistive coupling circuit can be either a single resistor, a plurality of resistors, or a coupling circuit which has substantially resistive characteristics.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: March 21, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Christophe J. Chevallier
  • Patent number: 6036834
    Abstract: A method and device for the electrolytic formation of a deposit on a group of electrodes of an electrolysis support. The support has a plurality of electrodes. Electric charges are selectively deposited on chosen electrodes. The support is placed in the presence of an electrolyte to produce the deposit on the chosen electrodes by electrolysis. The electric charges deposited on the electrodes provide an electrolysis current for each chosen electrode. The formed device may be used as a biological sensor.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: March 14, 2000
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Jean-Frederic Clerc
  • Patent number: 5949708
    Abstract: A charge pump coupling circuit is described for more efficiently coupling a final capacitive stage of a charge pump to a capacitive load. The coupling circuit is has primarily resistive characteristics to allow for a greater load voltage. The resistive coupling circuit in one embodiment is included in a memory device for coupling a charge pump to a memory array word line. The resistive coupling circuit can be either a single resistor, a plurality of resistors, or a coupling circuit which has substantially resistive characteristics.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: September 7, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Christopher J. Chevallier
  • Patent number: 5610580
    Abstract: A motion detection and imaging method and device 10 for carrying out the method are provided. The device 10 comprises a housing 12 containing a CCD 18 for providing digital image data, a lens 16 for focusing an image on the CCD 18 and a solid state non-volatile memory 24 for storing the digital image data. In one embodiment, the device includes a motion detector 26 for triggering the storage of the digital data.
    Type: Grant
    Filed: August 4, 1995
    Date of Patent: March 11, 1997
    Inventor: Joseph M. Lai
  • Patent number: 5485597
    Abstract: A memory device for storing analog or multilevel data which is easy to produce and of a small scale. The memory device according to the present invention circulates data between a plurality of linear CCD arrays which store data as electrical charges, allows high speed memory access by reading and writing data through cache memory which stores row addresses corresponding to CCD arrays, and includes an address register for registering the address of cache memory data.
    Type: Grant
    Filed: May 6, 1993
    Date of Patent: January 16, 1996
    Assignee: Yozan Inc.
    Inventor: Makoto Yamamoto
  • Patent number: 5420812
    Abstract: A bidirectional-type charge coupled device in which the directions of the signal flow can be changed by an external controlling signal.
    Type: Grant
    Filed: June 7, 1994
    Date of Patent: May 30, 1995
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Young J. You
  • Patent number: 5386384
    Abstract: A fully parallel CCD memory chip of N address lines which detects in just one clock cycle, a perfect match between an input pattern and any of a plurality of stored patterns and also detects in less than (N+1)-comparison cycles and still just one XOR operation, the best matching in case a perfect one does not exist. The chip disclosed herein has a fully parallel architecture in which an input word is compared to all stored words at one time. A preferred embodiment of the invention uses a four phase CCD, wherein each stored word occupies one row of the CCD and each such bit of each such word occupies two cells. Where perfect matches exist, only one comparison clock cycle is needed to compare the input word with all stored words and where there is no perfect match, the best match will be detected on a subsequent comparison pulse. Charge packets represent binary words generated by external pulses that are applied to the chip through data input lines and then are compared to the data applied to the address lines.
    Type: Grant
    Filed: March 9, 1993
    Date of Patent: January 31, 1995
    Assignee: California Institute of Technology
    Inventors: Volnei A. Pedroni, Amnon Yariv, Aharon J. Agranat
  • Patent number: 5379252
    Abstract: The present invention provides a memory device for realizing an analog memory that or a multilevel memory easy to produce and requires only small scale circuitry. The memory device comprises: a CCD array "Ai" linearly arranged a refresh circuit "R" connected to a CCD on one end CCD array; a shaping circuit connected to a CCD on another end of the CCD array; a feedback line "FL" for connecting an output the shaping circuit to an input of the refresh a topology difference clock line "CL" for transmitting data CCD array.
    Type: Grant
    Filed: April 6, 1993
    Date of Patent: January 3, 1995
    Assignee: Yozan Inc.
    Inventor: Makoto Yamamoto
  • Patent number: 5373464
    Abstract: The present invention provides a memory device for preventing data circulating on a plural number of linear CCD array from being corrupted, for accessing data at a high speed, and for reducing the device's electric power consumption.A memory device according to this invention downsizes a block of a memory cell by circulating data on a plural number of linear CCD arrays which are for storing data by an electric charge on a cell and keeping analog data, which sets a clock generation means for circulating data on all arrays and another clock generation means for circulating at a high speed only the array loops having necessary data.
    Type: Grant
    Filed: June 16, 1993
    Date of Patent: December 13, 1994
    Assignee: Yozan Inc.
    Inventors: Sunao Takatori, Makoto Yamamoto
  • Patent number: 5339275
    Abstract: An improved analog memory arrangement is interfaced to receive digital signals through a digital to analog converter and is interfaced to output analog signals through an analog to digital converter. Analog refreshing is implemented to reduce degradation of analog signals stored by the analog memory including scale factor refreshing and bias refreshing. The analog memory is particularly suitable for illumination signal processing and for storing display images to be displayed.
    Type: Grant
    Filed: March 16, 1990
    Date of Patent: August 16, 1994
    Inventor: Gilbert P. Hyatt
  • Patent number: 5289408
    Abstract: A scanning tunneling microscope memory apparatus comprises first and second integrated circuit (IC) substrates. First and second cantilevers, which can be moved by piezoelectric elements, are arranged on the first and second IC substrates, respectively. Tunnel current probes are provided on a free end of the first cantilever, and a recording element is provided on a free end of the second cantilever. The first and second cantilevers are spaced from each other and overlap such that the tunnel current probes face the recording element. The first or second substrate includes a charge coupled device (CCD) circuit, a control circuit for controlling the CCD circuit and cantilevers, and a drive circuit having a preamplifier, a write circuit, and a servo circuit.
    Type: Grant
    Filed: April 23, 1992
    Date of Patent: February 22, 1994
    Assignee: Olympus Optical Co., Ltd.
    Inventors: Yoshiyuki Mimura, Hiroshi Kajimura, Toshihito Kouchi, Akitoshi Toda, Yasuo Isono, Hiroko Ohta, Ryouhei Shimizu
  • Patent number: 5168463
    Abstract: An apparatus for storing digital data includes a clock pulse source and plural serial shift register stages storing data bits. Digital data signals, each having plural databits, are coupled to and shifted in the stages in synchronization with the clock pulses. Data stored in the memory stages stages are held in a non-erasable memory unit provided for each stage while an emergency causing a failure of a power supply of the shift register occurs.
    Type: Grant
    Filed: February 23, 1989
    Date of Patent: December 1, 1992
    Assignee: Nissan Motor Company, Ltd.
    Inventors: Hiroshi Ikeda, Norio Fujiki, Masaki Hirota
  • Patent number: 5111436
    Abstract: Two dimensional charge coupled device (CCD) memories are coupled to acoustic charge transport devices (ACT) which act as input and/or output multiplexers for the memories. In a preferred embodiment of the invention, the input to a NXM memory is in the form of an optical image projected on the CCD device and the output stage of each column of the memory is provided to one of N FET switches. A 1-D ACT device has multiple taps each connected to the gate of one of the FET switches and as an impulse signal propagates along the ACT channel, the FET switches are successively triggered causing the column outputs to be provided to a summing device to generate a serial output.In an alternative embodiment forming a corner-turn memory, an ACT tapped delay line has a number of equally spaced electrode taps equal to the number of columns of a CCD corner-turn array and each tap is connected to an electrical switch which in turn is connected to an input cell of a bordering row of the array.
    Type: Grant
    Filed: October 17, 1990
    Date of Patent: May 5, 1992
    Inventors: Nikola S. Subotic, Michael T. Eismann
  • Patent number: 5077762
    Abstract: There is provided a one-dimensional MIM array having MIM structures arranged on an insulative substrate in a lateral direction and each used as a unit for storing a signal charge, for sequentially storing and transferring the signal charges between the adjacent MIM structures. With the above element structure, the signal charge is transferred in each of the MIM structures in a thickness direction (depth direction) thereof and stored in a capacitor. The signal charge stored in the capacitor is sequentially transferred in a lateral direction or to the next MIM structure. In order to drive the above charge transfer device, transfer pulses applied to a plurality of MIM structures constituting a one-dimensional MIM array are controlled to sequentially transfer and store the signal charges into the MIM structures starting from the MIM structure which is provided on the output terminal side of the one-dimensional MIM array.
    Type: Grant
    Filed: September 18, 1990
    Date of Patent: December 31, 1991
    Assignee: Olympus Optical Co., Ltd.
    Inventors: Masamichi Morimoto, Hiroshi Nakano, Yoshiyuki Mimura
  • Patent number: 5030953
    Abstract: A full search block matching algorithm includes a charge-domain serial tapped delay line as an input buffer, and an array of charge domain signal processors. The delay line shifts and holds analog sampled data which are in the form of charge packets. At each stage of delay, the signals are nondestructively sensed and coupled to a corresponding signal processor, and the sampled data are transferred and subsequently processed in parallel. The processed data from all the processors can be read out either in a parallel or serial format through a parallel-in-serial-out output buffer. In this structure, only the serial input buffer has to be clocked at the system throughout rate; the internal clock rate of each processor is reduced by the number of parallel processors. Within each processor, all of the computation functions are performed in the charge domain, and local charge domain memories are included for storing the processed signal.
    Type: Grant
    Filed: July 11, 1990
    Date of Patent: July 9, 1991
    Assignee: Massachusetts Institute of Technology
    Inventor: Alice M. Chiang
  • Patent number: 5018172
    Abstract: In a charge-coupled SPS memory device, in which the transport takes place according to the "pushing" principle, it may occur that during the SP transport charge is injected into the substrate and diffuses via the substrate into the memory mat. In order to avoid this undesired injection of charge, the input is provided with means by which it is ensured that the storage site under the input gate is entirely empty during the SP transport.
    Type: Grant
    Filed: March 5, 1990
    Date of Patent: May 21, 1991
    Assignee: U.S. Philips Corp.
    Inventor: Frits A. Steenhof
  • Patent number: 4992982
    Abstract: An SPS charge coupled device memory is described which is useful for storing video pictures. The memory avoids accumulation of charge below the de-interlacing electrodes controlling the transfer of data to the series output register by using two different procedures for generating the de-interlacing clocks for the odd channels and for the even channels of the parallel section. These procedures are carried out sequentially with an adjustable difference in time.
    Type: Grant
    Filed: October 3, 1988
    Date of Patent: February 12, 1991
    Assignee: U.S. Philips Corporation
    Inventor: Frits A. Steenhof
  • Patent number: 4987558
    Abstract: In dynamic memories, generally a fluctuation of 10% of the nominal value of the supply voltage is allowed. Since, when reading, the input gate is applied to the supply, this fluctuation in the supply results in 20% of fluctuation in the charge packet formed below the input gate. In order to eliminate this fluctuation and hence to increase the permitted interference margin for other interference sources, a voltage stabilization circuit is arranged between the supply voltage and the input gate so that the fluctuation in the supply also occurs at the source zone, as a result of which the size of the charge packet becomes independent of the supply. For the voltage stabilization circuit, use may advantageously be made of a band gap reference.
    Type: Grant
    Filed: March 31, 1989
    Date of Patent: January 22, 1991
    Assignee: U.S. Philips Corp.
    Inventor: Arie Slob
  • Patent number: 4951302
    Abstract: A two phase shift register comprises four serial registers each having an input section, a transfer section, and a lead-in section disposed between the input section and the transfer section. The input sections provide respective sequences of charge samples, the four sequences being offset in phase relative to each other by 90.degree. within the cycle of a clock signal. At least one of the serial registers comprises a first lead-in gate pair and a second lead-in gate pair over the lead-in section, the second lead-in gate pair being between the first lead-in gate pair and the transfer section. The first lead-in gate pair and the second lead-in gate pair are each driven at the frequency of the clock signal, the drive signal applied to the second lead-in gate pair being retarded in phase relative to that applied to the first lead-in gate pair by 90.degree. within the cycle of the clock signal.
    Type: Grant
    Filed: June 30, 1988
    Date of Patent: August 21, 1990
    Assignee: Tektronix, Inc.
    Inventors: Joseph R. Peter, Raymond Hayes
  • Patent number: 4947371
    Abstract: An analog dynamic memory circuit comprises a time delay element with a variable delay time feedback loop and a time delay element control device which changes the delay time of the time delay element every time when an analog signal circulates in the feedback loop. This analog dynamic memory circuit prevents or avoids superposition of noise signals which have the same phase in the loop circuit, with the result that amplification of noise and tuned waves in the circuit is prevented.
    Type: Grant
    Filed: March 29, 1989
    Date of Patent: August 7, 1990
    Assignee: Addams Systems Inc.
    Inventor: Tomohiko Suzuki
  • Patent number: 4916664
    Abstract: A charge transfer device having a first storage gate above a first storage region and a second storage gate above a second storage region. The charge duplicator has a first charge injector having a first passage gate which introduces, below the first storage gate, the reference charge to be duplicated. A second charge injector having a second passage gate is located near the second storage gate. The first storage gate and second storage gate are connected to the two inputs of a voltage comparator, the output of the voltage comparator being connected to the second passage gate. The charge duplicator has a mechanism which initially is used to apply a reference voltage to the two inputs of the voltage comparator, thereby leaving the two inputs and the gates connected to them in a floating state. The voltage comparator outputs a high level or low level, depending on the value of the differential voltage between its inputs.
    Type: Grant
    Filed: January 3, 1989
    Date of Patent: April 10, 1990
    Assignee: Thomson-CSF
    Inventors: Jean-Luc Berger, Marc Arques
  • Patent number: 4881250
    Abstract: A charge-coupled device has a semiconductor body defining a charge transfer channel. Charge storage and charge transfer electrodes are provided for, respectively, defining charge wells within the charge transfer channel and transferring charge between charge wells. Two clock lines provide clock signals to the charge storage and transfer electrodes for controlling movement of charge between charge wells and to an output connection of the charge transfer channel. Signal processing means in the form of a sense amplifier are provided for processing an output from the charge transfer channel and a conductive path connects the output connection and the signal processing means. The conductive path crosses at least one of the clock lines and a conductive shielding layer extends between and is electrically isolated from the said at least one clock line and the conductive path.
    Type: Grant
    Filed: July 7, 1988
    Date of Patent: November 14, 1989
    Assignee: U.S. Philips Corp.
    Inventors: Geert J. T. Davids, Wiegert Wiertsema