Abstract: Disclosed is an electronic data storage of the type wherein data is entered and read out serially. In a conventional serial-parallel-serial configuration, data is serially entered into an input register and then transferred and stored in parallel through the main section of the storage until data is transferred in parallel to the output register from which the data is read serially. In a conventional line-addressable configuration, data is entered into and read from columns of shift registers where each column is addressable. The disclosed array combines the conventional serial-parallel-serial and the line-addressable structures into one array. This permits serial data to be read one row at a time as well as one column at a time.

Abstract: Disclosed is an electronic data storage of the type wherein data is entered and read out serially. In a conventional serial-parallel-serial configuration, data is serially entered into an input register and then transferred and stored in parallel through the main section of the storage until data is transferred in parallel to the output register from which the data is read serially. In a conventional line-addressable configuration, data is entered into and read from columns of shift registers where each column is addressable. The disclosed array combines the conventional serial-parallel-serial and the line-addressable structures into one array. By utilizing three phase clock lines and an inhibit line for each cell, the disclosed structure can be fabricated with two levels of gate electrodes.

Abstract: A charge transfer device has a means for grouping a charge transfer section of a semiconductor substrate into a plurality of semiconductor regions each provided with a plurality of charge transfer electrodes and storing a fixed information, predetermined correspondingly to a combination of surface potential levels to be formed at semiconductor subregions under the electrodes on each semiconductor region, in such semiconductor region.

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

Abstract: A gate electrode which is common to at least two CCD channels is formed with a "window" over one of the channels. A second gate electrode over the first controls the substrate potential of the one channel through the window but has no effect on the substrate potential of the other channel. The structure makes it possible to block or delay the propagation of charge in one channel relative to the other and is useful, for example, in structures for parallel-to-serial charge signal translation and vice versa.

Abstract: An electrode per bit (E/B) structure type charge transfer device in which N storage cell each consisting of a barrier region and a storage region are driven by N-phase clocks, one of N storage cells being empty and the remaining N-1 cells storing signal charge packets. The N-phase clocks are biased to a low level for storage and pulsed to a high level for transfer. The N storage cells are successively rendered in the transfer mode in the direction opposite to the charge transfer direction so that the empty cell is shifted to the adjacent preceding cell in the direction opposite to the charge transfer direction every time each of the N-phase clocks is pulsed. After one cycle of the N-phase clocks, all the signal charge packets are shifted to the succeeding cells respectively. A multiplexed electrode per bit (ME/B) structure type charge transfer device also is disclosed which employs the E/B structure and is operable by the clocks with small number of phases, providing a CCD memory with a large capacity.

Abstract: An improved arrangement is provided for processing analog and digital signals, where particular advantages are obtained using charge coupled devices (CCDs). A memory arrangement utilizes a novel refresh circuit to re-establish signal amplitudes which are degraded by a CCD memory. Further, various gating and control circuits are used for loading and unloading the memory. A CCD signal processor and memory arrangement is provided for in an embodiment of an array processing system to exemplify one application of these arrangements.

Abstract: A charge coupled device (CCD) register includes a first group of CCD cells coupled horizontally together. Each of the CCD cells includes a "first phase location" and a "second phase location". The register includes a plurality of CCD loops, each of the CCD loops beginning at the first phase location of a respective one of the CCD cells and ending at the second phase location of the same CCD cell. Each of the CCD loops includes the same number of sequentially coupled CCD cells. The CCD register has a very high density of CCD cells, and requires far fewer regeneration devices than a serial CCD register with the same number of CCD cells.

Abstract: A data storage system for storing multilevel, non-binary data includes a charge coupled device (CCD) shift register and a detection circuit for detecting the data level represented by the charge or signal within each cell location of the CCD shift register. The detection circuit includes a sense amplifier for comparing the signals from two adjacent cell locations, with one signal representing a known data level. The comparison of adjacent cell locations compensates for signal losses during shifting, since the losses experienced by adjacent cell locations are nearly identical. Switching transistors cause the output of an incrementing digital-to-analog converter to be added to one of the signals prior to comparison. The output of the sense amplifier is provided to a flip-flop, which controls the switching transistors. The outputs of the sense amplifier and flip-flop are connected to an EXCLUSIVE NOR gate, whose output enables an up/down counter, which in turn provides the detected data level.

Abstract: Charge-coupled device (CCD) including a plurality of parallel CCD channels and common electrodes extending over these channels for controlling the flow of charge in the channels. Potential barrier regions are located beneath certain of the electrodes in certain of the channels, each pair of barrier regions separated by a normal channel region, and voltages are applied to the electrodes at levels such that charge in a channel containing the barrier regions is trapped and temporarily delayed in the normal channel region between the barrier regions relative to the propagation of charge in a channel not containing barrier regions. The structure is useful, for example, in tree networks for parallel-to-serial signal translation and vice versa.

Abstract: Each memory cell of an x-y addressable semiconductor memory includes a charge storage element serially connected with an I-O (bit) line through a pair of CCD-type transfer gates. One gate is responsive to x-addressing and the other gate to y-addressing.When an x-y address is selected only the charge storage element of the one selected memory cell communicates with the bit line.

Abstract: A data storage system having a charge coupled device (CCD) shift register and a detection circuit for detecting the binary value represented by the charge level or signal within each cell location of the CCD shift register. The detection circuit includes a sense amplifier for comparing the signals from two adjacent cell locations, with one signal representing a known binary value. The comparison of adjacent cell locations compensates for signal losses during shifting, since the losses experienced by adjacent cell locations are nearly identical. Switching transistors cause an adjustment voltage to be added to one of the signals prior to comparison. The output of the sense amplifier is provided to a flip-flop, which in turn has an output initially set at the known binary value and which controls the switching transistors.

Abstract: A conductor-insulator-semiconductor (CIS) structure for a random access surface charge memory system is disclosed. The memory system comprises an array of memory cells including charge storage regions, charge transfer regions and charge receive-source regions formed along the surface-adjacent portions of a semiconductor substrate. A charge-storage line insulatingly overlies the storage regions of a row of memory cells and a bit line, comprising an extended region of opposite-conductivity-type, interconnects the receive-source regions of the same memory cells. Addressing in the Y-direction (word selection) is provided by charge transfer lines insulatingly overlying the charge transfer regions of a column of memory cells. Selected memory cells are addressed for read and write purposes by first activating the word select line which makes available one cell in each row of the memory. The desired row is then selected by means external to the array of memory cells.

Abstract: High vertical resolution can be obtained in a charge-coupled device (CCD) imager of the field transfer type by integrating charge in the A register in storage potential wells separated by potential barriers, with no empty potential wells separating the storage wells. Transfer of the integrated charge from the A to the B register at a speed which meets commercial television standards is obtained by employing a new type of multiple-phase clocking. Starting with the first row of charges S.sub.j =S.sub.1, the clock pulses successively separate each row of charges S.sub.j from the following row S.sub.j+1 by a space for a potential well and a potential barrier, and in synchronism with each such separation, the clock pulses shift the rows S.sub.j-1, S.sub.j-2. . . , if any, which previously have been separated, in unison, all by one row position. Then, after the first row of charges S.sub.

Abstract: Input sampling circuits are described for converting an analog signal into charge samples for charge transfer devices.

Abstract: A bidirectional serial-parallel-serial charge-coupled device wherein each serial section is both an input register and an output register, and serial streams of charge packets flow simultaneously in opposite directions in the parallel section. Odd data bits of a serial input stream flow into a first serial register and then through the parallel section in one direction and then out of the second serial register, while concurrently the even data bits flow into the second serial register and then through the parallel section in the opposite direction and then out of the first serial register. The data transfer rate is thereby substantially doubled.

Abstract: A CCD storage module has storage positions which are arranged in cascade and which are produced by electrodes arranged in insulated fashion above a semiconductor substrate. In respect of each storage position, an item of information incoming as a n-digit binary number is stored in that a quantity of charge consisting of i unit charges is stored in respect of each storage position, where i corresponds to the value of the binary number of the information. A decoder circuit is provided for the input of the quantity of charge to the first storage position. The decoder circuit consists of n input circuits and each input circuit is assigned one bit position of the information composed of n bits and produces a charge corresponding to the digit value of that position.

Abstract: A permutation memory comprises an input control means for decoding, having plurality L of inputs for an L-bit binary number, and a plurality 2.sup.L of outputs. Means are connected to the decoding means, for initiating the read-in of the L-bit number. Means are provided for applying an input signal. A first plurality of 2.sup.L of normally open switching means are connected to the 2.sup.L outputs of the decoding means and to the signal applying means. A plurality of 2.sup.L of means are connected to the switching means, for storing a charge when a specific switching means, connected to a corresponding charge storing means, is in a closed condition. A second plurality 2.sup.L of switching means are connected to the first plurality of switching means and to the charge storing means. An output control means, connected to the second plurality of switching means, reads out the states of the 2.sup.L charge-storing means, as to the amount of charge in each.

Abstract: A charge coupled device (CCD) serial memory has data read from or written into it at a sub-multiple rate of the data rate. The sub-multiple rate is determined by the number of interleaved blocks into which the CCD serial memory is divided.

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

Abstract: A CCD storage module has storage positions which are arranged in cascade and which are formed with the aid of electrodes arranged in insulated fashion above a semiconductor substrate. In respect of each storage position, an item of information, incoming as a binary number comprising n bits, is stored in that a quantity of charge composed of small i unit charges is stored in respect of each storage position, where i corresponds to the value of the binary number of the information. For analysis of the quantity of charge eminating from the last storage position of the cascade of storage positions, in a cascade with the last storage position (2.sup.

Abstract: A two phase charge coupled device memory array wherein the storage capacity is increased by using multiple levels of charge storage within a given cell. A voltage waveform generator capable of producing one of four different voltages is utilized to input and output charge in the multiple level charge method. In determining the level of charge stored within a given cell in the array, the voltage difference between a reference cell and an adjacent addressing cell is used. By determining the voltage level of the addressing cell at which charge overflows the reference cell and counting the number of times it overflows as the voltage generator is successively stepped through its four voltage levels, the level of the original charge input to a given cell can be determined. To make the multiple level scheme independent of process parameters and temperature, the same two cells are utilized for both input and output functions. Various other cells are provided to block and route charge with respect to the array.

Abstract: The problem of gradual dissipation of charge in charge packets in charge-coupled devices (CCDs) as the packets are successively shifted is overcome by a regenerator circuit which also provides a basic structure for effecting elemental logic and arithmetic functions. A standardized charge packet is injected along with a digitally valued but somewhat diminished charge packet into a potential well under a storage electrode arranged to retain a single charge packet. Overflow from the storage electrode region that represents only some part of a full charge packet is detected by a master sensing gate that controls a slave gate forming a shunt path for the full charge packet and that is normally maintained in a transfer state. The slave gate shifts to a barrier state when the overflow packet is present, however, permitting the full charge packet to advance along another electrode path.

Abstract: A method and apparatus is disclosed for a fast switching digital differential amplifier system useful in regenerating information signals in charge coupled devices. The amplifier system has a first capacitance at an input point which is charged and discharged in accordance with a binary "0" or binary "1" at the input. A second capacitance and an output capacitance is provided with a predetermined charge thereon. In the event of a binary "1", the predetermined charge on the second and output capacitance is retained while the first capacitance is discharged. In the event of a binary "0", the second and output capacitances are discharged via a current sink. A flip-flop is connected to the output capacitance for accelerating the discharge of the same. Switching transistors are additionally provided for activating the flip-flop to achieve the desired fast-switching.

Abstract: A charge transfer device in which series-parallel or parallel-series conversion of information which is present in the form of stored charge packets can take place and in which in a semiconductor body a row of charge storage sites is present in which beside said row several substantially parallel charge transfer registers are provided. The charge storage sites and the registers are interconnected by controllable charge transfer paths in the transverse direction so that charge packets can be distributed from the row between the registers or conversely charge packets distributed between the registers can be transferred to the row of storage sites.

Abstract: A functional and structural arrangement for charge-coupled device binary or multi-level storage systems of a modified serial-parallel serial type memory block arrangement wherein the output sequence is removed from the memory block proximate to the location where the original sequence was entered into the memory block. The structure includes two memory block portions designated as the left and right memory block portions. The input information sequence is entered into the upper left side of the right memory block portion in serial fashion, is moved in parallel to the bottom of the right memory block portion and serially removed from the lower left side of the right memory block portion and entered into the lower right side of the left memory block portion.

Abstract: A CCD (charge coupled device) RAM (random access memory) includes a plurality of "rings" of serially connected CCDs in which digital information recirculates. A combinational decoder selects one of the plurality of rings by decoding a first group of binary address inputs. Each ring includes a plurality of input/output circuits coupled to associated "taps", each tap being coupled between an input and an output of a CCD regeneration cell. An address addition circuit includes a counter which counts at the same rate that data shifts through each of the rings and has a plurality of taps spaced at the same intervals (numbers of intervening CCD cells) as the taps in each of the rings. The counter outputs are decoded to provide a first internal address corresponding to the location of a fictitious tag bit in a ring with reference to an initial reference bit in a ring.

Abstract: An array of rows and columns of charge transfer stages are provided. Each of the stages have identical sets of four electrodes. In response to a first set of clocking voltages applied to the sets of four electrodes charge packets are transferred from stage to stage in the column direction. In response to a second set of clocking voltages applied to the sets of four electrodes charge packets are transferred from stage to stage in the row direction.

Abstract: Insulated gate field effect transistor charge regenerator amplifiers respectively cross-couple the output regions of a pair of two-phase CCD structures with the input regions of those structures. Each amplifier senses the level of binary data charge packets from the output region of one of the shift register structures and in response thereto applies a regenerated and inverted binary data charge packet to the input region of the other shift register structure. One of the amplifiers includes logic gating for inputting and outputting data into and from the shift register structure.A charge regenerator for a two-phase CCD structure comprising first and second shift registers. The charge regenerator comprises a source follower amplifier including a driver transistor, a load transistor and a positive feedback transistor connected between the gate and source of the driver transistor.

Abstract: A solid state imaging device capable of converting one-dimensional or two-dimensional optical information into an electrical signal is disclosed. A signal charge stored in each of a plurality of photo-electric converter elements, which is proportional to the amount of incident light, is read into a corresponding stage of a charge transfer device through a switching transistor under the control of a read control pulse. The read control pulse is applied through a clock line of the charge transfer device so that the clock line is used both for read-in and for transfer. In this manner, one picture element of the imaging device is constructed of one photo-cell and two transistors whereby a high integration density of the solid state imaging device is attained.

Abstract: Disclosed is an interlaced serial-parallel-serial (SPS) charge coupled device (CCD) memory with improved clocking. By performing the interlacing as well as the serial-parallel-serial function with only seven clock pulses, less metallurgy and consequently less space per bit on a semiconductor chip is required. By reducing the number of clock requirements, the supporting logic circuitry is simplified permitting a larger portion of the semiconductor chip area to be used for data bit storage.

Abstract: A stabilized charge injector for charge coupled devices (CCD) includes a diffusion and two or more gate structures in a CCD channel wherein the diffusion alternately acts as a source and drain of the minority-type signal carriers. D.C. signals are applied to the gates immediately adjacent the diffusion and the next successive adjacent gate to provide a charge injection which is proportional to the difference between the signal voltage applied to the one of the two gates and a DC reference voltage applied to the other thereof. Low noise performance is achieved through utilization of a quasi-static operation in which neither of the aforementioned gates adjacent the diffusion is pulsed. Moreover, the use of a gate injector presents at the input, a true capacitance defined as a function of the gate oxide layer. Hence, the value of capacitance is constant and independent of the signal voltage applied.

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

Abstract: Signal processing apparatus is disclosed comprising a plurality of charge storage cells, each including first and second storage regions in a semiconductor substrate. Means are provided responsive to a scanning signal for introducing into each of the cells a respective quantity of charge, a first portion of which is contained in one of the storage regions and represents a respective analog signal sample. Means are provided for transferring each first portion of charge from one storage region to the other storage region in a respective cell in response to a respective second signal. Means are provided connected in circuit with the first electrodes for sensing the charge transferred to and from the first charge storage regions of the cells for detecting the signal samples.

Abstract: A CCD memory is comprised of an array of serial-parallel-serial memory blocks. Each block is comprised of an N-stage serial-parallel register, an M-stage stack, and an N-stage parallel-serial register. The serial-parallel register has N outputs which couple in parallel to N inputs of the stack. The parallel-serial register has N inputs which couple in parallel to N outputs of the stack. Both registers have a zig-zag shaped charge transfer path which reduces their linear dimension, and also reduces the width of the stack.

Abstract: A storage arrangement for use with CCD storage devices, the storage area having an input shift register and an output shift register each of m bits. 2m shift registers, each of length n bits and constructed using the electrode-per-bit principle connect the input shift register to the output shift register. A circular shift register of length n bits being connected to the gate input of n switching transistors each of which is connected between a supply potential and one of n pulse train lines of the storage area. A circulating charge in the circular shift register is the means whereby each one of the n switching transistors cyclically connects one of the n pulse train lines to the supply potential.

Abstract: A cell for a semiconductor memory of the static type employs two conventional MOS transistors along with a field implanted resistance which functions as a grounded-gate junction FET. Along with other resistor elements, these devices provide a grounded-gate amplifier with voltage gain and a source follower, creating a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.

Abstract: A semiconductor random access memory is described in which the datum stored in one memory cell can be recalled without having to recall, temporarily store, and then re-enter the data stored in a column of memory cells. Datum can also be entered into one memory cell without having to recall and subsequently re-enter the data in a column of memory cells. During the recall and enter processes, only one of the normally off sense amps needs to be powered up. Compared to prior art one-transistor memories, this memory consumes less power and has a faster write cycle.

Abstract: A memory system for analogue data includes a plurality of semiconductor charge device shift registers integrated on a semiconducor substrate. In one embodiment analogue data is serially inputed into a charge-coupled device (CCD) shift register. The serial data is converted to parallel and propagates at a substantially slower speed through a plurality of shift registers. A parallel-to-serial conversion provides a serial readout of the data. The serial-parallel-serial arrangement of the memory significantly reduces the number of transfers required to propagate one bit of data through the memory and provides correspondingly improved outputs. In a different aspect of the invention, a plurality of bits of digital data are transformed into a single analogue signal effecting a reduction in size of the memory for equal storage capability.

Abstract: Line imaging and area imaging devices are described which employ the concept of storage and transfer of charge carriers in a semiconductor medium by the application of appropriate potentials to electrodes disposed above the medium. The devices are characterized by two arrays of electrodes, one functioning as an optical sensing array and the other as a storage and readout array. Charge carriers are collected in the medium under the metal electrodes of the sensing array in proportion to incident light. This information is rapidly transferred to the storage and readout array by sequentially biasing series of electrodes of the two arrays. The information may then be read out of the array without smearing while the sensing array continues to integrate. The structure includes means for preventing cross-coupling and maintaining transfer efficiency for small area electrodes.

Abstract: An analog memory apparatus for storing and retrieving a sequence of samples of an analog signal is described. The apparatus includes a plurality of storage devices each storing each of the samples of the sequence with appropriate sign in accordance with a predetermined code. The samples stored in each device represent a respective algebraic sum of the samples of the sequence. To retrieve the samples of the analog signal the different algebraic sums of samples stored in the devices are algebraically summed in accordance with the predetermined code.

Abstract: A semiconductor memory produced in a unipolar technology includes a cell which has an inversion capacitor with one terminal connected to a bit/sense line, the other terminal is coupled to a source of charges by a pulse from a word line. To provide a word organized array of these cells, each word includes a source of charges produced at the surface of a semiconductor substrate and plurality of inversion capacitors are formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the capacitors by applying voltages of two different magnitudes, representing 1 and 0 bits of information, to one terminal of the capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors. The capacitors having the larger voltage store the greater amount of charge.

Abstract: Waveguides having light propagating therethrough are positioned between a common electrode and individual electrodes arranged along a charge-coupled device. The waveguides are of a type which modulate the propagating light responsive to an electric field. The charge-coupled device is activated to place charges at selected ones of the individual electrodes, creating a field across the waveguide by which light propagating through the waveguide is modulated.

Abstract: This disclosure relates to a charge coupled device memory that is content or associative addressable with the respective word locations (loops) being searched concurrently although word access is serial in manner. Data bits in respective word loops are arranged in a staggered manner such that when the first bit of the first word is at its comparison location, the second bit of the second word is at its comparison location and so forth. The comparand and mask bits are shifted serially from comparison location to comparison location and recirculated in synchronism with the recirculation of the word loops. Content addressing logic includes a series of match bit shift registers, one for each comparison location, to record match occurrences. When a word match occurs, the address of the respective word loop is sent to the memory to read out the data bits stored therein.

Abstract: A dynamic semiconductor memory cell which can be used in content addressable or associative memories is described. In the memory cell, a one is represented by storing a relatively large number of minority carriers in the potential well formed in a semiconducting substrate beneath a first storage electrode, and a zero is represented by storing a relatively large number of minority carriers in the potential well formed in a semiconducting substrate beneath a second storage electrode. The match zero operation is performed by extracting some of any of the minority carriers stored beneath the first storage electrode, which induces a relatively small potential change on that electrode if a zero is stored in the memory cell and induces a relatively large potential change on that electrode if a one is stored therein. Similarly, the match one operation is performed by interrogating the minority carriers stored in the potential well beneath the second storage electrode.

Abstract: Semiconductor memory cells include gate conductor-insulator-semiconductor regions having storage and transfer portions in which the threshold voltage and surface potential-gate conductor voltage characteristics differ as between the storage and transfer portions. This may be achieved by employing relatively thick and relatively thin insulator areas at the storage and transfer portions, or vice versa, with a surface charge accumulation layer at the semiconductor region insulator interface. In a different form of cell structure, the insulator is a uniform thickness layer overlying the storage and transfer portions one of which includes a doped semiconductor region of the same conductivity type as, but higher dopant concentration than, the remainder of the semiconductor region.

Abstract: A semiconductor memory device provided with one transferring electrode, one gate electrode and one diode of a charge coupled device is produced by a process with a reduced number of steps of diffusion and patterning. Both electrodes consists of doped polycrystalline silicon and both are electrically connected to a resistive layer which consists of non-doped polycrystalline silicon. A potential barrier between the region of both electrodes is removed due to the resistive layer. Resistive layer is formed by utilization of a two-stage deposition of the polycrystalline silicon layer with appropriate mashing steps.

Abstract: An FET read only memory array having bit locations arranged in rows and columns utilizes a dynamic array and static sensing. A dynamic first address selects the gate line of a selected column and a second address selects the source line or lines to select one or more bits within the selected column. The presence or absence of a gate at a selected bit location determines whether a first or second logic level is present at the sense or drain line serving the bit location. An additional column of FET bit positions each with a gate has the gate line activated toward the conclusion of the cycle to provide a path to ground for the elimination of any charge on a sense line in preparation for the next succeeding cycle. The sensed output from a selected bit location is latched until reset.

Abstract: The memory cells in the rows of a random access memory are divided in to subrows, and an access transistor is used selectively isolate or connect the output terminals of each subrow of memory cells to the row line. When recalling the datum from a memory cell, the subrow is isolated, and thus the loading of the output signal from that memory cell is reduced. Consequently, an improved output signal can be obtained from a memory cell with a given size storage capacitance, or a smaller storage capacitance can be used in the memory cell, or both.