Abstract: An analog dynamic memory circuit comprises a time delay element with a variable delay time feedback loop and a time delay element control device which changes the delay time of the time delay element every time when an analog signal circulates in the feedback loop. This analog dynamic memory circuit prevents or avoids superposition of noise signals which have the same phase in the loop circuit, with the result that amplification of noise and tuned waves in the circuit is prevented.

Abstract: A charge transfer device having a first storage gate above a first storage region and a second storage gate above a second storage region. The charge duplicator has a first charge injector having a first passage gate which introduces, below the first storage gate, the reference charge to be duplicated. A second charge injector having a second passage gate is located near the second storage gate. The first storage gate and second storage gate are connected to the two inputs of a voltage comparator, the output of the voltage comparator being connected to the second passage gate. The charge duplicator has a mechanism which initially is used to apply a reference voltage to the two inputs of the voltage comparator, thereby leaving the two inputs and the gates connected to them in a floating state. The voltage comparator outputs a high level or low level, depending on the value of the differential voltage between its inputs.

Abstract: A charge-coupled device has a semiconductor body defining a charge transfer channel. Charge storage and charge transfer electrodes are provided for, respectively, defining charge wells within the charge transfer channel and transferring charge between charge wells. Two clock lines provide clock signals to the charge storage and transfer electrodes for controlling movement of charge between charge wells and to an output connection of the charge transfer channel. Signal processing means in the form of a sense amplifier are provided for processing an output from the charge transfer channel and a conductive path connects the output connection and the signal processing means. The conductive path crosses at least one of the clock lines and a conductive shielding layer extends between and is electrically isolated from the said at least one clock line and the conductive path.

Abstract: A charge-coupled memory of the SPS type, in which the input of the series input register is coupled so as to be switchable to an n-bit shift register. The data can thus be read in directly or with a certain delay via the shift register. If an uninterrupted flow of bits is supplied, for example video information, a pause, during which no bits appear at the input of the input register, can be obtained by switching on the shift register in the supply of information to the input register, without information being lost. This pause can be utilized to transport information already read in to the parallel section. As a result, a matrix organization can be given to the memory, in which event the dissipation is lower, the transfer losses are smaller and at the same time a gain in surface area is obtained.

Abstract: The present invention provides a vertical punch-through cell comprising a silicon substrate, an epitaxial silicon layer overlying the substrate, an N+ buried column line formed at the interface between the substrate and the epitaxial layer, an N+ diffusion region formed above and spaced apart from the buried column line at the surface of the epitaxial layer, a field oxide layer formed over the epitaxial layer and having an contact opening formed therein over the N+ diffusion region, a polysilicon layer formed on the surface of the field oxide layer to extend through the contact opening to make contact with the N diffusion region, a layer of dielectric material formed over the polysilicon layer, and a layer of conductive material formed over the dielectric material.

Abstract: In an SPS charge transfer device comprising a parallel register having a plurality of signal transfer channels for transferring signal charges, and a first and a second serial registers, a plurality of noise transfer channels for transferring noise charges due to a dark current are formed adjacent to and parallel with the signal transfer channels. The signal charges are transferred through the signal transfer channels toward the second serial register, and then through the second serial register, while the noise charges are transferred through the noise transfer channels toward the first serial register, and then through the first serial register. The signal charges at the output end of the second serial register and the noise charges at the output end of the first serial register are used to produce signals representing the signal charges which are originally introduced into the parallel register, i.e., the signal charges from which the noise components due to the dark current have been removed.

Abstract: An analog image memory device using charge transfer and comprising:a memory zone of N lines of M memory points, each memory point being formed by the integration on the same semiconductor substrate of an MIS capacity separated from a diode by a screen grid,means for selecting each memory point,means for writing in each memory point a charge amount corresponding to the analog signal to be stored andmeans for reading the memory zone line by line after writing.

Abstract: A multilinear charge transfer array is provided formed by N lines of P photosensitie detectors. Each photosensitive detector is connected directly by a connection to a demultiplexing and reading system, the signals obtained at the output of the array being fed to a processing device external to the array.The demultiplexing system comprises a charge transfer shift register with N.times.P stages, the connections between each detector and the corresponding input of the register being provided so that the detectors of the same rank are connected to contiguous inputs.

Abstract: In order to clear at a high speed unwanted charge in a solid image sensing element of a charge transfer type, a potential barrier for allowing passage of excessive charge in the direction of the transfer of a CCD shift register, is provided. Also, in order to clear the charge of the CCD shift register via the barrier, an overflow drain is provided. Thus, the clearing action is effected at a high speed, and also, a blooming can be eliminated.

Abstract: A charge coupled device (CCD) analog shift register in a two-channel serial-parallel-serial (SPS) structure operating in a fast-in/slow-out (FISO) mode for high speed signal acquisition and temporary storage of a plurality of samples. The two CCD arrays are clocked simultaneously, and the input analog signal is demultiplexed to the two arrays. Additional transfer electrodes are provided at the input of one of the arrays, and the other array is provided with a sampling clock which is 180.degree. out of phase with the sampling clock of the first array; two consecutive samples of the input signal are taken during each transfer clock cycle. All signal samples are clocked through the arrays simultaneously and appear at the output at the same time.

Abstract: A dynamic closed-loop circulating analog memory, preferably embodied with monolithic charge coupled devices and employing a minimum number of serial data transfers, additive refresh signal processing, and dark current subtraction for limiting crosstalk degradation of the circulated signals.

Abstract: A series-parallel-series memory or other parallel-to-series CCD has charge-signals interlaced in alternate parallel channels 1a and 1b, and de-interlacing electrodes (19, 20, 21, 22) at the parallel-to-series transition. In order to avoid delay effects as a result of comb-shaped electrode configurations of the de-interlacing electrodes, and associated complex clock control, a narrow extra electrode (41) is provided between the de-interlacing electrodes and the series-output register (B). This electrode (41) may serve as a buffer electrode for each half row of information (from 1a or 1b) while the preceding half row (from 1b or 1a) is transported through the series output register.

Abstract: A digital memory comprises a charge coupled device (CCD) that includes a reference signal storage section. The digital input to the CCD includes an input reference signal and an information signal having a plurality of data levels, for example, a digital "0" and "1". The input reference signal includes a reference bit at the higher data level. The reference signal storage section divides the level of the reference bit to provide a reference level signal halfway between the two data levels. Thus, any shift in the data levels due, for example, to temperature changes in the CCD, affects the reference level signal to the same degree and the reference level can be kept exactly halfway between the data levels.

Abstract: Charge transfer device output signals typically include an information component which is contaminated with both on-chip amplifier noise and reset noise. For reducing these noise components, the device output signal is applied to first and second synchronous detectors. The first synchronous detector is responsive to a first reference carrier signal for maximizing at its output the information component while the second synchronous detector is responsive to a second reference carrier for maximizing at its output the noise components. The synchronous detector output signals are then differentially combined so as to substantially reduce the noise components from the contaminated information component.

Abstract: A high-density semiconductor memory with charge-coupling memory cells is disclosed. Each CC cell includes three field effect transistors and one capacitor, which are integrated in a small area by sharing their nodes with one another. A P.sup.+ type semiconductor layer of high-impurity concentration is formed in a shallow N type semiconductive layer and is electrically floating to function as the data storage capacitor. The potential corresponding to the data storage in the above P.sup.+ layer controls the readout current flowing through the N layer.

Abstract: The noise in the output signal from the floating diffusion output stage of a charge transfer device is reduced. Reset noise can be reduced by resetting the floating diffusion to an in-channel potential, rather than to the reset drain potential. Flicker noise or "1/f" noise in the electrometer stage following the floating diffusion is suppressed by high-pass or band-pass filtering the output signal samples, after which the filtered signal is synchronously detected against a harmonic of the clocking frequency of the charge transfer device to obtain full bandwidth output response. The filtering not only suppresses flicker noise or "1/f" noise, but also suppresses smear that afflicts output signal samples originating from a floating diffusion reset to an in-channel potential.

Abstract: Disclosed is a solid state imaging device which comprises an imaging unit having a plurality of picture cells arranged in at least one line for producing electrical information in response to incident radiation; a read-out unit for reading out said electrical information from said imaging unit, said read-out unit including m separate read-out channels, where m is an integer no smaller than three; and an input unit for dividing the electrical information in one line of said imaging unit into m groups, parallel-to-serial converting the respective groups of electrical information and supplying the serial information to said read-out unit.

Abstract: The invention relates to a charge-coupled SPS memory comprising a series input register, a parallel section and a series output register. In order to increase the retention time leakage current drain regions are provided beside the memory. Since the charge collected as a result of leakage current is largest during the transport through the outermost registers of the parallel section, only the sides of the parallel section are screened by the said draining regions which preferably consist of dummy registers. FIG. 1.

Abstract: An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and first storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage element of the output register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.

Abstract: Trade-off between dynamic range and sampling rate in a charge coupled device is virtually eliminated in the serpentine charge coupled device of the present invention. In this device, for each charge packet transferred in a first direction, a plurality of n charge packets are transferred in a second transverse direction in the serpentine register. Accordingly, for a given charge transfer rate in the first direction, the charge coupled device clock frequency is increased by a factor of n. The serpentine register is formed on the semiconductive substrate having two parallel channel stops extending in a first direction and a plurality of parallel interlaced channel stop fingers extending in a second direction which are alternately connected to the two parallel channel stops.

Abstract: A dynamic RAM memory comprised of a plurality of storage cells, each cell having its elements vertically stacked and using vertical charge coupling for charging and discharging the cell capacitor. The preferred embodiment of the cell comprises a semiconductive substrate having diffused into its upper surface a channel of opposite impurity concentration to that of the substrate for forming the bit line of the memory. An epitaxial layer is grown on the substrate surface to bury the bit line, a channel stop is diffused into the upper surface of the epitaxial layer to circumscribe the active cell area, and a thin insulator is disposed on the surface of the epitaxial layer with a conductive strip deposited thereon which form the word line of the memory. The thickness of the epitaxial layer, the impurity concentration of the buried channel and the epitaxial layer, together with the applied voltages, are selected for charge coupling operations.

Abstract: The present invention is directed to an analog memory for storing digital information in analog signal form. Typically, digital information is stored in digital signal form, where each digital bit is stored in a separate digital memory cell. In accordance with the present invention, an analog memory such as a charge transfer device (CTD), bubble memory, or magnetostrictive memory is used to store analog signals. Each analog signal is representative of a plurality of digital bits, thereby providing storage for a plurality of digital bits in each analog memory cell. Use of such an analog memory in combination with a digital system facilitates a hybrid memory, where digital information is stored in analog signal form.

Abstract: A method for the operation of a CID (Charge Injection Device) arrangement is disclosed. Electric analog signals are input into the CID arrangement by use of first and second capacitors connected to row and column lines. A signal voltage creates a signal charge in the first capacitor which is read into the second capacitor.

Abstract: CCD methods and devices for recording transient data signals, in which charge is transferred under the influence of transmission line fields at sampling sites disposed along a charge transfer channel.

Abstract: A serial-parallel-serial organized charge transfer memory is integrated on a semiconductor chip and includes a read-in chain consisting of first and second charge transfer elements alternately arranged behind one another, respectively controllable by way of clock pulse lines, and comprising memory and shift electrodes, and a field of parallel chains of charge transfer elements into which charges characterizing information are transferred either only from the first or only from the second charge transfer elements of the read-in chain, and a read-out chain constructed as the read-in chain and operated by way of clock pulse lines. The like electrodes of the charge transfer elements of the read-in and read-out chains, together with the appertaining control and clock pulse lines respectively consist of a continuous conduction band, at least in the area of the serial read-in and read-out chains of the chip.

Abstract: An improved read-only/read-write semiconductor memory of the type that includes a semiconductor substrate with dopant atoms of a first conductivity type, a pair of spaced-apart charge storage regions at the surface of the substrate, a bit line at the surface of the substrate spaced apart from the charge storage region, respective MOSFET transistor gate regions at the surface of the substrate between the bit line and the charge storage regions, and a conductor over the storage regions; the improvement comprising dopant atoms of a second conductivity type in one of the storage regions, and dopant atoms of the first conductivity type in the other of the storage regions having a greater doping concentration than is in the body of the substrate; and circuitry for applying a read-write mode voltage to the conductor to permit charge to be stored in both of the storage regions, and for applying a read-only mode voltage to the conductor to permit charge to be stored in the one storage region and simultaneously prevent

Abstract: This invention improves production yield and charge transfer speed and efficiency at the detector/register interface in a focal plane array and includes a novel meander channel CCD serial register in which charge packets generated in the array are stored. The electrode edge length across which charge is transferred at each entrance to the serial register is substantially increased in this invention in comparison with the prior art, resulting in a significant improvement in charge transfer efficiency and layout simplicity. Furthermore, this invention provides symmetrical surface potential distribution, and eliminates the gap instability in charge transfer.

Abstract: A charge coupled device is disclosed which includes a plurality of stages having increased charge storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. A charge transfer channel extends through the stage. An insulating layer of non-uniform thickness lies on the first surface. The insulating layer has at least two spaced apart relatively thick portions traversing the channel, and has relatively thin portions traversing the channel throughout the spaces between the spaced apart thick portions. Phase electrodes traverse the channel such that each phase electrode overlies one relatively thick portion and one adjacent relatively thin portion of the insulating layer. A shallow dopant layer of a second-type conductivity lies throughout the channel relatively near to the first surface.

Abstract: This serial to parallel to serial (SPS) charge coupled device (CCD) shift register memory has a serial output shift register with stage gate electrode structures that are interdigitated with the gate electrode structures of each last stage of a plurality of parallel shift registers to transfer interlaced data bits from the parallel shift registers to the serial output register in a sequential order. This is done without employing a fixed voltage midway between the highest clock voltage and reference potential in the parallel registers in what is commonly called a midway store to regulate the transfer of data to the interdigitated gate electrode structures.

Abstract: The present invention is directed to a read only memory, wherein the preferred embodiment provides an analog read only memory using charge coupled devices. Fixed but selectable charge packets are used to charge elements in a charge coupled device array; where selectable charging may be provided by selecting resistor values, selecting capacitor values, selectable masking of photo detectors, and other such methods. The accumulated fixed packets of charge are then shifted with a charge coupled device register to provide sequential analog signal outputs. Use of an analog read only memory permits hybrid signal processing such as for voice response. Use of a serial output simplifies the accessing and reduces accessing electronics by eliminating the more complex random access arrangements.

Abstract: A charge coupled device is disclosed which includes a plurality of stages having increased charge storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. An insulating layer of uniform thickness lies on the first surface. A charge transfer channel extends through each stage. Phase electrodes lie on the insulating layer transversely to the channel. The semiconductor substrate under each phase electrode is divided into a barrier region and an adjacent well region bounded by the channel. A shallow dopant layer of the first-type conductivity lies in each of the barrier regions relatively near to the first surface. A buried channel dopant layer of a second-type conductivity lies in the well regions and the barrier regions under and relatively near to the shallow first-type conductivity dopant layer.

Abstract: A charge coupled device memory is disclosed which includes a plurality of stages having increased charged storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. An insulating layer of uniform thickness lies on the first surface. A charge transfer channel extends through each stage. Phase electrodes lie on the insulating layer transversely to the channel. The semiconductor substrate under the phase electrodes is divided into barrier regions and adjacent well regions bounded by the channel. A dopant layer of a second-type conductivity lies in each of the well regions relatively near to the first surface. An enhanced first-type conductivity dopant layer lies in the well regions and the barrier regions relatively far from the surface having a doping which is greater than the doping of the first-type conductivity semiconductor substrate.

Abstract: An input bias circuit for a charge transfer device array in which the fat zero signal level is a function of device threshold voltage and other device parameters. The use of such a circuit eliminates the need to adjust or tune the reference or bias level from array to array. The circuit includes the addition of a diode connected field effect transistor and capacitor between the input device, the source of the first charge transfer device stage, and the input gating device such that the minimum discharge level is set, on the input node, a threshold voltage drop above the reference level. When device threshold voltages are higher the charge established on the input node is decreased to compensate for the decrease in charge transferred by the register stages. Matching of the sizes of the diode connected field effect transistor with the input device and the devices in each stage of the array insures accurate tracking with process variations.

Abstract: A sense amplifier for use with a charge coupled device in which capacitive coupled charge is employed with a flip-flop circuit to accelerate sense and readout. Operation of the amplifier is effected with two external clocks and two internally generated clocks.

Abstract: A random access memory device which is comprised of a matrix of individual MOS random access memory cells, the individual cells utilizing a sense region formed by a diffused layer of heavily doped silicon material underlying the storage and transfer regions, the storage region being formed at the surface of the device and containing a double implant for increasing the storage capacity of the cell, the transfer region being formed along the edge of a V-groove anisotropical etch which extends from the surface of the device adjacent the storage region and into the diffused sense region. In one embodiment first and second layers of polycrystalline silicon separated by an insulating layer and deposited at the surface of the cell act as the storage and transfer gates, respectively, the first layer overlying the storage region adjacent the V-groove and the second layer lying within the V-groove and partially overlapping the first layer.

Abstract: A monolithically integrated circuit for relatively slow readout of a two-dimensional image sensor and transfer of separate signal charge packets and noise charge packets from the image sensor to a pair of charge transfer devices has first and second intermediate memories for respectively storing the signal and noise charge packets which are connected to clock pulse voltages for successively transferring the packets to the charge transfer devices. An output stage connected to the charge transfer devices contains a difference circuit for subtracting the noise signal from the total signal to generate a readout representing only the signal generated by incident radiation on the sensor.

Abstract: Relatively noise-free information signals are recovered from a charge transfer device by demodulating sideband components of the output signal of the device at a selected harmonic of the pulse output frequency of the device. In a further refinement of the invention, the relative duty cycles between the clock signals employed to operate the device and the output signal from the device are chosen such that a minimum of power from the clock signals is present at the selected harmonic.

Abstract: A circulating shift register memory, particularly adaptable to charge coupled device technology, wherein a plurality of circulating shift registers are arranged to provide a matrix of data bits accessible at a common data front. Address counter circuitry cooperating with the register clocking circuits selects a particular bit location on the data front for each shift of the shift registers. Depending upon a mode signal and beginning address from a host system, the address counter circuitry provides successive accesses in predetermined patterns, for example along a row, column or diagonal of the bit matrix.

Abstract: A solid state device capable of providing long-term storage of analog signals which in a particular embodiment utilizes a plurality of MNOS storage elements. An input analog signal is applied to a plurality of temporary storage means each associated with an MNOS storage element for temporarily storing a charge proportional to the amplitude of the portion of the input analog signal applied thereto. Storage control means are used to transfer the temporarily stored charges to the long-term MNOS storage elements so that controlled amounts of carrier charges are stored in the nitride layers thereof, such controlled amounts being substantially linearly proportional to the temporarily stored charges associated therewith. In a particular embodiment the input analog signal may be supplied via a surface acoustic wave (SAW) device and coupled to the MNOS device directly or it may be coupled to a charge-coupled device (CCD) and then coupled to the MNOS device.

Abstract: A digital-to-analog conversion (DAC) circuit and trigger comparator combination is described for encoding and decoding charge packets in a common-well multi-level signal charge-coupled memory device (CCD). The DAC circuit, which may be of the weighted capacitor type, is used to generate a staircase waveform and to create the common-well under a first gate in the CCD. The trigger comparator adjacent to a second gate in the CCD is a detection circuit which stays in one binary state until an input charge signal is received, whereupon it switches state. In particular, the weighted capacitor DAC contains an extra offset bit which is used in the analog-to-digital or regeneration operation such that when the trigger comparator switches state, the digital input to the DAC at that time correctly represents the signal charge being converted. In one embodiment a circular serial-parallel-serial memory structure is employed as the multi-level CCD memory system.

Abstract: A charge coupled device multiplexed parallel channel storage array useful with a serial input register having a storage density unconstrained by the serial register and effective for storing analog information. The same serial register cell reads charge packets sequentially to successive parallel channels by means of a single multiplexer electrode overlying the entrances to the parallel channels in a staircase configuration to which the entrances themselves conform.

Abstract: This serial to parallel to serial (SPS) charge coupled device (CCD) shift register memory has a serial output shift register with gate electrode structures that are interdigitated with the gate electrode structures of each last stage of a plurality of parallel shift registers to transfer interlaced data bits from the parallel shift registers to the serial output register in a sequential order.

Abstract: A calibrated sensing system is provided in accordance with the teachings of this invention for sensing charge in a storage medium, such as a storage capacitor, coupled to an access or bit/sense line which compensates for most sources of variability in the storage medium and in the access line. In the system, the unknown charge stored in the storage medium is transferred to a first capacitor or potential well via the access line. A high charge state of the storage medium is written into the storage medium and known fractional packets of charge are prepared therefrom, transferred selectively to a second capacitor or potential well and compared with the unknown charge in the first potential to determine the relative level of the unknown charge that was stored in the storage medium. By selectively using two or more fractional packets of charge multilevel sensing is performed.

Abstract: A solid state device capable of providing long-term storage of analog signals which in a particular embodiment utilizes a plurality of MNOS storage elements. An input analog signal is applied to a plurality of temporary storage means each associated with an MNOS storage element for temporarily storing a charge proportional to the amplitude of the portion of the input analog signal applied thereto. Storage control means are used to transfer the temporarily stored charges to the long-term MNOS storage elements so that controlled amounts of carrier charges are stored in the nitride layers thereof, such controlled amounts being substantially linearly proportional to the temporarily stored charges associated therewith. In a particular embodiment the input analog signal may be supplied via a surface acoustic wave (SAW) device and coupled to the MNOS device directly or it may be coupled to a charge-coupled device (CCD) and thence coupled to the MNOS device.

Abstract: A solid state device combining the use of a surface-acoustic-wave (SAW) device and a charge-coupled device (CCD) which utilizes an interface means therebetween comprising a plurality of conductive fingers responsive to an acoustic wave on the SAW device. The conductive fingers are electrically connected at at least one end to the CCD substrate and a plurality of temporary storage means are used for temporarily storing a charge proportional to the voltage potential on the associated conductive finger. The temporary stored charges can be transferred to the storage wells of the CCD for storing a replica of the acoustic wave. The SAW-CCD combination is adapted for use as a buffer memory, an accumulating correlator, or as a matched filter device.

Abstract: An SPS CCD memory system is provided wherein a single tap, preferably a storage node, on an input serial or shift register is connected to the input of a plurality of parallel shift registers through a fan out circuit and the output of the plurality of parallel shift registers is connected to a single tap, preferably a storage node, on an output serial or shift register through a fan in circuit.

Abstract: Packets of charges representing an electrical signal are injected into a semiconductor substrate by injection means comprising a diode and two electrodes. The charge packets are transferred to an output diode with a well-defined time-delay by means of electrodes which are disposed on the substrate and to which periodic transfer potentials are applied. The output diode also receives samples of the signal to be stored and is connected to an inverter which serves to regenerate and transmit the signal to the injection means.

Abstract: An array of charge storage devices each including a pair of closely coupled conductor-insulator-semiconductor cells, one a row line connected cell and the other a column line connected cell, is provided on a common semiconductor substrate. Readout of the charges stored in a row of devices is accomplished by transferring the charge in each of the devices of the selected row of devices in one direction between the row line connected cell and the column line connected cells of a device in sequence and sensing the resultant current flow in the row line of the selected row of devices.

Abstract: A charge transfer memory has a read-in chain, and assigned parallel chain and a read-out chain, each consisting of charge transfer elements. An additional parallel chain of charge transfer elements stores bias charges which are fed into the read-in chain, after the transfer of information charges from the read-in chain into the parallel chain, before a renewed serial input of information charges into the read-in chain. The read-out chain has a circuit arrangement assigned thereto which fills the output chain with bias charges upon the serial read-out of charges which characterize the information. The read-out chain has assigned thereto a further parallel chain of charge transfer elements with which the bias charges are removed from the output chain before the renewed delivery of charges characterizing information from the parallel chain.

Abstract: Storage systems are provided with memory cells made of devices having different voltage thresholds for storing information permanently or semipermanently. The devices are arranged adjacent to each other and communicating with a diffusion region in a semiconductor substrate. Information is sensed by detecting the charge transferred from a selected cell to the diffusion region. In an embodiment of the invention, a P-type substrate has an N+ diffusion region formed therein with a plurality of adjacent and parallelly arranged word lines insulated from the substrate and disposed adjacent to the N+ diffusion region. A P+ region, preferably implanted into the substrate, is disposed under selected segments of the word lines to provide devices having a first or high threshold voltage magnitude. The remaining devices which are not associated with a P-30 region have a second or low threshold voltage magnitude.