Data Security Patents (Class 365/185.04)
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Publication number: 20150003155Abstract: A write-protection system and method for use with a gaming machine. The system having a non-volatile data storage device, an interface device and an electrically conductive connector. The storage device having electronic data storage and a write-protection controller providing a write-protected state and a write-permitting state, the electronic data storage being blocked from receiving electronic write commands in the write-protected state and being able to receive write commands in the write-permitting state. The interface device electrically connecting the data storage device to a power supply and control circuitry of the gaming machine. The interface device connected to the electronic data storage through the controller and the connector.Type: ApplicationFiled: July 1, 2014Publication date: January 1, 2015Inventors: Steven John Jaskowiak, Jeffrey W. Siegrist
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Patent number: 8908453Abstract: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided.Type: GrantFiled: October 16, 2013Date of Patent: December 9, 2014Assignee: Round Rock Research, LLCInventor: Thomas H. Kinsley
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Patent number: 8891302Abstract: Electronic equipment according to the present disclosure includes a writable non-volatile memory, a plurality of volatile memories, and a sequencer. The writable non-volatile memory stores an operation parameter group required to operate the electronic equipment. Respective addresses are assigned to the plurality of volatile memories. The plurality of volatile memories includes a specified volatile memory. The specified volatile memory stores a part of the operation parameters among the operation parameter group. The specified volatile memory is accessible by inputting an Enable signal. The sequencer can read and write the non-volatile memory when the Enable signal allows an operation parameter stored in the volatile memory to be written to the non-volatile memory.Type: GrantFiled: June 25, 2013Date of Patent: November 18, 2014Assignee: Nihon Dempa Kogyo Co., Ltd.Inventor: Tsukasa Kobata
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Patent number: 8885408Abstract: A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.Type: GrantFiled: May 14, 2012Date of Patent: November 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Noboru Shibata, Tomoharu Tanaka
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Patent number: 8848417Abstract: A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.Type: GrantFiled: September 7, 2012Date of Patent: September 30, 2014Assignee: STMicroelectronics (Crolles 2) SASInventor: Emmanuel Petitprez
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Patent number: 8848477Abstract: An electric physical unclonable function (PUF) (100) is provided comprising a semiconductor memory element (110) connectable to a PUF control means for reading content from the memory element and for deriving at least in part from said content a digital identifier, such as a secret key. Upon powering the memory element it settles into one of at least two different stable states. The particular stable state into which the memory element settles is dependent at least in part upon random physical characteristics of the memory element introduced during manufacture of the memory element. Settling of the memory element is further dependent upon a control input (112) of the memory element.Type: GrantFiled: September 28, 2011Date of Patent: September 30, 2014Assignee: Intrinsic ID B.V.Inventors: Geert Jan Schrijen, Petrus Wijnandus Simons, Erik Van Der Sluis, Pim Theo Tuyls
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Patent number: 8842482Abstract: Embodiments of a circuit and method for setting initial trim bits in an integrated circuit (IC) are described. The circuit includes a memory array including a plurality of trim bit cells to store and provide trim bits to trim registers in a main circuit of the IC following energizing of the IC. The memory array further includes replica bit circuitry to generate a number of replica bits. A logic circuit coupled to the memory array and the main circuit of the IC is configured to receive the replica bits, and to provide a signal to the IC that indicates when the trim bits are valid. In one embodiment, the circuit further includes redundancy check logic configured to receive a number of the trim bits from the memory array, compare the number of trim bits to a pre-determined or computed value, and to provide a BITS_OK signal to the logic circuit.Type: GrantFiled: June 29, 2012Date of Patent: September 23, 2014Assignee: Cypress Semiconductor CorporationInventors: David Kunst, Hans Van Antwerpen
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Patent number: 8811106Abstract: Disclosed is a non-volatile memory data protecting device and method. The non-volatile memory data protecting device that is used for protecting non-volatile memory data when a power is shut down in a system, may include a signal delay unit to delay a drop in voltage of an input/output line, a power shutdown sensor to sense power shutdown of a system, and a controller to control the signal delay unit in response to whether the system is shut down.Type: GrantFiled: April 22, 2013Date of Patent: August 19, 2014Assignee: SK Hynix Inc.Inventor: Youjip Won
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Publication number: 20140219021Abstract: A data storage device receives a write data command and data. The data is stored in a buffer of the data storage device. The data storage device issues a command complete status indication. After the command complete status indication is issued, the data are stored in a primary memory of the data storage device. The primary memory comprises a first type of non-volatile memory and the buffer comprises a second type of non-volatile memory that is different from the first type of non-volatile memory.Type: ApplicationFiled: February 7, 2013Publication date: August 7, 2014Applicant: SEAGATE TECHNOLOGY LLCInventors: Jon D. Trantham, Michael Joseph Steiner, Antoine Khoueir
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Publication number: 20140160844Abstract: A memory repairing method for a rewritable non-volatile memory module and a memory controller and a memory storage apparatus are provided. The method includes monitoring a wear degree of the rewritable non-volatile memory module; determining whether the wear degree of the rewritable non-volatile memory module is larger than a threshold; and heating the rewritable non-volatile memory module such that the temperature of the rewritable non-volatile memory module lies in between 100° C.˜600° C. if the wear degree of the rewritable non-volatile memory module is larger than the threshold. Accordingly, deteriorated memory cells in the rewritable non-volatile memory module can be repaired, thereby preventing data loss.Type: ApplicationFiled: February 26, 2013Publication date: June 12, 2014Applicant: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Yu-Cheng Hsu, Kuo-Yi Cheng, Chun-Yen Chang
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Patent number: 8751730Abstract: A serial interface flash memory apparatus and a writing method for a status register thereof are disclosed. The writing method for the status register mentioned above includes: receiving a write command with an updated data for the status register; writing the updated data to a volatile latch and set an update flag according to whether or not a write-protected data in the status register is updated by the write command; and writing the data from the volatile latch to the status register according to the update flag when a power down process of the serial interface flash memory apparatus is processed.Type: GrantFiled: July 27, 2012Date of Patent: June 10, 2014Assignee: Winbond Electronics Corp.Inventors: Yung-Chen Lin, Ya-Chun Chang
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Publication number: 20140146607Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a random number generation circuit configured to generate a random number, and a controller configured to control the memory cell array and the random number generation circuit. The random number generation circuit includes a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter, and a pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value.Type: ApplicationFiled: February 17, 2012Publication date: May 29, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yuji Nagai, Atsushi Inoue, Yoshikazu Takeyama
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Publication number: 20140133227Abstract: A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block.Type: ApplicationFiled: October 3, 2013Publication date: May 15, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: HO-KIL LEE, SUNG-JOON KIME, JIN-YUB LEE, SUNG-KYU JO, SEUNG-JAE LEE, JONG-HOON LEE
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Patent number: 8699269Abstract: A state set module arranges states of a memory cell in a first and a second sequence in a first and a second state set, respectively. The memory cell stores first and second bits when programmed to a state. When the states in the first and second state sets are accessed respectively in the first and the second sequence, the first and second bits of the states in the first and second state sets exhibit different number of logical transitions. A write module receives first and second sets of bits to be written as the first and second bits in a plurality of memory cells, and selects states from the first and second state sets in an alternating pattern to write the first and second sets of bits as the first and second bits in the plurality of memory cells.Type: GrantFiled: July 26, 2013Date of Patent: April 15, 2014Assignee: Marvell International Ltd.Inventor: Xueshi Yang
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Patent number: 8634240Abstract: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC and estimated to represent a worst error rate among the copy it is sampling. One embodiment has the sample taken from one bit of each multi-bit memory cell of a group.Type: GrantFiled: September 1, 2010Date of Patent: January 21, 2014Assignee: Sandisk Technologies, Inc.Inventors: Lee M. Gavens, Jian Chen
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Patent number: 8582356Abstract: A common standard may be used for both dynamic random access memories and non volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to.Type: GrantFiled: September 13, 2012Date of Patent: November 12, 2013Assignee: Micron Technology, Inc.Inventor: Mostafa Naguib Abdulla
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Patent number: 8577031Abstract: An integrated circuit (1) is provided with function modules (2) which comprise a central processing unit (4) for treating data and executing a program and a cache memory (5). Until now, it was complicated and costly to ensure the manipulation security of the modules. The function modules (2) comprise an encoding unit (6) for data encoding and decoding.Type: GrantFiled: March 10, 2005Date of Patent: November 5, 2013Assignee: Continental Automotive GmbHInventors: Karl Asperger, Jochen Kiemes, Roland Lange, Andreas Lindinger, Gerhard Rombach
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Patent number: 8570823Abstract: In an embodiment related to a sense amplifier, the sense amplifier includes a pair of transistors (e.g., transistors P2 and P3) that, when appropriate, enables data on input lines DL and DLB to be preset directly to the internal nodes (e.g., nodes S and SB) of the sense amplifier, from which the data can be read out. In addition, this pair of transistors P2 and P3 also allows the internal nodes S and SB to share the pre-charge mechanisms of lines DL and DLB.Type: GrantFiled: February 18, 2010Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Huei Chen, Hsien-Yu Pan, Shao-Yu Chou
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Patent number: 8566931Abstract: A method and a circuit for protecting data contained in an electronic circuit against a disturbance of its operation, in which a detection of a disturbance conditions the incrementing or the decrementing of a counter over at least one bit, the counter being automatically reset at the end of a time period independent from the fact that the circuit is or not powered.Type: GrantFiled: January 4, 2008Date of Patent: October 22, 2013Assignee: Proton World International N.V.Inventors: Jean-Louis Modave, Thierry Huque
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Patent number: 8565035Abstract: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided.Type: GrantFiled: September 19, 2011Date of Patent: October 22, 2013Assignee: Round Rock Research, LLCInventor: Tom Kinsley
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Patent number: 8498154Abstract: A memory system includes a state set module that provides a first state set having a plurality of states, each being assigned to represent a particular data sequence, and a second state set having a same number of states as the first state set, wherein an assignment of one or more particular data sequences among the states of the second state set is different relative to that set forth in the first state set. The memory system further includes a write module that writes first data to a first multi-level memory cell of the memory system based on the first state set, the first multi-level cell being located on a wordline of the memory system, and that writes second data to a second multi-level memory cell of the memory system based on the second state set, the second multi-level cell being located on the wordline of the memory system.Type: GrantFiled: May 14, 2012Date of Patent: July 30, 2013Assignee: Marvell International Ltd.Inventor: Xueshi Yang
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Patent number: 8467249Abstract: A method, system and computer-readable medium are provided for reading information from a memory unit. A request may be received to read information from a set of memory cells in the memory unit. At least one read threshold in an initial set of read thresholds may be perturbed to generate a perturbed set of read thresholds. The set of memory cells may be read using the perturbed set of read thresholds to provide a read result. The performance of said reading may be evaluated using the perturbed set of read thresholds. The at least one read threshold may be iteratively perturbed for each sequential read operation that the read performance is evaluated to be sub-optimal.Type: GrantFiled: June 30, 2011Date of Patent: June 18, 2013Assignee: Densbits Technologies Ltd.Inventors: Michael Katz, Hanan Weingarten
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Patent number: 8446795Abstract: Disclosed is a non-volatile memory data protecting device and method. The non-volatile memory data protecting device (200) that is used for protecting non-volatile memory data when a power is shut down in a system, may include a signal delay unit (230) to delay a drop in voltage of an input/output line, a power shutdown sensor (210) to sense power shutdown of a system, and a controller (220) to control the signal delay unit in response to whether the system is shut down.Type: GrantFiled: July 31, 2009Date of Patent: May 21, 2013Assignee: IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)Inventor: Youjip Won
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Patent number: 8422293Abstract: The self-powered detection device comprises a non-volatile memory cell and a sensor activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester transforming energy from the physical or chemical action orphenomenon into an electrical stimulus pulse, the memory cell arranged for storing, by using electrical power of the electrical stimulus pulse, at least a bit of information relative to detection by the sensor of at least a first physical or chemical action or phenomenon. The non-volatile memory cell comprises a FET transistor having a control gate, a first diffusion defining a first input and a second diffusion defining a second input. This FET transistor is set to its written logical state from its initial logical state when, in a detection mode, it receives on a set terminal a voltage stimulus signal resulting from the first physical or chemical action or phenomenon.Type: GrantFiled: November 12, 2010Date of Patent: April 16, 2013Assignee: EM Microelectronic-Marin SAInventors: David A. Kamp, Filippo Marinelli, Thierry Roz
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Patent number: 8411505Abstract: The self-powered detection device comprises a Non-Volatile Memory (NVM) unit (52) formed at least by a NVM cell and a sensor which is activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester that transforms energy from said physical or chemical action or phenomenon into an electrical stimulus pulse, said NVM unit being arranged for storing in said NVM cell, by using the electrical power of said electrical stimulus pulse, a bit of information relative to the detection by said sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal (SET) and a base terminal (SET *) of said NVM unit with at least a given set voltage.Type: GrantFiled: November 12, 2010Date of Patent: April 2, 2013Assignee: EM Microelectronic-Marin SAInventor: David A. Kamp
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Patent number: 8411504Abstract: A method and a circuit for controlling the access to at least one resource of an electronic circuit, in which a test of the value of a counter over at least one bit conditions the access to the resource, the counter being automatically reset after a time period independent from whether the circuit is powered or not.Type: GrantFiled: January 4, 2008Date of Patent: April 2, 2013Assignee: Proton World International N.V.Inventors: Jean-Louis Modave, Thierry Huque
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Patent number: 8384525Abstract: The present invention provides a method for contactless programming of a memory element of an electronic device having a wireless short range communications interface. The method comprises performing an interrogation for detecting the presence of said wireless short range communications interface, receiving, responsive to said interrogation, data from said wireless interface, said data indicating a hardware configuration of said electronic device, selecting programming data for programming said memory element based on said hardware configuration, and transmitting said selected programming data to be received by said wireless short range communications interface.Type: GrantFiled: May 15, 2006Date of Patent: February 26, 2013Assignee: Nokia CorporationInventors: Risto Ronkka, Jukka Reunamaki
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Patent number: 8346306Abstract: A suspend control apparatus, disposed in an electronic device having a SIM card, includes a control unit that switches the state of the SIM card between a suspended state and a resumed state. The control unit determines, based on the state of SIM card access for data communication and the state of the SIM card when the data communication occurs, whether to give priority to SIM card access or switching to the suspended state, and sets the state of the SIM card accordingly.Type: GrantFiled: June 10, 2011Date of Patent: January 1, 2013Assignee: Fujitsu LimitedInventors: Masanobu Kawakishi, Mikimasa Yamagishi, Takao Ohta, Shinichi Matsuya, Kiyotaka Sawae, Shinji Yamauchi, Masahiro Harima, Yoichi Kikuchi, Keigo Kuramoto
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Patent number: 8312238Abstract: A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information and a reset apparatus configured to invalidate the memory protection information stored in the protection information storage according to a reset request signal output from the CPU.Type: GrantFiled: April 18, 2007Date of Patent: November 13, 2012Assignee: RENESAS Electronics CorporationInventors: Rika Ono, Hitoshi Suzuki
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Patent number: 8289767Abstract: A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to.Type: GrantFiled: October 19, 2011Date of Patent: October 16, 2012Assignee: Micron Technology, Inc.Inventor: Mostafa Naguib Abdulla
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Patent number: 8264880Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described device includes a non-volatile memory structure including a first data area, and a second data area that stores information. The information can include a first value corresponding to the first data area, the first value being set responsive to a last programming cycle on the first data area, and a second value indicating a total number of programming or erasing operations on the first data area.Type: GrantFiled: September 29, 2011Date of Patent: September 11, 2012Assignee: Marvell International Ltd.Inventor: Xueshi Yang
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Patent number: 8259500Abstract: A non-volatile memory (NVM) circuit is provided, that includes at least a first and second NVM sub-array. The first sub-array is built from first memory cells. The second NVM sub-array is built from second memory cells that are constructed differently from the first memory cells. The NVM sub-arrays share a support circuit. In some embodiments the sub-arrays can be constructed, so that they exhibit different characteristics tailored to their intended use. For example one sub-array might be tailored for data retention, while the next sub-array for programming endurance, still another for write disturb immunity.Type: GrantFiled: February 24, 2011Date of Patent: September 4, 2012Assignee: Synopsys, Inc.Inventors: Yanjun Ma, Steven I. Mozsgai
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Patent number: 8248850Abstract: An error detection and data recovery operation for a non-volatile memory system. Even after a programming operation for a set of storage elements is successfully completed, the data of some storage elements may be corrupted. For example, erased state storage element may be disturbed by programming of other storage elements. To allow recovery of data in such situations, associated data latches can be configured to allow the erased state storage elements to be distinguished from other data states once programming is completed. Furthermore, a single read operation can be performed after programming is completed. Logical operations are performed using results from the read operation, and values in the data latches, to identify erased state storage elements which have strayed to another data state. If the number of errors exceeds a threshold, a full recovery operation is initiated in which read operations are performed for the remaining states.Type: GrantFiled: January 28, 2010Date of Patent: August 21, 2012Assignee: SanDisk Technologies Inc.Inventors: Deepanshu Dutta, Jeffrey W. Lutze, Yan Li
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Patent number: 8243514Abstract: Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.Type: GrantFiled: April 7, 2011Date of Patent: August 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Gu Kang, Seungjae Lee, Donghyuk Chae
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Patent number: 8189389Abstract: A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.Type: GrantFiled: January 24, 2011Date of Patent: May 29, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Noboru Shibata, Tomoharu Tanaka
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Patent number: 8189384Abstract: A device includes a one-time-programmable memory including multiple random accessible input/output pins. Each random accessible I/O pin corresponds to a unique memory address in the one-time-programmable memory. The device also includes a multiplexing circuit with multiple inputs. Each of the multiple inputs is coupled to one of the multiple random accessible I/O pins. An output of the multiplexing circuit has a bit width that is less than the number of the multiple random accessible I/O pins.Type: GrantFiled: February 11, 2011Date of Patent: May 29, 2012Assignee: Sigmatel, Inc.Inventor: Sebastian Ahmed
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Patent number: 8179719Abstract: A memory system includes a state set module that provides a first state set having a plurality of states, each being assigned to represent a particular data sequence, and a second state set having a same number of states as the first state set, wherein an assignment of one or more particular data sequences among the states of the second state set is different relative to that set forth in the first state set. The memory system further includes a write module that writes first data to a first multi-level memory cell of the memory system based on the first state set, the first multi-level cell being located on a wordline of the memory system, and that writes second data to a second multi-level memory cell of the memory system based on the second state set, the second multi-level cell being located on the wordline of the memory system.Type: GrantFiled: March 10, 2009Date of Patent: May 15, 2012Assignee: Marvell International Ltd.Inventor: Xueshi Yang
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Patent number: 8156280Abstract: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.Type: GrantFiled: May 26, 2011Date of Patent: April 10, 2012Assignee: Renesas Electronics CorporationInventor: Hitoshi Kurosawa
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Patent number: 8117378Abstract: An input voltage range may be established between different voltage levels used for different programming functions of an integrated circuit device, thus implementing a protection zone (“safe zone”) of non-operation to facilitate prevention of an unintended irreversible programming operation, e.g., permanent write protection.Type: GrantFiled: October 29, 2008Date of Patent: February 14, 2012Assignee: Microchip Technology IncorporatedInventors: David Francis Mietus, Bruce Edward Beauchamp, Samuel Alexander, Ezana H. Aberra
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Patent number: 8111551Abstract: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.Type: GrantFiled: May 2, 2011Date of Patent: February 7, 2012Assignees: Kabushiki Kaisha Toshiba, Sandisk CorporationInventors: Tomoharu Tanaka, Koichi Kawai, Khandker N Quader
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Patent number: 8089806Abstract: A method for controlling a semiconductor storage device including memory cells each configured to hold data of 2 bits or more, the method includes starting first signal processing, and inputting lower bits into the semiconductor storage device in a ready state, writing the lower bits to the memory cells, changing the semiconductor storage device from the ready state into a busy state, changing the semiconductor storage device from the busy state into the ready state, and finishing the first signal processing, starting second signal processing, and inputting upper bits into the semiconductor storage device in the ready state, and writing the upper bits to the memory cells. A period for the writing the upper bits is longer than a period for the writing the lower bits. A period for performing the second signal processing is longer than a period for performing the first signal processing.Type: GrantFiled: March 17, 2009Date of Patent: January 3, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Tomoji Takada
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Patent number: 8064250Abstract: A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to.Type: GrantFiled: December 16, 2008Date of Patent: November 22, 2011Assignee: Micron Technology, Inc.Inventor: Mostafa Naguib Abdulla
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Patent number: 8023344Abstract: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided.Type: GrantFiled: June 30, 2010Date of Patent: September 20, 2011Assignee: Micron Technology, Inc.Inventor: Tom Kinsley
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Publication number: 20110205794Abstract: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.Type: ApplicationFiled: May 2, 2011Publication date: August 25, 2011Inventors: Tomoharu Tanaka, Koichi Kawai, Khandker N. Quader
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Patent number: 8004894Abstract: In the semiconductor integrated circuit incorporating non-volatile memory that is not electrically rewritable, updating stored data and reusing the non-volatile memory are made possible. The data stored in the non-volatile memory can be updated and the non-volatile memory can be reused by dividing the non-volatile memory into a plurality of blocks and replacing a used block with an unused block. When data “1” is set in the first flag of a certain block, a block selection circuit judges that data is already written in the block and rewriting new data into the block is not possible. To update the stored data, the updated data is written into a block that is selected by the block selection circuit out of the rest of the blocks. At that time, the first flag of the block is set to data “1”. Stored data is updated one after another as described above. When data of final update is written into a certain block, the second flag of the block is set to data “1”.Type: GrantFiled: September 25, 2008Date of Patent: August 23, 2011Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventor: Hideo Kondo
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Patent number: 7982488Abstract: A semiconductor chip having a subcircuit formed in a substrate; and a phase-change memory cell located on the subcircuit, and configured to directly detect an attack on the subcircuit, or to form a shield to prevent physical access to the subcircuit.Type: GrantFiled: May 29, 2009Date of Patent: July 19, 2011Assignee: Infineon Technologies AGInventors: Thomas Nirschl, Berndt Gammel, Stefan Rueping, Ronald Kakoschke, Gerd Dirscherl, Philip Schlazer
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Patent number: 7983096Abstract: A semiconductor device includes a nonvolatile memory configured to store write data in a write-enabled state, a check circuit configured to enable the write data as data for comparison in response to an enabled-status indicating signal indicative of the write-enabled state and to output a result of comparison obtained by comparing data read from the nonvolatile memory with the enabled data for comparison, and a path configured to output the result of comparison output from the check circuit to outside the semiconductor device, wherein no path to output the data read from the nonvolatile memory to outside the semiconductor device is in existence.Type: GrantFiled: February 18, 2011Date of Patent: July 19, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Kenichiro Kuroki, Andreas Bandt
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Patent number: 7965556Abstract: A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.Type: GrantFiled: May 27, 2010Date of Patent: June 21, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Norihiro Fujita, Hiroyuki Nagashima, Hiroshi Nakamura
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Patent number: 7961530Abstract: A semiconductor device includes a nonvolatile memory configured to store write data in a write-enabled state, a check circuit configured to enable the write data as data for comparison in response to an enabled-status indicating signal indicative of the write-enabled state and to output a result of comparison obtained by comparing data read from the nonvolatile memory with the enabled data for comparison, and a path configured to output the result of comparison output from the check circuit to outside the semiconductor device, wherein no path to output the data read from the nonvolatile memory to outside the semiconductor device is in existence.Type: GrantFiled: April 16, 2009Date of Patent: June 14, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Kenichiro Kuroki, Andreas Bandt
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Publication number: 20110128785Abstract: An apparatus for securely protecting data in a flash memory upon power off is disclosed. In the apparatus, a power detector monitors a voltage output from a power supply unit, and outputs a power fail signal when the voltage drops by a predetermined reference voltage or more. A Programmable Logic Device (PLD) outputs a Write Protect (WP) signal for performing write protection on the flash memory upon receiving the power fail signal from the power detector. A WP controller outputs the WP signal output from the PLD to the flash memory, according to a Ready/Busy (R/B) state of the flash memory.Type: ApplicationFiled: November 26, 2010Publication date: June 2, 2011Applicant: SAMSUNG ELECTRONICS CO. LTD.Inventor: Hee-Yun SEO