Abstract: The invention concerns a device for read-protection of at least a zone of a non-volatile storage (10), characterised in that it comprises: an address decoder (40) for supplying on one of the output terminals an addressing signal (NSWHADOW1SEL, NSWHADOWnSEL) when the address corresponds to one of the read-protected zones of the storage (10); a state storage (Mn1,Mn) for each read-protected zone for supplying a state signal (PMPR1, PMPRn) indicating whether the zone is read-protected or not; a programme instruction decoder (DIP) for supplying a programme signal (OP) indicating whether the current addressing operation corresponds or not to a programme instruction; and a logic circuit (42), whereto are applied the addressing signal (NSWHADOW1SEL, NSWHADOWnSEL), the state signal (PMPR1, PMPRn) and the programme signal (OP), for supplying an instruction signal (R10) for reading the read-protected zone when the programme signal (OP) indicates that the current addressing operation concerns a programme instruction.

Abstract: A semiconductor memory in which the protection state of data in a nonvolatile memory can be changed quickly and which provides sufficient security. A volatile protection state specification section controls the protection state of data in the nonvolatile memory. A nonvolatile initial state store section determines the initial state of the protection state specification section.

Abstract: An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.

Abstract: A mobile telephone (52) comprises a flash memory (3) having a sector data structure. A flash memory (3) has a sector data structure and stores user data (UD) and a firmware (FW) in a sector unit. A user data buffer (4A) and a firmware buffer (4B) are random accessible memories. The buffers (4A) and (4B) store the user data (UD) and firmware (FW) transferred from the memory (3) together with recognition numbers thereof, respectively. As a result of retrieval in the buffer (4B) which is carried out by a CPU (1), when the firmware (FW) required for the execution of an operation input by a user is not present in the buffer (4B), the CPU (1) controls a sequencer (2) to transfer the necessary firmware (FW) from the memory (3) to the buffer (4B). The CPU (1) executes the operational contents by utilizing the firmware (FW) in the buffer (4B). The CPU (1) also utilizes the user data (UD) in the same manner as the firmware (FW).

Abstract: The invention relates to an electronic assembly having a non-volatile memory device with a controllable write protection feature and a switching configuration for generating a write protection signal from potentials at the supply terminals of the electronic assembly.

Abstract: A coding method of a multi-level cell, applied to a programming operation of a multi-level memory cell. The multi-level memory cell can store n bits and has 2n levels with respect to 2n codes. Each code is constructed with n bits. In the coding method, a code to be stored is provided. According to a relationship between the code and level, the multi-level memory cell has a specified level for corresponding code to be stored. The relationship is a correspondence between the 2n codes and the 2n levels. Two codes corresponding to any neighboring two levels has only a one-bit difference.

Abstract: The invention is a method and system in which an authentication chip having secret information stored within it, including secret data stored in multi-level flash memory, is protected from unauthorised modification of values stored in the flash memory. The secret information is stored using an internal command and can only be accessed by one or more further commands. Secret data in the information is stored in intermediate states of the multi-level flash memory between the minimum and maximum voltage level states. A validity check is performed on secret data items before allowing them to be read out by a command accessing them. The validity check involves calculation of a checksum and comparison of the result with a checksum stored using the internal command as part of the secret information.

Abstract: The present invention relates to a nonvolatile memory device including a write protected region, comprising a program command processor, a write protected region setting unit and a write controller. The program command processor outputs a program command signal by decoding an external signal. The write protected region setting unit stores a region address corresponding to an inputted address when the program command signal is activated, and outputs a write protect signal when the program command signal is inactivated. The write controller controls a cell corresponding to the region address not to perform a write mode when the write protect signal is activated.

Abstract: A memory cell configuration has a nonvolatile memory that can be latched by a latching element. The nonvolatile memory is latched by activating a copy of the latching memory cell, which is coupled to the latching memory cell, and can be activated in a manner dependent on the operating state using an activation element. This makes it possible to identify and avoid incorrect programming, in particular in the case of calibratable sensors.

Abstract: In protecting Flash memory data, a flexible system and method provides for different levels of protection. It offers the ability to dynamically lock a sector of memory using a dynamic protection bit in volatile memory. It offers persistent locking of a sector using a non-volatile bit in memory and locking this status using a lock bit in volatile memory. It offers yet further protection by including a password mode which requires a password to clear the lock bit. The password is located in an unreadable, one time programmable area of the memory. The memory also includes areas, whose protection state is controlled by an input signal, for storing boot code in a protected manner.

Abstract: The present invention provides a non-volatile semiconductor memory device that can protect each block without increasing a memory element area, and make an access to the memory cells in hidden blocks in a hidden mode in which the hidden blocks are accessed. This electrically rewritable non-volatile semiconductor memory device includes K non-volatile memory elements that store protection information, a non-volatile memory element that stores a protection status, and a storage area that is logically divided into 2K or less blocks. In accordance with information stored in the K non-volatile memory elements and the non-volatile memory element that stored the protection status, a write operation is inhibited in the successive bocks in storage area.

Abstract: A data communication device which includes a flash memory, a primary buffer region in the flash memory which has time-sequential information stored therein from earliest to, an auxiliary buffer region in the flash memory which receives and stores primary-buffer storage information to be stored in the primary buffer region during a first condition of the data communication device when the information stored in the primary buffer region is not allowed to be updated, and an information-storage control unit which, when the primary-buffer storage information is stored in the auxiliary buffer region and during a second condition of the data communication device when updating of the information in the primary buffer region is allowed, reads information having a size not more than the storage capacity of the primary buffer region from the information stored in said primary buffer region and the auxiliary buffer region, and which re-stores the information that has been read in the primary buffer region.

Abstract: In order to preclude unauthorized access to a memory, for example after testing, two EEPROM cells are programmed and their outputs are subjected to a logic operation, the result being stored in a memory element and being evaluated. The cells are arranged in such a manner that they are programmed together in anti-parallel. A well-defined initial condition before a test is established by changing the control gate voltage, which causes both cells to be set to an initial state with similar output signals. The initial state is stored in the storage element and is evaluated. It is not until the initial condition has been established that the EEPROM cells are programmed and the correct programming is tested. Locking is effected by means of a single programming pulse and is irreversible.

Abstract: A nonvolatile semiconductor memory device includes a plurality of banks including respective memory cell arrays independent of each other, a password storage area that is associated with one of the banks, a bank decoder which generates a bank selection signal by decoding a bank address, a first bank selection circuit which outputs a write instruction or a read instruction to the one of the banks, a plurality of second bank selection circuits which outputs a write instruction or a read instruction to the respective banks except for the one of the banks, and a command-decode-&-bank-control circuit which controls the first and second bank selection circuits such that receipt of a first command causes one of the first and second bank selection circuits selected by the bank selection signal to output a write instruction or a read instruction, and such that receipt of a second command causes the first bank selection circuit to output a write instruction independently of the bank selection signal, and causes one

Abstract: A memory system includes manufacturer identifiers, such as serial numbers and part numbers, stored in locations of memory that are unalterable by end users. A customer identification location of the memory allows the user to program its own identifier and includes a lock-in code that prevents subsequent alteration of the customer identification location. A recall procedure at power on verifies the content of the locked code for allowing alteration of the memory.

Abstract: A rewrite disable control method for a non-volatile semiconductor storage device is disclosed for relying on a majority decision to determine whether a rewrite is disabled or enabled. A write disable control signal generating circuit reads three write disable flags of the same contents stored in security flag storage areas of three memory blocks, respectively, and makes a majority decision to determine a disable/enable state to establish the logic of a write disable control signal. Even if a power supply is instantaneously interrupted during an erasure of a certain block to cause a change in the security flag associated with one memory block, the security flags stored in the two remaining memory blocks maintain the original values, thereby making it possible to effectively prevent a trouble in which an unintended disable setting is validated.

Abstract: A configuration and a method for increasing the retention time and the storage security in a ferroelectric or ferromagnetic semiconductor memory utilize the imprint effect for increasing the remanent polarization or remanent magnetization of a material having a hysteresis property. The remanent polarization or magnetization is increased by writing a memory content a number of times to the same memory cells.

Abstract: A semiconductor device comprises a nonvolatile memory (A) for storing information on a frequency of operation; a volatile memory (B) in which the information on the frequency of operation is rewritten; and a control device for transferring the information on the frequency of operation stored in the memory (A) to the memory (B), rewriting the transferred information in the memory (B), and returning the rewritten information to the memory (A).

Abstract: A method for producing a non-volatile semiconductor memory cell with a separate tunnel window cell includes the step of forming a tunnel zone in a late implantation step by performing a tunnel implantation with the aid of a tunnel window cell as a mask. The resulting memory cell has a small area requirement and a high number of program/clear cycles.

Abstract: The invention is a method and system in which an authentication chip having secret information stored within it, including secret data stored in multi-level flash memory, is protected from unauthorized modification of values stored in the flash memory. The secret information is stored using an internal command and can only be accessed by one or more further commands. Secret data in the information is stored in intermediate states of the multilevel flash memory between the minimum and maximum voltage level states. A validity check is performed on secret data items before allowing them to be read out by a command accessing them. The validity check involves calculation of a checksum and comparison of the result with a checksum stored using the internal command as part of the secret information.

Abstract: A circuit (100) for protecting sensitive data stored in a storage area (108) includes a one time programmable device such as a fuse element (104) coupled to the input data path (102), and a one time programmable device such as fuse element (112) coupled to the output data path (118). Once sensitive data is loaded into the storage area (108), either one of, or both of the fuses (104, 112) can be activated (blown) in order to prevent access to the data stored in storage area (108). Optionally, a fuse element (130) can also be added to the internal circuit data line (120) that would prevent both internal and external access to the stored data.

Abstract: A program data latch circuit supplies one of a write bit line potential and a write prohibiting potential corresponding to multilevel data to be written, to a bit line in accordance with a level of a write control signal in a write operation. On the other hand, a program sense latch circuit compares a threshold value of a memory cell transistor sensed through the bit line with a reference potential, changes the level of the write control signal if the threshold value becomes a value corresponding to the multilevel data and instructs output of the write prohibiting potential in a verification operation.

Abstract: A memory cell configuration has a nonvolatile memory that can be latched by a latching element. The nonvolatile memory is latched by activating a copy of the latching memory cell, which is coupled to the latching memory cell, and can be activated in a manner dependent on the operating state using an activation element. This makes it possible to identify and avoid incorrect programming, in particular in the case of calibratable sensors.

Abstract: A memory cell array has a first and a second storage area. The first storage area has a plurality of memory elements selected by an address signal. The second storage area has a plurality of memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Abstract: A semiconductor memory device is provided which includes a rewrite-inhibited region for individual certification. Non-volatile memory elements constituting a memory cell array are used instead of a conventionally used fuse element to form the rewrite-inhibited region for individual certification. A voltage at high level is applied to a pad formed on a chip with a probe before the chip is sealed in a package to set the non-volatile memory elements in the rewrite-inhibited region to a writable state. After data for individual certification is written thereto, the chip is sealed in a package to disable electrical connection from outside to the pad set to a voltage at low level with a pull-down resistor.

Abstract: The invention relates to a method and an arrangement for controlling access to EEPROMs' and to a corresponding computer software product and a corresponding computer-readable storage medium, which can in particular be used to prevent the unauthorized manipulation of EEPROMs. Specifically, it is possible by using the invention to stop the unauthorized use of totally erased EEPROMs on smart-card controllers.

Abstract: The present invention provides a non-volatile semiconductor memory device that can protect each block without increasing a memory element area, and make an access to the memory cells in hidden blocks in a hidden mode in which the hidden blocks are accessed. This electrically rewritable non-volatile semiconductor memory device includes K non-volatile memory elements that store protection information, a non-volatile memory element that stores a protection status, and a storage area that is logically divided into 2K or less blocks. In accordance with information stored in the K non-volatile memory elements and the non-volatile memory element that stored the protection status, a write operation is inhibited in the successive bocks in storage area.

Abstract: A semiconductor storage device that determines the cause of an error at the time of the error correction of data read out from a non-volatile semiconductor memory, on the basis of a previously recorded error correction count, and selects a data refresh processing or a substitute processing to perform. When the error is detected, the corrected data is rewritten back for preventing reoccurrence of error due to accidental cause. If it is determined that the reoccurrence frequency of the error is high and the error is due to degradation of the storage medium, based on the error correction count, the substitute processing is performed.

Abstract: An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations.

Abstract: A write-protected memory device has two write modes. Such memory device has many memory cells organized into pages. A normal write mode checks a one-bit flag collocated with every memory cell to see if writes are allowed. If the flag indicates a write operation to that memory cell is allowed, the flag is toggled and the cell is written. If the flag has previously been toggled, the write operation is prevented. A special write mode allows write operations to memory cells regardless of the state of the one-bit flag. The special write mode can be discerned in hardware by the loading of a register with a reprogrammable password, or the splitting of a normal single write-enable pin into two independent pins, e.g., normal write and special write.

Abstract: The present invention provides a non-volatile semiconductor memory device that can protect each block without increasing a memory element area, and make an access to the memory cells in hidden blocks in a hidden mode in which the hidden blocks are accessed. This electrically rewritable non-volatile semiconductor memory device includes K non-volatile memory elements that store protection information, a non-volatile memory element that stores a protection status, and a storage area that is logically divided into 2K or less blocks. In accordance with information stored in the K non-volatile memory elements and the non-volatile memory element that stored the protection status, a write operation is inhibited in the successive bocks in storage area.

Abstract: In order to preclude unauthorized access to a memory, for example after testing, two EEPROM cells are programmed and their outputs are subjected to a logic operation, the result being stored in a memory element and being evaluated. The cells are arranged in such a manner that they are programmed together in anti-parallel. A well-defined initial condition before a test is established by changing the control gate voltage, which causes both cells to be set to an initial state with similar output signals. The initial state is stored in the storage element and is evaluated. It is not until the initial condition has been established that the EEPROM cells are programmed and the correct programming is tested.

Abstract: According to the present invention, access to a password area in a nonvolatile memory cannot be granted by simple supply of an address in a normal order. According to one preferable mode, for instance, a trap address is set in the password area so that reading information from the password area is permitted only when the password area is accessed without accessing the trap address, whereas when the password area is accessed the trap address, whereas when the password area is access through the trap address, information reading is inhibited, or meaningless data is output or the information in the password area is destroyed. This invention can make it harder to gain access to a password area which is used to protect against illegitimate copying and can provide a nonvolatile memory having a stronger copy protection capability.

Abstract: A semiconductor device includes: a memory having a memory space for recording data, the memory space including addresses; at least one first storage section for storing at least a portion of an address at which access to the memory space is requested and/or data which is requested to be written to the memory space; and an operation restriction circuit for at least partially restricting operations to be performed on the memory. The operation restriction circuit controls restriction on the operations to be performed on the memory based on at least a portion of the data and/or the address stored in the at least one first storage section.

Abstract: A method and circuit are disclosed for providing sector protection to sectors of nonvolatile memory cells in a nonvolatile memory device. The circuit includes maintaining sector protection information in the core of memory cells in the nonvolatile memory device. In this way, the circuitry and/or algorithms utilized for reading and modifying memory cells in the memory cell core that maintain the sector protection information is the same utilized for reading and modifying the other memory cells in the core.

Abstract: In the data writing sequence, judgement of writing is divided into two stages of judgement 1 and judgement 2. In the judgement 1, it is determined whether the data writing has been completed for at least one of a plurality of memory cells, and in the judgement 2, it is determined whether the data writing has been completed for all the memory cells. Changing the writing conditions for the judgements 1 and 2 enables judgement of the data writing in an early stage.

Abstract: In the data writing sequence, judgement of writing is divided into two stages of judgement 1 and judgement 2. In the judgement 1, it is determined whether the data writing has been completed for at least one of a plurality of memory cells, and in the judgement 2, it is determined whether the data writing has been completed for all the memory cells. Changing the writing conditions for the judgements 1 and 2 enables judgement of the data writing in an early stage.

Abstract: There is provided an electronic apparatus that can recover easily even when failing to update version up of a program and can be started without resort to special operation even when the program changes to change the storage format of setting information. The apparatus has a central processing unit for controlling the whole of the apparatus, a writable and nonvolatile memory for storing programs and setting information and a random access memory uses as a work area. The nonvolatile memory has at least three program areas.

Abstract: A non-volatile semiconductor memory device for allowing a data writing operation to, a data reading operation from, and a data erasing operation from a plurality of non-volatile memory cells. The non-volatile semiconductor memory device includes a data comparison section for outputting a first comparison result obtained by comparing data read from each of the plurality of memory cells and data read using a reference element for reading, a second comparison result obtained by comparing data read from each of the plurality of memory cells and data read from a reference element for writing, and a third comparison result obtained by comparing data read from each of the plurality of memory cells and data read from a reference element for erasing; and a data storage defect detection section for detecting a data storage defect of a memory cell among the plurality of memory cell, based on the first, second and third comparison results obtained from the data comparison section.

Abstract: A nonvolatile semiconductor memory device includes a plurality of memory cell array blocks including a first memory cell array block to which a data write operation is performed or from which a data erasure operation is performed, and a second memory cell array block from which a data read operation is performed concurrently with the data write operation or the data erasure operation to or from the first memory cell array block; and a plurality of block lock setting devices respectively provided in correspondence with the plurality of memory cell array blocks for placing the second memory cell array block into a locked state in which a data write operation to and a data erasure operation from the second memory cell array block is prohibited.

Abstract: A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.

Abstract: An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations.

Abstract: A programmable cell comprises an externally loadable electrically erasable (EE) transistor cell that is configured to be independent of the currently active state of the programmed cell. When all of the EE cells are loaded with a new configuration, the contents of all of the EE cells are loaded into the corresponding programmable cells, preferably within one clock cycle. Because the entirety of the programmable cells can be pre-loaded with the new configuration, the time to effect a reconfiguration is one clock cycle. Because an EE cell is significantly smaller than a conventional four to six transistor storage cell, the area required to implement this single-clock-cycle reconfiguration capability is substantially less than traditional dynamically reprogrammable memory configurations. In an alternative embodiment, multiple EE cells can be associated with each programmable cell, thereby allowing a multiple-configuration capability.

Abstract: A non-volatile semiconductor memory includes a plurality of memory areas, a control unit which performs a data-write or data-erase operation with respect to one of the memory areas, an address-detection unit which detects an address that indicates the one of the memory areas having the data-write or data-erase operation performed therein, and supplies information indicative of the address, and at least one output terminal which supplies the information to an exterior of the device.

Abstract: The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory.

Abstract: A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the FPGA is passed through a configuration port to a decoder. The decoder processes the configuration data to detect locked macros. If a locked macro is detected, the decoder attempts to unlock the locked macro using one or more keys stored in a key table of the FGPA. If an appropriate key is in the key table, the decoder unlocks the locked macro to configure the FPGA. The keys can be pre-programmed into the FGPA by the macro vendor. If configuration data containing a locked macro is used with an FPGA without the appropriate key, configuration of the FPGA fails.

Abstract: A coincidence circuit outputs a coincidence signal when a specific address derived from a specific address setting circuit and an input address coincided with each other. A counter circuit outputs a pulse signal each time the coincidence signal is inputted to a specified number of times. According to the pulse signal, a multiplexer switching circuit toggles the output of the multiplexer to the false data side connecting to a false data conversion circuit over a specified range of addresses. Thus, when addresses of the memory cell array are scanned in an unauthorized user's attempt at an illegal read, the false data is mixed into the read data at a specified period, making it difficult to reproduce correct data or correct programs from the acquired data. Consequently, with this memory device, it is impossible to reproduce correct data or correct programs even if an attempt to illegally read memory contents is made.

Abstract: A read protection memory area is formed within the same memory mat as a main memory area, so that the need to dedicatedly provide a dedicated EEPROM cell for storing read protection data and an analog control circuit for writing the read protection data into this EEPROM cell is eliminated and a chip size can be reduced.

Abstract: An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete.

Abstract: According to the present invention, access to a password area in a nonvolatile memory cannot be granted by simple supply of an address in a normal order. According to one preferable mode, for instance, a trap address is set in the password area so that reading information from the password area is permitted only when the password area is accessed without accessing the trap address, whereas when the password area is accessed through the trap address, information reading is inhibited, or meaningless data is output or the information in the password area is destroyed. According to another preferable mode, the order in which access is made to the password area can arbitrarily be set so that accessing the password area in this order alone can permit the password area to be read, whereas when access to the password area is made in a different order, information reading is inhibited, or meaningless data is output or the information in the password area is destroyed.