With Volatile Signal Storage Device Patents (Class 365/185.08)
  • Patent number: 11404419
    Abstract: A semiconductor memory cell having an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: August 2, 2022
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Jin-Woo Han
  • Patent number: 11392102
    Abstract: A driver IC (100) includes a pair of output terminals in each of a plurality of channels and in each of the channels, power is supplied from the pair of output terminals (OUT1 and OUT2, OUT3 and OUT4, OUT5 and OUT6 or OUT7 and OUT8) to a load (M1, M2, M3 or M4). In each of the channels, the pair of output terminals are adjacent to each other.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: July 19, 2022
    Assignee: Rohm Co., Ltd.
    Inventors: Takashi Fujimura, Takashi Kira
  • Patent number: 11380377
    Abstract: A contactless transponder includes a non-volatile static random access memory including memory points. Each memory point is formed by a volatile memory cell and a non-volatile memory cell. A protocol processing circuit receives data and stores the received data in the volatile memory cells of the memory. A write processing circuit is configured, at the end of the reception and storage of the data, to record, in a single write cycle, the data from the volatile memory cells to the non-volatile memory cells of the respective memory points.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: July 5, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francois Tailliet, Beatrice Brochier, Sylvain Fidelis
  • Patent number: 11361813
    Abstract: Technologies for a three-dimensional (3D) multi-bit non-volatile dynamic random access memory (nvDRAM) device, which may include a DRAM array having a plurality of DRAM cells with single or dual transistor implementation and a non-volatile memory (NVM) array having a plurality of NVM cells with single or dual transistor implementations, where the DRAM array and the NVM array are arranged by rows of word lines and columns of bit lines. The nvDRAM device may also include one or more of isolation devices coupled between the DRAM array and the NVM array and configured to control connection between the dynamic random access bit lines (BLs) and the non-volatile BLs. The word lines run horizontally and may enable to select one word of memory data, whereas bit lines run vertically and may be connected to storage cells of different memory address.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: June 14, 2022
    Assignee: Aspiring Sky Co. Limited
    Inventors: Zhijiong Luo, Xuntong Zhao
  • Patent number: 11361798
    Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: June 14, 2022
    Inventors: Kilho Lee, Gwanhyeob Koh, Junhee Lim, Hongsoo Kim, Chang-hoon Jeon
  • Patent number: 11355182
    Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 7, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaowei Deng, Wah Kit Loh
  • Patent number: 11348622
    Abstract: Apparatuses and methods can be related to implementing a conditional write back scheme for memory. The data may be stored by memory cells of a memory array. The data may be moved to sense circuitry. The data can be conditionally held by the sense circuitry while a plurality of operations is performed. The results of the plurality of operations can dictate whether to commit the data to the memory cells.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
  • Patent number: 11264065
    Abstract: A data transceiver device and an operation method are provided. The data transceiver device receives input data and transmits output data. The data transceiver device includes a buffer circuit, a storage circuit, a timing circuit and a control circuit. The buffer circuit is configured to store input data. The storage circuit is configured to store the output data. The timing circuit is configured to generate a time-out signal according to the set time. The control circuit is configured to process the input data to generate the output data, to store the output data in the storage circuit, and to transmit the output data according to an output data threshold value and the time-out signal. The control circuit adjusts the set time and/or the output data threshold value based on an initial condition and the state of the buffer circuit.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: March 1, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Zhen-Ting Huang, Chun-Hao Lin, Er-Zih Wong, Shih-Chiang Chu
  • Patent number: 11233068
    Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bong-soon Lim, Jin-young Kim, Sang-won Shim, Il-han Park
  • Patent number: 11222593
    Abstract: A top-emitting AMOLED panel includes a pixel circuit for each of multiple pixels. The circuit includes a first TFT connected to first, second, and third nodes; a second TFT connected to a scan signal, the first node and a data signal; a third TFT connected to the scan signal, the second node, and a reference voltage; a fourth TFT connected to the scan signal, the third node, and a high voltage power source; a first capacitor connected to the first node and the second node; a second capacitor connected to the third node and the reference voltage; and an OLED connected to the second node and a low voltage power source. The voltages supplied from the high voltage power source and the low voltage power source to the pixel are variable as functions of the location of the pixel on the panel, such that a voltage difference therebetween keeps unchanged.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: January 11, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Baixiang Han
  • Patent number: 11176993
    Abstract: A neuromorphic processor may include at least a first synapse element. The first synapse element may include a first bit cell and a second bit cell, the first bit cell connected to a first bitline, a first inverted bitline, a first wordline, and a first inverted wordline, and the second bit cell connected to the first bitline, the first inverted bitline, a second wordline, and a second inverted wordline. The first synapse element may be configured to receive a first input through the first wordline, the first inverted wordline, the second wordline, and the second inverted wordline, store a first synapse value in the first bit cell and the second bit cell, perform a calculation operation using the first input and the first synapse value, and output a result of the calculation through the first bitline and the first inverted bitline.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-In Kim, Youngnam Hwang
  • Patent number: 11115022
    Abstract: An accelerated aging circuit is described to shorten the required stress time to a few seconds of operation. Due to the challenges posed by process variation in advanced CMOS technology, a stochastic processing methodology is also described to reduce the failure rate of the tracking and detection. Combining both circuit and system level acceleration, the creation of a silicon marker can be realized within seconds of usage in contrast with days of operation from previously reported aging monitor.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: September 7, 2021
    Assignee: NORTHWESTERN UNIVERSITY
    Inventor: Jie Gu
  • Patent number: 11094393
    Abstract: Aspects of the present disclosure relate to systems and methods for issuing and executing a clear content command within a memory. Certain embodiments provide a method for the memory to receive a clear content command configured to clear content stored on the memory in a first set of memory cells of the plurality of memory cells of the plurality of memory banks. Certain embodiments provide a method of implementing within a DRAM memory the clear command by reusing existing refresh mechanism with minimal or no additional transistors or other hardware within the sense amplifier circuitry of the memory.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: August 17, 2021
    Assignee: QUALCOMM Incorporated
    Inventor: Olivier Alavoine
  • Patent number: 11061763
    Abstract: According to an aspect of inventive concepts, there is provided a memory controller configured to control a memory device including a plurality of memory pages, the memory controller including an error correction code (ECC) region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions, and an ECC engine configured to perform an ECC operation on data included in the ECC enable regions.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: July 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-hun Kim, Yong-sang Yu, Man-hwee Jo, Min-young Joe, Ji-woong Kim, Nak-hee Seong
  • Patent number: 11055011
    Abstract: A storage device includes a first nonvolatile memory device, a second nonvolatile memory device, and a data line. The second nonvolatile memory device is of a different type from the first nonvolatile memory device. The data line is shared by the first nonvolatile memory device and the second nonvolatile memory device. First data is simultaneously provided to the first nonvolatile memory device and the second nonvolatile memory device through the data line, the first data is written to the second nonvolatile memory device, and the first data is reprogrammed into the first nonvolatile memory device by reading the first data from the second nonvolatile memory device and providing the read first data to the first nonvolatile memory device.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee Sung Kim, Hyun Wook Shin
  • Patent number: 11049563
    Abstract: A mixed mode memory cell comprises a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line and two bit lines, wherein the two bit lines respectively transmit two data signals. The storage circuit is electrically coupled to the reading and writing component group. The selection circuit is electrically coupled to the reading and writing component group and the storage circuit, and configured to control the storage circuit to operate in a volatile storage mode or a non-volatile storage mode based on a selection voltage.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 29, 2021
    Assignee: JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD.
    Inventors: Yu-Cheng Liao, Chun-Chih Liu, Ching-Sung Chiu
  • Patent number: 11036398
    Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 15, 2021
    Assignee: Rambus, Inc.
    Inventors: Aws Shallal, Michael Miller, Stephen Horn
  • Patent number: 11024345
    Abstract: Disclosed is an improved load switch driver for Power Management Integrated Circuit (PMIC) devices. In one embodiment, a PMIC is disclosed comprising a gate driver, the gate driver connected to the gate of a switch; an operation frequency generator connected to the gate driver and configured to supply a periodic voltage to the gate driver; and a voltage sensor, the voltage sensor connected to the operation frequency generator and the source of the switch, the voltage sensor configured to monitor a drain-source voltage of the switch and lower the frequency of the operation frequency generator to a second frequency in response to detecting a collapse of the drain-source voltage.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Matthew David Rowley
  • Patent number: 10978112
    Abstract: Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Theodore T. Pekny, Victor Y. Tsai
  • Patent number: 10971229
    Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: April 6, 2021
    Assignee: Arm Limited
    Inventors: Akhilesh Ramlaut Jaiswal, Mudit Bhargava
  • Patent number: 10964393
    Abstract: Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: March 30, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hikaru Tamura
  • Patent number: 10950297
    Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Hikaru Tamura
  • Patent number: 10885989
    Abstract: A data storage apparatus includes storage and a controller configured to control the storage in response to a request from a host. The controller includes an internal voltage trimming circuit which includes: an integration circuit configured to generate an integration signal by integrating a difference between a test voltage output from a device under test (DUT) and a reference voltage; a comparison circuit configured to generate a comparison signal by comparing the integration signal and the reference voltage; a transition detection circuit configured to output a detection signal according to level transition of the comparison signal; a counter configured to receive an initial trimming code and generate a preliminary trimming code by increasing or reducing the initial trimming code in response to the detection signal; and an average circuit configured to generate a final trimming code by averaging the preliminary trimming code for a determined time interval and provide the final trimming code to the storage.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: January 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Young Jin Moon
  • Patent number: 10846236
    Abstract: A memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and a control logic configured to include at least one register in which a plurality of program algorithms and a plurality of pieces of operation information are stored, select any one of the program algorithms in response to an address of a program target page, among the pages, and perform a program operation on the program target page based on the selected program algorithm and operation information corresponding to the selected program algorithm.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventor: Jung Hwan Lee
  • Patent number: 10804276
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: October 13, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10796764
    Abstract: A semiconductor memory device includes a plurality of memory cells, and a control circuit configured perform a multi-bit write operation on the memory cells in response to sequentially received commands including a first command and a second command, which is received after the first command, the first command including first bits to be written respectively in the memory cells and the second command including second bits to be written respectively in the memory cells. The multi-bit write operation includes at least a first write operation including at least one program operation that is initiated after receipt of the first command and prior to the receipt of the second command, and a second write operation that is initiated after receipt of the second command.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: October 6, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshikazu Harada
  • Patent number: 10795809
    Abstract: A non-volatile logic device for energy-efficient logic state restoration is disclosed. The non-volatile logic device incorporates a volatile flip-flop and a non-volatile storage unit to achieve on-chip non-volatile storage. The non-volatile logic device further allows for a backup time to be determined on a per-chip basis, resulting in minimizing energy wastage and satisfying a given yield constraint.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: October 6, 2020
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Jinghua Yang, Sarma Vrudhula, Aykut Dengi
  • Patent number: 10789021
    Abstract: A memory device includes a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply a verifying voltage to the memory cells, for verifying at least one programming state of the memory cells; and a voltage controller configured to control the voltage generator to change a level of the verifying voltage as a program loop count increases, based on temperature information about a temperature inside or outside the memory device.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 29, 2020
    Assignee: Volentine, Whitt & Francos, PLLC
    Inventor: Yong-Sung Cho
  • Patent number: 10776153
    Abstract: An information processing device connectable to a plurality of storage devices includes a power source circuit configured to supply power from a backup power source to each of the plurality of storage devices in response to a power loss event, and a processor. The processor is configured to transmit, to each of the storage devices, a first instruction to save user data that have been transmitted to the storage device and have not been written in a non-volatile manner, in response to the power loss event, and transmit, to at least one of the storage devices, a second instruction to save updated address translation information that corresponds to the user data and has not been reflected in an address translation table, upon receiving a response indicating completion of saving the user data from each of the storage devices.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: September 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Patent number: 10677839
    Abstract: A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of the interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: June 9, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francesco La Rosa
  • Patent number: 10529406
    Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows, a temperature sensor that detects a temperature of the memory cell array and generates internal temperature data, a first register that stores external temperature data received from outside of the memory device, and a refresh control unit that determines a skip ratio of refresh commands received at a refresh frequency that corresponds to the external temperature data by comparing the internal temperature data and the external temperature data and performing a refresh operation for the plurality of memory cell rows in response to refresh commands skipped and transmitted based on the skip ratio.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO. LTD.
    Inventors: Won Jun Choi, Hui Kap Yang
  • Patent number: 10490294
    Abstract: Systems and methods are directed to an integrated circuit to sense a state of a fuse having one of a blown state and an unblown state. The integrated circuit includes a fuse sensing circuit having an input and a plurality of outputs, the input being configured to receive a sense signal having a first state and a second state, and the plurality of outputs including a first output to connect to a first contact of the fuse, a second output to provide a first signal indicative of the state of the fuse, and a third output to provide a second signal indicative of the state of the fuse, the fuse sensing circuit being configured to provide the first and second signals responsive to a change in state of the sense signal, and a latch circuit having a first input to receive the first signal, a second input to receive the second signal, and an output to provide an output signal indicative of the state of the fuse, the latch circuit being configured to store and maintain a value of the output signal.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 26, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Bo Zhou, Guillaume Alexandre Blin
  • Patent number: 10360980
    Abstract: Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 10354737
    Abstract: A non-volatile memory is configured to allow programming and erase at the sub-block level. In a sub-block erase, some of the memory cells can be selected for erase while others are not selected for erase, such as by leaving their word lines to float while applying the erase voltage to the well structure of the physical block to which the sub-blocks belong. Although a sub-block erase applies a lower electric field across the non-selected memory cells than the erase selected memory cells, it still places the non-selected memory cells under some degree of stress and can lead to erase disturb. To help manage this erase disturb, each sub-block has an associated erase disturb count, which is incremented when another sub-block of the same physical block is erased, but reset when the sub-block itself is erase. Once a count reaches a threshold value, the sub-block can be marked for remedial action, such as refresh or garbage collection.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 16, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Xinde Hu
  • Patent number: 10303372
    Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngjin Cho, Sungyong Seo, Sun-Young Lim, Uksong Kang, Chankyung Kim, Duckhyun Chang, JinHyeok Choi
  • Patent number: 10282133
    Abstract: A memory device is provided. The memory device includes a memory array, operation circuitry configured to perform a memory operation in the memory array in response to a command received from a connected host device, and delay circuitry configured to delay the performance of the memory operation in response to one or more bits received with the command. The one or more bits indicate a duration by which to delay the performance of the memory operation.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 7, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Matthew A. Prather
  • Patent number: 10262731
    Abstract: A device includes a first word line, a resistive random access memory (RRAM) cell, a second word line, and a charge pump circuit. The RRAM cell is coupled to the first word line and is not formed. The charge pump circuit is coupled to the second word line and is configured to provide a negative voltage. Methods of forming the device are also disclosed.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Yu-Wei Ting, Chun-Yang Tsai, Kuo-Ching Huang
  • Patent number: 10241723
    Abstract: A memory card includes first and second groups of terminals, at least one controller, and first and second nonvolatile memories. The first group of terminals are adjacent to an edge at an insertion side of a substrate and include a first power terminal to provide a first voltage. The second group of terminals is spaced farther apart from the edge at the insertion side than the first group of terminals and includes a second power terminal to provide a second voltage. The at least one memory controller is connected to the first and second groups of terminals, and the first and second nonvolatile memories are independently connected to the at least one controller. The at least one controller simultaneously accesses the first nonvolatile memory and the second nonvolatile memory when the first group of terminals and the second group of terminals are connected to an external host.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: March 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-Jae Lee, Kwang-Soo Kim, Hyong-Woo Yu
  • Patent number: 10241683
    Abstract: A data processing system includes a backup nonvolatile memory (NVM), a random access memory (RAM), and a controller. The RAM includes a plurality of partitions, each partition having a different corresponding backup frequency. The controller is configured to back up the contents of each partition of the RAM to the backup NVM in accordance with the corresponding backup frequency.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Frank Kelly Baker, Jr., David B. Kramer, Anirban Roy
  • Patent number: 10229738
    Abstract: Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David D. Cadigan, William V. Huott, Adam J. McPadden, Anuwat Saetow
  • Patent number: 10223018
    Abstract: The amount of remapping data in a file system of a memory device is reduced. In one aspect, for each request access, e.g., read or write operation, the memory cells of a primary physical address are evaluated. If the evaluation indicates the memory cells are good, the read or write operation proceeds. If the memory cells have a failure such as uncorrectable errors, the primary physical address is hashed to obtain an auxiliary physical address. If the auxiliary physical address is not available, the primary physical address can be hashed again to obtain another auxiliary physical address. In another aspect, per-page remapping is performed until a threshold number of bad pages in a block are detected, after which the entire block is remapped. In another aspect, pages of a block are remapped to auxiliary pages based on a block identifier.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: March 5, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Kiran Gunnam, Robert Mateescu
  • Patent number: 10185515
    Abstract: An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: January 22, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Hyunsuk Shin, Jung Pill Kim, Dexter Tamio Chun, Jungwon Suh
  • Patent number: 10185508
    Abstract: Technologies are provided for remotely destroying a storage device. One or more commands can be transmitted to a storage device to render the storage device inoperable. The storage device can be placed in a retired operation mode, in which the storage device cannot process data access commands. Data stored in the storage device can be sanitized to prevent it from being retrieved. Code modules that are responsible for processing data access commands can be erased from a firmware of the storage device. The storage device can perform operations to render a storage medium of the storage device inoperable. While in the retired mode, the storage device can process an inquiry command to retrieve information about the storage device from the firmware of the storage device. The retrieved information can be used to generate a digital destruction certificate that can be provided to a supplier of the storage device.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 22, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Munif M. Farhan, Luis Padilla Munoz, Troy Cognata
  • Patent number: 10177924
    Abstract: A physically unclonable function unit includes and anti-fuse transistor and a control circuit. The anti-fuse transistor has a first terminal, a second terminal, and a gate terminal. The control circuit is coupled to the anti-fuse transistor. During an enroll operation, the control circuit applies an enroll voltage to the gate terminal of the anti-fuse transistor and applies a reference voltage to the first terminal and the second terminal of the anti-fuse transistor. The enroll voltage is higher than the reference voltage, and is high enough to create a rupture path on the gate terminal to the first terminal or to the second terminal.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: January 8, 2019
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Meng-Yi Wu, Po-Hao Huang
  • Patent number: 10120674
    Abstract: An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: November 6, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ralf Brederlow, Oscar Miguel Guillen-Hernandez, Peter Wongeun Chung
  • Patent number: 10102081
    Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: October 16, 2018
    Assignee: Rambus Inc.
    Inventors: Shih-ho Wu, Christopher Haywood
  • Patent number: 10061617
    Abstract: A system of processing a task based on information of frequently used algorithms learned through a memory unit includes a first memory, a second memory, a processor, and a reading unit. The processor processes a first type of task using a first algorithm, and writes to a first memory cell of the second memory. The second memory including first and second memory cells each having a charge storage element. The first and second memory cells correspond to the first and second algorithms, respectively. The reading unit senses a first voltage stored in the first memory cell and a second voltage stored in the second memory cell, and provides information of frequently used algorithms to the processing device based on the sensed first and second voltages.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10014071
    Abstract: A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 3, 2018
    Assignee: SK Hynix Inc.
    Inventors: Min-Su Park, Jae-Il Kim, Tae-Kyun Kim, Jun-Gi Choi
  • Patent number: 10007603
    Abstract: A nonvolatile memory device includes a mat including a plurality of memory blocks, an address decoder configured to select one of the memory blocks in response to an address, an input/output circuit including first and second page buffers configured to program a plurality of data pages into a single physical page of the selected one of the memory blocks or store the plurality of data pages read from the single physical page of the selected one of the memory blocks, and a control logic configured to perform a dumping operation at an other one of the first page buffers and second page buffers when a data input operation or a data output operation is performed at one of the first and second page buffers of the input/output circuit. The input/output circuit includes a plurality of page buffers. The plurality of page buffers include the first and second page buffers.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Jun Lee, Dongku Kang
  • Patent number: 9997237
    Abstract: A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 12, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Joseph S Tandingan, David W. Still, Jesse J Siman, Jayant Ashokkumar