With Volatile Signal Storage Device Patents (Class 365/185.08)
  • Patent number: 10529406
    Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows, a temperature sensor that detects a temperature of the memory cell array and generates internal temperature data, a first register that stores external temperature data received from outside of the memory device, and a refresh control unit that determines a skip ratio of refresh commands received at a refresh frequency that corresponds to the external temperature data by comparing the internal temperature data and the external temperature data and performing a refresh operation for the plurality of memory cell rows in response to refresh commands skipped and transmitted based on the skip ratio.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO. LTD.
    Inventors: Won Jun Choi, Hui Kap Yang
  • Patent number: 10490294
    Abstract: Systems and methods are directed to an integrated circuit to sense a state of a fuse having one of a blown state and an unblown state. The integrated circuit includes a fuse sensing circuit having an input and a plurality of outputs, the input being configured to receive a sense signal having a first state and a second state, and the plurality of outputs including a first output to connect to a first contact of the fuse, a second output to provide a first signal indicative of the state of the fuse, and a third output to provide a second signal indicative of the state of the fuse, the fuse sensing circuit being configured to provide the first and second signals responsive to a change in state of the sense signal, and a latch circuit having a first input to receive the first signal, a second input to receive the second signal, and an output to provide an output signal indicative of the state of the fuse, the latch circuit being configured to store and maintain a value of the output signal.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 26, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Bo Zhou, Guillaume Alexandre Blin
  • Patent number: 10360980
    Abstract: Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 10354737
    Abstract: A non-volatile memory is configured to allow programming and erase at the sub-block level. In a sub-block erase, some of the memory cells can be selected for erase while others are not selected for erase, such as by leaving their word lines to float while applying the erase voltage to the well structure of the physical block to which the sub-blocks belong. Although a sub-block erase applies a lower electric field across the non-selected memory cells than the erase selected memory cells, it still places the non-selected memory cells under some degree of stress and can lead to erase disturb. To help manage this erase disturb, each sub-block has an associated erase disturb count, which is incremented when another sub-block of the same physical block is erased, but reset when the sub-block itself is erase. Once a count reaches a threshold value, the sub-block can be marked for remedial action, such as refresh or garbage collection.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 16, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Xinde Hu
  • Patent number: 10303372
    Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngjin Cho, Sungyong Seo, Sun-Young Lim, Uksong Kang, Chankyung Kim, Duckhyun Chang, JinHyeok Choi
  • Patent number: 10282133
    Abstract: A memory device is provided. The memory device includes a memory array, operation circuitry configured to perform a memory operation in the memory array in response to a command received from a connected host device, and delay circuitry configured to delay the performance of the memory operation in response to one or more bits received with the command. The one or more bits indicate a duration by which to delay the performance of the memory operation.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 7, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Matthew A. Prather
  • Patent number: 10262731
    Abstract: A device includes a first word line, a resistive random access memory (RRAM) cell, a second word line, and a charge pump circuit. The RRAM cell is coupled to the first word line and is not formed. The charge pump circuit is coupled to the second word line and is configured to provide a negative voltage. Methods of forming the device are also disclosed.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Yu-Wei Ting, Chun-Yang Tsai, Kuo-Ching Huang
  • Patent number: 10241723
    Abstract: A memory card includes first and second groups of terminals, at least one controller, and first and second nonvolatile memories. The first group of terminals are adjacent to an edge at an insertion side of a substrate and include a first power terminal to provide a first voltage. The second group of terminals is spaced farther apart from the edge at the insertion side than the first group of terminals and includes a second power terminal to provide a second voltage. The at least one memory controller is connected to the first and second groups of terminals, and the first and second nonvolatile memories are independently connected to the at least one controller. The at least one controller simultaneously accesses the first nonvolatile memory and the second nonvolatile memory when the first group of terminals and the second group of terminals are connected to an external host.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: March 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-Jae Lee, Kwang-Soo Kim, Hyong-Woo Yu
  • Patent number: 10241683
    Abstract: A data processing system includes a backup nonvolatile memory (NVM), a random access memory (RAM), and a controller. The RAM includes a plurality of partitions, each partition having a different corresponding backup frequency. The controller is configured to back up the contents of each partition of the RAM to the backup NVM in accordance with the corresponding backup frequency.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Frank Kelly Baker, Jr., David B. Kramer, Anirban Roy
  • Patent number: 10229738
    Abstract: Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David D. Cadigan, William V. Huott, Adam J. McPadden, Anuwat Saetow
  • Patent number: 10223018
    Abstract: The amount of remapping data in a file system of a memory device is reduced. In one aspect, for each request access, e.g., read or write operation, the memory cells of a primary physical address are evaluated. If the evaluation indicates the memory cells are good, the read or write operation proceeds. If the memory cells have a failure such as uncorrectable errors, the primary physical address is hashed to obtain an auxiliary physical address. If the auxiliary physical address is not available, the primary physical address can be hashed again to obtain another auxiliary physical address. In another aspect, per-page remapping is performed until a threshold number of bad pages in a block are detected, after which the entire block is remapped. In another aspect, pages of a block are remapped to auxiliary pages based on a block identifier.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: March 5, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Kiran Gunnam, Robert Mateescu
  • Patent number: 10185508
    Abstract: Technologies are provided for remotely destroying a storage device. One or more commands can be transmitted to a storage device to render the storage device inoperable. The storage device can be placed in a retired operation mode, in which the storage device cannot process data access commands. Data stored in the storage device can be sanitized to prevent it from being retrieved. Code modules that are responsible for processing data access commands can be erased from a firmware of the storage device. The storage device can perform operations to render a storage medium of the storage device inoperable. While in the retired mode, the storage device can process an inquiry command to retrieve information about the storage device from the firmware of the storage device. The retrieved information can be used to generate a digital destruction certificate that can be provided to a supplier of the storage device.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 22, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Munif M. Farhan, Luis Padilla Munoz, Troy Cognata
  • Patent number: 10185515
    Abstract: An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: January 22, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Hyunsuk Shin, Jung Pill Kim, Dexter Tamio Chun, Jungwon Suh
  • Patent number: 10177924
    Abstract: A physically unclonable function unit includes and anti-fuse transistor and a control circuit. The anti-fuse transistor has a first terminal, a second terminal, and a gate terminal. The control circuit is coupled to the anti-fuse transistor. During an enroll operation, the control circuit applies an enroll voltage to the gate terminal of the anti-fuse transistor and applies a reference voltage to the first terminal and the second terminal of the anti-fuse transistor. The enroll voltage is higher than the reference voltage, and is high enough to create a rupture path on the gate terminal to the first terminal or to the second terminal.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: January 8, 2019
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Meng-Yi Wu, Po-Hao Huang
  • Patent number: 10120674
    Abstract: An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: November 6, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ralf Brederlow, Oscar Miguel Guillen-Hernandez, Peter Wongeun Chung
  • Patent number: 10102081
    Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: October 16, 2018
    Assignee: Rambus Inc.
    Inventors: Shih-ho Wu, Christopher Haywood
  • Patent number: 10061617
    Abstract: A system of processing a task based on information of frequently used algorithms learned through a memory unit includes a first memory, a second memory, a processor, and a reading unit. The processor processes a first type of task using a first algorithm, and writes to a first memory cell of the second memory. The second memory including first and second memory cells each having a charge storage element. The first and second memory cells correspond to the first and second algorithms, respectively. The reading unit senses a first voltage stored in the first memory cell and a second voltage stored in the second memory cell, and provides information of frequently used algorithms to the processing device based on the sensed first and second voltages.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10014071
    Abstract: A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 3, 2018
    Assignee: SK Hynix Inc.
    Inventors: Min-Su Park, Jae-Il Kim, Tae-Kyun Kim, Jun-Gi Choi
  • Patent number: 10007603
    Abstract: A nonvolatile memory device includes a mat including a plurality of memory blocks, an address decoder configured to select one of the memory blocks in response to an address, an input/output circuit including first and second page buffers configured to program a plurality of data pages into a single physical page of the selected one of the memory blocks or store the plurality of data pages read from the single physical page of the selected one of the memory blocks, and a control logic configured to perform a dumping operation at an other one of the first page buffers and second page buffers when a data input operation or a data output operation is performed at one of the first and second page buffers of the input/output circuit. The input/output circuit includes a plurality of page buffers. The plurality of page buffers include the first and second page buffers.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Jun Lee, Dongku Kang
  • Patent number: 9997237
    Abstract: A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 12, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Joseph S Tandingan, David W. Still, Jesse J Siman, Jayant Ashokkumar
  • Patent number: 9972494
    Abstract: A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Ruilong Xie
  • Patent number: 9959053
    Abstract: The present invention provides a method for constructing an NVRAM-based efficient file system, including the following steps: S1. determining a file operation type of the file system, where the file operation type includes a file read operation, a non-persistent file write operation, and a persistent file write operation; and S2. if the file operation type is a non-persistent file write operation, writing, by the file system, content of the non-persistent file write operation to a dynamic random access memory DRAM, updating a corresponding DRAM cache block index, and flushing, at a preset time point, the content of the non-persistent file write operation back to a non-volatile random access memory NVRAM asynchronously, or otherwise, copying, by the file system, related data directly between the NVRAM/DRAM and the user buffer.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 1, 2018
    Inventors: Jiwu Shu, Jiaxin Ou, Youyou Lu
  • Patent number: 9928182
    Abstract: A memory system comprises an SRAM array and a NVM array. The SRAM array and NVM array are both organized in rows and columns. The NVM array is directly coupled to the SRAM array. The memory system may also be coupled to a system bus of a data processing system. The number of columns of the NVM array is an integer multiple of the number of columns of the SRAM array, where the integer multiple is greater than one. Column logic is coupled to the SRAM array and to the NVM array. The column logic controls accesses to the SRAM and to the NVM array, and the column logic controls direct data transfers between the SRAM array and the NVM array.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: March 27, 2018
    Assignee: NXP USA, Inc.
    Inventors: Perry H. Pelley, Anirban Roy
  • Patent number: 9859415
    Abstract: High voltage devices and methods for forming a high voltage device are disclosed. The high voltage device includes a substrate prepared with a device isolation region. The device isolation region defines a device region. The device region includes at least first and second source/drain regions and a gate region defined thereon. A device well is disposed in the device region. The device well encompasses the at least first and second source/drain regions. A primary gate and at least one secondary gate adjacent to the primary gate are disposed in the gate region. The at least first and second source/drain regions are displaced from first and second sides of the primary gate.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: January 2, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Xinfu Liu, Xueming Dexter Tan
  • Patent number: 9842650
    Abstract: A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M1a or the second memory cell M1b. Thus memory capacity is increased.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: December 12, 2017
    Assignee: FLOADIA CORPORATION
    Inventors: Yasuhiro Taniguchi, Yutaka Shinagawa, Hideo Kasai, Ryotaro Sakurai, Tatsuro Toya, Yasuhiko Kawashima, Kosuke Okuyama
  • Patent number: 9792219
    Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: October 17, 2017
    Assignee: Si-Flash Drives, LLC
    Inventor: G. R. Mohan Rao
  • Patent number: 9779814
    Abstract: Non-Volatile Static Random Access Memory (NVSRAM) cell devices applying only one single non-volatile element embedded in a conventional Static Random Access Memory (SRAM) cell are disclosed. The NVSRAM cell devices can be integrated into a compact cell array. The NVSRAM devices of the invention have a read/write speed of a conventional SRAM and non-volatile property of a non-volatile memory cell. The methods of operations for the NVSRAM devices of the invention are also disclosed.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: October 3, 2017
    Assignee: Flashsilicon Incorporation
    Inventor: Lee Wang
  • Patent number: 9747983
    Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: August 29, 2017
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 9741454
    Abstract: A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: August 22, 2017
    Assignee: SK Hynix Inc.
    Inventors: Sang Kyu Lee, Chang Geun Kim
  • Patent number: 9740431
    Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.
    Type: Grant
    Filed: July 17, 2016
    Date of Patent: August 22, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Syed M. Alam, Thomas Andre, Dietmar Gogl
  • Patent number: 9728249
    Abstract: Various implementations described herein are directed to a circuit for memory applications. The circuit may include a data storage structure having column multiplexor transistors coupled to complementary bitlines. The circuit may include a wordline shape enhancer having a pair of passgate transistors coupled between the complementary bitlines and a capacitive load.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: August 8, 2017
    Assignee: ARM Limited
    Inventors: Cédric Sacha Redeau, Nicolaas Klarinus Johannes van Winkelhoff
  • Patent number: 9721633
    Abstract: A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows in each of the banks; and an address latch circuit configured to latch a full address specifying one of the word lines, the full address including a first address and a second address. The address latch circuit receives a first command and a second command to latch the first address and the second address in accordance with the first command and the second command, respectively. Paths for the first address and the second address are configured to be separate from each other.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Naoki Shimizu
  • Patent number: 9685239
    Abstract: A Field Sub-bitline NOR-type (FSNOR) flash array and its operating methods are disclosed. In contrast to the conventional NOR flash array, the FSNOR array is configured in column with multiple 90° rotated NOR pairs linked by field side sub-bitlines to achieve the minimum 4F2 cell size. The FSNOR flash array is divided into multiple sectors by selection transistors for connecting the even/odd sub-bitlines to the global main first metal bitlines. For each FSNOR sector, the two drain electrodes of column-adjacent NOR pairs form the even/odd sub-bitlines separated by trench field oxides respectively, and the common source electrodes of NOR pairs in a column form the common diffusion source lines tied with metal contacts connected to the first metal common source lines. The FSNOR flash array design has enhanced the electrical isolation of the selected NVM cell devices from the unselected NVM cell devices.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: June 20, 2017
    Assignee: PEGASUS SEMICONDUCTOR (BEIJING) CO., LTD
    Inventor: Lee Wang
  • Patent number: 9633745
    Abstract: A semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: April 25, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenichi Abe, Masanobu Shirakawa, Mizuho Yoshida, Takuya Futatsuyama
  • Patent number: 9620212
    Abstract: A memory array including: a plurality of volatile memory cells, each including a latch; and a plurality of non-volatile memory cells, each including at least one resistive element that can be programmed by the direction of a current passed therethrough in order to take at least two resistive states, each of the non-volatile memory cells being associated with a corresponding cell from the volatile memory cells.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: April 11, 2017
    Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Centre National de la Recherche Scientifique
    Inventors: Virgile Javerliac, Christophe Layer
  • Patent number: 9530502
    Abstract: A configuration memory includes: memory cell including first and second MISFETs, each of the first and second MISFETs having a gate insulating layer, a source, a drain, and a gate, one of the source and the drain of the first MISFET being connected to a first bit line, the gate of the first MISFET being connected to a first word line, one of the source and the drain of the second MISFET being connected to a second bit line, the gate of the second MISFET being connected to the first word line; a sense amplifier having an output terminal and connected to the first and second bit lines; and a control circuit which is configured to write data in the memory cell by injecting carriers in the gate insulating layer of the first MISFET.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: December 27, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kosuke Tatsumura
  • Patent number: 9530490
    Abstract: A data storage device may include a memory die. The memory die may include a memory. A method may include selecting a source compaction block of the memory for a compaction process. The source compaction block stores data. The method may further include writing the data to a destination compaction block of the memory at a rate that is based on a number of multiple blocks of the memory associated with the compaction process.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: December 27, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman
  • Patent number: 9508433
    Abstract: The invention concerns a memory cell comprising: first and second resistive elements (202, 204), at least one of which can be programmed to adopt at least two resistive states (Rmin Rmax); the first resistive element (202) being coupled between a first storage node (206) and a first intermediate node (208), the second resistive element (204) being coupled between a second storage node (210) and a second intermediate node (212); a transistor (220) coupled between the first and second intermediate nodes; and a control circuit arranged to activate the transistor while a second supply voltage (VDD, GND) is being applied to the first or second storage node to generate a programming current in a selected direction through the first and second resistive elements in order to program the resistive state of at least one of the elements.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: November 29, 2016
    Assignees: Centre National de la Recherche Scientifique, Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Guillaume Prenat, Grégory Di Pendina
  • Patent number: 9508443
    Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: November 29, 2016
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Patent number: 9484072
    Abstract: A nonvolatile memory device includes a pair of MIS transistors one of which is placed in a programmed state by a first program operation utilizing a hot carrier effect to store one-bit data in the pair of MIS transistors, and a control unit configured to recall the one-bit data from the pair of MIS transistors in a recall operation, to cause an unprogrammed one of the MIS transistors to be placed in a programmed state by a second program operation utilizing a hot carrier effect in response to the one-bit data recalled from the pair of MIS transistors, and to erase the programmed states of both of the MIS transistors in an erase operation.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: November 1, 2016
    Assignee: NSCore, Inc.
    Inventor: Kenji Noda
  • Patent number: 9455036
    Abstract: A system can include a first memory section comprising a plurality of volatile memory cells; a second memory section comprising a plurality of nonvolatile memory cells; a first data path configured to transfer data between the first and second memory sections; an interface circuit coupled to receive access commands and address values, the interface circuit configured to determine if a data transfer operation is occurring in the device, and if the data transfer operation is occurring, accessing the address in the first memory section or accessing a location in the second memory section based on a select value, and if the data transfer operation is not occurring, accessing the address in the first memory section; and a compare circuit configured to compare a received address to a predetermined value to generate the select value.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: September 27, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: Ed McKernan, Malcolm Wing, Ravi Sunkavalli
  • Patent number: 9442641
    Abstract: An operation unit-equipped device includes a generator that generates an application module including a processing executor that executes a processing, a display part that performs a display appropriated to the processing executor, and a controller that controls the processing executor and the display part; and a discard requester that requests, when at least one new processing executor and one new display part are generated after the generation of the processing executor and the display part, a discard of the processing executor and the display part generated previously. When there is an active processing in the processing executor generated previously when the request for discard is made, the controller discards the display part generated previously and maintains the processing executor generated previously until the active processing is completed, and discards the processing executor generated previously when the active processing in the processing executor generated previously is completed.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: September 13, 2016
    Assignee: RICOH COMPANY, LTD.
    Inventor: Hiroki Asakimori
  • Patent number: 9431108
    Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: August 30, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Marc Battista, François Tailliet
  • Patent number: 9418001
    Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: August 16, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre, Dietmar Gogl
  • Patent number: 9411719
    Abstract: A memory system having multiple memory layers includes a first memory layer comprising a volatile memory, a second memory layer comprising a first sub-memory and a second sub-memory. In response to a reference failure that occurred in the first memory layer, to which a read reference failed data and a write reference failed data are respectively loaded from a lower level memory layer.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: August 9, 2016
    Assignee: SEONG UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION
    Inventor: Gi Ho Park
  • Patent number: 9389786
    Abstract: A memory device includes storage layers each comprising memory cells arranged in a plurality of rows, bit lines coupled to the memory cells in the corresponding rows, tracking cells arranged in at least one row, at least one tracking bit line coupled to the tracking cells, and at least one sense amplifier coupled to the bit lines. The sense amplifier is configured to detect data stored in the memory cells, and has an enabling terminal coupled to the at least one tracking bit line. The memory device further comprises word lines and tracking word lines extending through the storage layers. The word lines are coupled to the corresponding memory cells in the storage layers. The tracking word lines are coupled to the corresponding tracking cells in the storage layers.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: July 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chien Tsai, Yu-Hao Hsu, Chih-Yu Lin, Chen-Lin Yang, Cheng Hung Lee
  • Patent number: 9384861
    Abstract: A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: July 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Min Oh, Ho-Young Song, Seong-Jin Jang
  • Patent number: 9356054
    Abstract: A semiconductor device that is suitable for miniaturization is provided. Alternatively, a highly reliable semiconductor device is provided. A semiconductor device including a capacitor and a transistor is provided. In the semiconductor device, the transistor includes a semiconductor layer, the semiconductor layer is positioned over the capacitor, and the capacitor includes a first electrode that is electrically connected to the transistor.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 31, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Shunpei Yamazaki
  • Patent number: 9356598
    Abstract: This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: May 31, 2016
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Sarma Vrudhula, Jinghua Yang, Niranjan Kulkarni, Shimeng Yu
  • Patent number: 9355715
    Abstract: A memory system and a method of operating the same are provided. The method includes reading least significant bit (LSB) data of a first physical page based on a first pre-read voltage and performing a most significant bit (MSB) program based on the LSB data of the first physical page when the MSB program is performed on the first physical page, defining a management area by comparing the number of error bits included in MSB data of the first physical page with a first threshold value, preforming an LSB program on a second physical page of the management area, reading LSB data of the second physical page based on a second pre-read voltage, which is lower than the first pre-read voltage, and performing the MSB program on the second physical page based on the LSB data of the second physical page.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: May 31, 2016
    Assignee: SK Hynix Inc.
    Inventor: Young Gyun Kim