Abstract: A first page read on the first memory page utilizing a first trim value is performed responsive to initiating a memory page scan on a first memory page of a plurality of memory pages. Whether a first data state metric associated with the first page read satisfies a first threshold criterion is determined. A second page read on the first memory page utilizing a second trim value is performed responsive to determining that the first data state metric satisfies the first threshold criterion. Whether a second data state metric associated with the second page read satisfies a second threshold criterion is determined. The second trim value to perform subsequent page reads during memory page scans is selected responsive to determining that the second data state metric does not satisfy the first threshold criterion.

Abstract: An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.

Abstract: A bridge chip includes a first selection circuit, a second selection circuit, and a control circuit. The first selection circuit determines an output destination of input data and an input flag indicating whether the input data is valid or invalid based on a first selection signal. The second selection circuit determines an output destination of the input data and the input flag output from the first selection circuit based on a second selection signal. The control circuit generates the first selection signal and the second selection signal, and outputs the first selection signal and the second selection signal to the first selection circuit and the second selection circuit, respectively.

Abstract: In one example, the memory system includes a memory coupled to a memory controller; the memory includes a plurality of word lines and a plurality of multi-bit memory cells coupled to the plurality of word lines; the memory includes multiple types of pages, each corresponding to a one read voltage level. In one example, the operation method includes obtaining, when a read operation of the memory fails, a target read retry table from a set of read retry tables, the set of read retry tables comprises all read retry tables corresponding to the multiple types of pages; a read retry table corresponding to each type of page comprises a set of bias voltages corresponding to respective read voltage levels that are used to distinguish stored data of corresponding bit; obtaining read retry voltages through the target read retry table, and performing a read retry operation using the read retry voltages.

Abstract: Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the plurality of memory planes, to perform operations that include, identifying a first block residing on a memory plane of the memory device, wherein the first block is associated with an error condition; and responsive to identifying the first block, performing an error recovery operation to replace the first block with a second block, wherein the second block resides on the memory plane.

Abstract: A storage device may execute a read retry operation on a plurality of memory cells when a failure occurs during a read operation on the plurality of memory cells. The storage device may perform the read retry operation based on M history read biases, and determine a first sequence in which the M history read biases are applied when the read retry operation is performed, based on a read retry sequence key.

Abstract: An MRAM cell includes a switch unit configured to determine opening and closing thereof by a word line voltage and to activate a current path between a bit line and a bit line bar in an opened state thereof, first and second MTJs having opposite states, respectively, and connected in series between the bit line and the bit line bar, to constitute a storage node, and a sensing line configured to be activated in a reading mode of the MRAM cell, thereby creating data reading information based on a voltage between the first and second MTJs, wherein the first and second MTJs have different ones of a low resistance state and a high resistance state, respectively, in accordance with a voltage drop direction between the bit line and the bit line bar, thereby storing data of 0 or 1.

Abstract: A decoding method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending at least one read command sequence instructing to read a first physical unit in a rewritable non-volatile memory module; receiving response data from the rewritable non-volatile memory module, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect a voltage variation of a first bit line where a first memory cell in the first physical unit is located during a discharge process; determining a decoding parameter corresponding to the first memory cell according to the plurality of identification bits; and decoding data read from the first memory cell according to the decoding parameter.

Abstract: According to one embodiment, an information processing apparatus includes a connecting portion connectable to a removable memory device and a power supply circuit configured to apply a first voltage and a second voltage to the removable memory device. When the removable memory device is connected to the connecting portion, one of a pair of first feedback wires is electrically connected to one of the first power supply terminals to which the first voltage is applicable, and the other of the pair of first feedback wires is electrically connected to one of the power supply ground terminals connectable to a ground level, the power supply circuit is configured to control the first voltage, based on a voltage between the pair of first feedback wires.

Abstract: A memory device includes source-drain structure bodies and gate structure bodies arranged along a first direction, and global word lines. The source-drain structure body includes a bit line, and first to third semiconductor layers. The first and second semiconductor layers are of first conductivity type and the first semiconductor layer is connected to the bit line. The third semiconductor layer of a second conductivity type contacts the first and second semiconductor layers. The gate structure body includes a local word line and a charge storage film. A first source-drain structure body includes a bit line forming a first reference bit line. A first global word line connects to the local word lines in the gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.

Abstract: Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).

Abstract: A method includes, in response to detecting a power on event, selecting a block from a set of blocks, causing a first scan to be performed using a set of read level offsets to select, from a set of bins in accordance with a scan order, a first bin assigned with a first read level offset resulting in a first bit error metric value, in response to determining that the first bin is not an initial bin of the scan order, causing, using a second read level offset assigned to a second bin, a second scan to be performed to obtain a second bit error metric value, wherein the second bin immediately precedes the first bin in the scan order, and selecting, based on first bit error metric value and the second bit error metric value, an optimal bin from the set of bins.

Abstract: A semiconductor device includes a memory circuit including first and second banks and configured to count the numbers of inputs of first and second active signals for executing active operations on the first and second banks to generate a counting signal and to generate first and second hammering detection signals when the numbers of inputs of the first and second active signals are equal to or greater than a set number, and an active control circuit configured to store an active address as a target address when at least one of the first and second hammering detection signals is enabled, and to execute addition and subtraction operations on the target address to output a result of the addition and subtraction operations as an internal address for at least one of the first and second banks for executing a smart refresh operation, based on the counting signal in a refresh operation.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a program operation performer configured to perform a plurality of program loops on the plurality of memory cells, a step voltage calculator configured to calculate a step voltage, the step voltage being a difference of magnitude between program voltages that are applied in any two consecutive program loops, a reference bit determiner configured to determine a reference number of fail bits based on a magnitude of the step voltage, and a verification result generator configured to generate verification result information based on a result of a comparison between the reference number of fail bits and a number of on-cells, among the plurality of memory cells, identified in a verify operation that is included in a program loop, among the plurality of program loops.

Abstract: A solution for improving the correction of errors in a 2T2R resistive memory protected by an error correction code. A method that makes it possible, through 1T1R read operations, to identify, in a codeword stored in memory, bits liable to be incorrect, called “erasures”, and then to invert these bits in the stored codeword in order to generate a new word corrected by the ECC.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

Abstract: Practical, energy-efficient, and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The mitigation may be implemented on a per-bank basis. The memory media device may be DRAM.

Abstract: An embodiment of an electronic apparatus may include one or more substrates; and a controller coupled to the one or more substrates, the controller including logic to control access to a NAND-based storage media that includes a first cell region with a first number of levels and a second region with a second number of levels that is different from the first number of levels, determine logical block address locations that correspond to a user configurable capacity placeholder, and adjust respective sizes of the first cell region and the second cell region at runtime based on the logical block address locations. Other embodiments are disclosed and claimed.

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

Abstract: In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.

Abstract: Aspects of the disclosure relate to controlling access to secure information resources using rotational datasets and dynamically configurable data containers. A computing platform may receive, from a requesting system, a data access request. After authenticating the requesting system, the computing platform may load, using a first data container, first source data from a data track. The computing platform may send the first source data to a second data container. Then, the computing platform may load, using the second data container, second source data from the data track and may produce a first combined dataset. The computing platform may send the first combined dataset to a third data container. Subsequently, the computing platform may load, using the third data container, third source data from the data track and may produce a second combined dataset. Thereafter, the computing platform may send, to the requesting system, the second combined dataset.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a set of memory cells of a source management unit of the memory device to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a first threshold; responsive to determining that the data integrity metric value fails to satisfy the first threshold, determining whether the data integrity metric value satisfies a second threshold that is lower than the first threshold; responsive to determining that the data integrity metric value satisfies the second threshold, causing the memory device to copy data from the source management unit to a destination set of pages of the memory device; and performing a subsequent data integrity check on one or more invalid pages of the source management unit.

Abstract: Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.

Abstract: A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to exemplary embodiments of the present disclosure, the memory system may calibrate a history read bias until a termination condition is satisfied based on a number of error bits generated in a first read operation. The memory system may reduce the overhead incurred in handling errors that occur during a read operation by reducing the number of error bits that can occur during read operation due to non-optimization of the history read bias value.

Abstract: A processing device determines difference error counts that are indicative of relative widths of valleys. Each of the valleys is located between a respective pair of programming distributions of memory cells of the memory device. A program targeting operation is performed on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions. To perform the program targeting operation, a rule from a set of rules is selected based on the difference error counts. The set of rules corresponds to an adjusting of a PV target of a last programming distribution. One or more program verify (PV) targets associated with the programming distributions are adjusted based on the selected rule.

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

Abstract: A system and method for calibrating read threshold voltages includes performing a plurality of read operations, determining to perform a read level tracking method, and performing the read level tracking method. The determining may be based on a temperature change or a bit error rate (BER). The read level tracking method includes determining the BER of an indicative word line, determining an adjusted read threshold level based on the BER, and adjusting read threshold levels according to the adjusted read threshold level.

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

Abstract: To increase the speed of programming of a multi-plane non-volatile memory, it is proposed to accelerate the programming of the last one or more data states for one or more slow planes.

Abstract: A memory device includes memory cells, and a first latch circuit, a second latch circuit, and a third latch circuit, coupled to the memory cells, wherein the first latch circuit is configured to store verification data during a verification operation, the second latch circuit is configured to store failure pattern data during the verification operation, and the third latch circuit is configured to store program data.

Abstract: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes outputting a first command including a request for on-chip valley search (OVS) count data of a memory region of the non-volatile memory device to the non-volatile memory device, wherein the OVS count data includes a first count value and a second count value of a first read voltage and a third count value and a fourth count value of a second read voltage, receiving the OVS count data from the non-volatile memory device, determining a distribution type of the memory region to be a predicted distribution type, from among a plurality of distribution types, based on the OVS count data, and determining a subsequent operation, based on the predicted distribution type.

Abstract: A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.

Abstract: Apparatuses, methods, and systems for storing one data value by programming a first memory cell and a second memory cell are disclosed. The first memory cell and the second memory cell may each be programmed to a first data state, a second data state, or a third data state, and the one data value can correspond to a combination of the first data state, the second data state, or the third data state to which the first memory cell and the second memory cell are programmed, where two combinations of the first data state, the second data state, or the third data state to which the first memory cell is programmable and the first data state, the second data state, or the third data state to which the second memory cell is programmable are ineligible to correspond to the one data value.

Abstract: In a method of reducing reliability degradation of a nonvolatile memory device, the nonvolatile memory device in which initial data having an initial threshold voltage distribution is stored in a plurality of memory cells connected to a plurality of wordlines is provided. Before a first process causing reliability degradation is performed, a first write operation is performed such that first data having a first threshold voltage distribution is stored into memory cells connected to first wordlines. The first wordlines have a degree of reliability degradation less than a reference value. Before the first process is performed, a second write operation is performed such that second data having a second threshold voltage distribution is stored into memory cells connected to second wordlines. The second wordlines have a degree of reliability degradation greater than or equal to the reference value.

Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.

Abstract: Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.

Abstract: A semiconductor memory device includes a command and address generator configured to decode a command to generate an active command, and generate an address applied with the active command as a row address, a control signal generator configured to generate sequence data changing with a random sequence in response to the active command, and generate a random pick signal when the sequence data is equal to previously stored comparison data, and a memory cell array comprising an odd page memory cell array including a plurality of first memory cells and an even page memory cell array including a plurality of second memory cells, and configured to simultaneously perform the active operation and a hidden hammer refresh operation on the selected first and second memory cells in response to the row address when the random pick signal is activated in response to the active command.

Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

Abstract: The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and setting a mark of the address information pointed to by the read command as invalid if an error occurs in the data to be read out, and backing up the address information pointed to by the read command and the mark into a non-volatile memory cell according to a preset rule.

Abstract: Various embodiments enable age tracking of one or more physical memory locations (e.g., physical blocks) of a memory die, which can be from part of a memory device. In particular, various embodiments provide age tracking of one or more physical memory locations of a memory die (e.g., memory integrated circuit (IC)) using one or more aging bins on the memory die, where each aging bin is associated with a different set of physical memory locations of the memory die. By use of an aging bin for a set of physical memory locations, various embodiments can enable a processing device that interacts with a memory die, after the memory die has been subjected to one or more reflow soldering processes, to determine how much the set of physical memory locations have aged after the one or more reflow soldering processes.

Abstract: A method provides the capability to maintain integrity of a data image stored by computing a hash value (“digest”) of the data image and comparing the hash value computed for the data image with a hash value computed for the data image and kept in a non-volatile area of memory. Bit flips in the data image that are a result of memory hardware errors reveal themselves as differences in the digest computed for the data image and the computed digest for the data.

Abstract: A memory stores dummy data including a first data area having more “0” than “1” of a binary logic and a second data area having more “1” than “0” of the binary logic. An ECC processor detects a first error bit number related to the first data area and a second error bit number related to the second data area. A calculator calculates a relative difference of the first error bit number from the second error bit number. A comparator compares the relative difference with a predetermined value. A corrector corrects a read voltage on the basis of a result of comparison by the comparator.

Abstract: An apparatus includes an error read flow component resident on a memory sub-system. The error read flow component can cause performance of a plurality of read recovery operations on a group of memory cells that are programmed or read together, or both. The error read flow component can determine whether a particular read recovery operation invoking the group of memory cells was successful. The error read flow component can further cause a counter corresponding to each of the plurality of read recovery operations to be incremented in response to a determination that the particular read recovery operation invoking the group of memory cells was successful.

Abstract: An integrated driver applied to a voltage converter having a switched capacitor conversion circuit, the integrated driver including: a first die having a first-type power transistor; a second die including at least one second-type power transistor, where a withstand voltage of the first-type power transistor is higher than a withstand voltage of the second-type power transistor; and where the first die and the second die are coupled in series between a high potential terminal and a low potential terminal of the voltage converter, such that the first-type power transistor receives a high voltage signal.

Abstract: A processing device determines a target bit error rate corresponding to a point of a first programming voltage distribution level corresponding to memory cells of a memory sub-system and a second programming voltage distribution corresponding to the memory cells of the memory sub-system. An offset voltage level corresponding to the point at the target bit error rate is selected. A first portion of a first group of the memory cells in the first programming voltage distribution level is programmed at a threshold voltage level to set a first embedded data value. A second portion of a second group of the memory cells in the second programming voltage distribution level is programmed at the threshold voltage level offset by the offset voltage level to set a second embedded data value.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page; responsive to the data state metric satisfying a first threshold criterion, determining a value of a voltage distribution metric associated with the page; and responsive to the voltage distribution metric value satisfying a second threshold criterion, performing a media management operation with respect to a block associated with the page.

Abstract: Provided herein may be a memory device and a memory system having the memory device. The memory system includes a memory device including a plurality of memory blocks, each including chunk blocks, and page buffer blocks respectively coupled to the chunk blocks, and a memory controller configured to, based on chunk block status information indicating whether each of the chunk blocks is one of a pass chunk block and a bad chunk block, control the memory device to perform an operation corresponding to a command on merged pass chunk blocks obtained by merging pass chunk blocks coupled to different page buffer blocks among pass chunk blocks included in memory blocks, each of the memory blocks including both the pass chunk block and the bad chunk block.

Abstract: A nonvolatile memory device includes; a memory cell array including a meta data region storing chip-level information, control logic identifying a target cell in response to a command, machine learning (ML) logic inferring an optimum parameter based on the chip-level information and physical information associated with the target cell applied as inputs to an artificial neural network model, and a buffer memory configured to store weight parameters of the artificial neural network model.

Abstract: According to one embodiment, a semiconductor memory card includes a first pin group which includes a plurality of pins arranged in a line at an end portion on a side of an inserting direction into a connector and part of which is used both in a first and second modes; and a second pin group which includes a plurality of pins including at least two pin pairs for differential signal, is arranged so that a ground is positioned on both sides of each of the pin pairs for differential signal, and is used only in the second mode. In the second mode, among the respective pins configuring the first pin group, any of adjacent two pins are changed to a pin pair for differential clock signal, and a function of remaining pins of the first pin group is stopped.