Error Correction (e.g., Redundancy, Endurance) Patents (Class 365/185.09)
  • Patent number: 11942165
    Abstract: A memory device includes memory cells, and a first latch circuit, a second latch circuit, and a third latch circuit, coupled to the memory cells, wherein the first latch circuit is configured to store verification data during a verification operation, the second latch circuit is configured to store failure pattern data during the verification operation, and the third latch circuit is configured to store program data.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: March 26, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Weijun Wan
  • Patent number: 11934701
    Abstract: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes outputting a first command including a request for on-chip valley search (OVS) count data of a memory region of the non-volatile memory device to the non-volatile memory device, wherein the OVS count data includes a first count value and a second count value of a first read voltage and a third count value and a fourth count value of a second read voltage, receiving the OVS count data from the non-volatile memory device, determining a distribution type of the memory region to be a predicted distribution type, from among a plurality of distribution types, based on the OVS count data, and determining a subsequent operation, based on the predicted distribution type.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woohyun Kang, Youngdeok Seo, Hyuna Kim, Hyunkyo Oh, Donghoo Lim
  • Patent number: 11929127
    Abstract: A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhongguang Xu, Murong Lang, Zhenming Zhou
  • Patent number: 11929121
    Abstract: Apparatuses, methods, and systems for storing one data value by programming a first memory cell and a second memory cell are disclosed. The first memory cell and the second memory cell may each be programmed to a first data state, a second data state, or a third data state, and the one data value can correspond to a combination of the first data state, the second data state, or the third data state to which the first memory cell and the second memory cell are programmed, where two combinations of the first data state, the second data state, or the third data state to which the first memory cell is programmable and the first data state, the second data state, or the third data state to which the second memory cell is programmable are ineligible to correspond to the one data value.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Umberto Di Vincenzo
  • Patent number: 11915770
    Abstract: In a method of reducing reliability degradation of a nonvolatile memory device, the nonvolatile memory device in which initial data having an initial threshold voltage distribution is stored in a plurality of memory cells connected to a plurality of wordlines is provided. Before a first process causing reliability degradation is performed, a first write operation is performed such that first data having a first threshold voltage distribution is stored into memory cells connected to first wordlines. The first wordlines have a degree of reliability degradation less than a reference value. Before the first process is performed, a second write operation is performed such that second data having a second threshold voltage distribution is stored into memory cells connected to second wordlines. The second wordlines have a degree of reliability degradation greater than or equal to the reference value.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: February 27, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minseok Kim, Junyong Park, Doohyun Kim, Ilhan Park
  • Patent number: 11908507
    Abstract: A semiconductor memory device includes a command and address generator configured to decode a command to generate an active command, and generate an address applied with the active command as a row address, a control signal generator configured to generate sequence data changing with a random sequence in response to the active command, and generate a random pick signal when the sequence data is equal to previously stored comparison data, and a memory cell array comprising an odd page memory cell array including a plurality of first memory cells and an even page memory cell array including a plurality of second memory cells, and configured to simultaneously perform the active operation and a hidden hammer refresh operation on the selected first and second memory cells in response to the row address when the random pick signal is activated in response to the active command.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongmin Bang, Seungki Hong
  • Patent number: 11907580
    Abstract: Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Tao Liu, Zhengang Chen, Ting Luo
  • Patent number: 11907560
    Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Joseph Thomas Pawlowski
  • Patent number: 11901033
    Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jooyong Park, Minsu Kim, Daeseok Byeon, Pansuk Kwak
  • Patent number: 11894088
    Abstract: The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and setting a mark of the address information pointed to by the read command as invalid if an error occurs in the data to be read out, and backing up the address information pointed to by the read command and the mark into a non-volatile memory cell according to a preset rule.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shuliang Ning
  • Patent number: 11869607
    Abstract: Various embodiments enable age tracking of one or more physical memory locations (e.g., physical blocks) of a memory die, which can be from part of a memory device. In particular, various embodiments provide age tracking of one or more physical memory locations of a memory die (e.g., memory integrated circuit (IC)) using one or more aging bins on the memory die, where each aging bin is associated with a different set of physical memory locations of the memory die. By use of an aging bin for a set of physical memory locations, various embodiments can enable a processing device that interacts with a memory die, after the memory die has been subjected to one or more reflow soldering processes, to determine how much the set of physical memory locations have aged after the one or more reflow soldering processes.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Falgun G. Trivedi
  • Patent number: 11861012
    Abstract: A method provides the capability to maintain integrity of a data image stored by computing a hash value (“digest”) of the data image and comparing the hash value computed for the data image with a hash value computed for the data image and kept in a non-volatile area of memory. Bit flips in the data image that are a result of memory hardware errors reveal themselves as differences in the digest computed for the data image and the computed digest for the data.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: January 2, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chun-Lien Su
  • Patent number: 11854638
    Abstract: A memory stores dummy data including a first data area having more “0” than “1” of a binary logic and a second data area having more “1” than “0” of the binary logic. An ECC processor detects a first error bit number related to the first data area and a second error bit number related to the second data area. A calculator calculates a relative difference of the first error bit number from the second error bit number. A comparator compares the relative difference with a predetermined value. A corrector corrects a read voltage on the basis of a result of comparison by the comparator.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: December 26, 2023
    Assignee: MEGACHIPS CORPORATION
    Inventors: Shunsuke Nakai, Atsufumi Kawamura, Yasuhisa Marumo, Handa Chen
  • Patent number: 11842787
    Abstract: An apparatus includes an error read flow component resident on a memory sub-system. The error read flow component can cause performance of a plurality of read recovery operations on a group of memory cells that are programmed or read together, or both. The error read flow component can determine whether a particular read recovery operation invoking the group of memory cells was successful. The error read flow component can further cause a counter corresponding to each of the plurality of read recovery operations to be incremented in response to a determination that the particular read recovery operation invoking the group of memory cells was successful.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: December 12, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Seungjune Jeon
  • Patent number: 11824434
    Abstract: An integrated driver applied to a voltage converter having a switched capacitor conversion circuit, the integrated driver including: a first die having a first-type power transistor; a second die including at least one second-type power transistor, where a withstand voltage of the first-type power transistor is higher than a withstand voltage of the second-type power transistor; and where the first die and the second die are coupled in series between a high potential terminal and a low potential terminal of the voltage converter, such that the first-type power transistor receives a high voltage signal.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: November 21, 2023
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Kaiwei Yao, Wang Zhang, Chen Zhao
  • Patent number: 11817152
    Abstract: A processing device determines a target bit error rate corresponding to a point of a first programming voltage distribution level corresponding to memory cells of a memory sub-system and a second programming voltage distribution corresponding to the memory cells of the memory sub-system. An offset voltage level corresponding to the point at the target bit error rate is selected. A first portion of a first group of the memory cells in the first programming voltage distribution level is programmed at a threshold voltage level to set a first embedded data value. A second portion of a second group of the memory cells in the second programming voltage distribution level is programmed at the threshold voltage level offset by the offset voltage level to set a second embedded data value.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: November 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Michael Sheperek, Larry J. Koudele
  • Patent number: 11810631
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page; responsive to the data state metric satisfying a first threshold criterion, determining a value of a voltage distribution metric associated with the page; and responsive to the voltage distribution metric value satisfying a second threshold criterion, performing a media management operation with respect to a block associated with the page.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Michael Sheperek, Christopher M. Smitchger
  • Patent number: 11782646
    Abstract: Provided herein may be a memory device and a memory system having the memory device. The memory system includes a memory device including a plurality of memory blocks, each including chunk blocks, and page buffer blocks respectively coupled to the chunk blocks, and a memory controller configured to, based on chunk block status information indicating whether each of the chunk blocks is one of a pass chunk block and a bad chunk block, control the memory device to perform an operation corresponding to a command on merged pass chunk blocks obtained by merging pass chunk blocks coupled to different page buffer blocks among pass chunk blocks included in memory blocks, each of the memory blocks including both the pass chunk block and the bad chunk block.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: October 10, 2023
    Assignee: SK hynix Inc.
    Inventor: Seung Hyun Chung
  • Patent number: 11763904
    Abstract: A method of adjusting operating conditions includes: a substrate; first conductive layers; a first semiconductor layers facing the first conductive layers; a second semiconductor layer connected to the first semiconductor layers; and an electric charge accumulating layer disposed between the first conductive layers and the first semiconductor layers. At a predetermined timing of a program operation, the second conductive layer which is one of the first conductive layers is supplied with a program voltage or a write pass voltage. The method executes: a first operation that supplies the second conductive layer with the write pass voltage and supplies a third conductive layer which is one of the plurality of first conductive layers with the program voltage; and a second operation that supplies the second conductive layer with a verify voltage and supplies the third conductive layer with a voltage.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: September 19, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinji Suzuki
  • Patent number: 11762563
    Abstract: A system for improving radiation tolerance of memory senses an amount of radiation exposure and, based on the sensed amount of radiation exposure, determines whether to perform one or more techniques for mitigating the effects of the radiation exposure. As an example, the system may perform a data refresh operation by re-writing data that has been corrupted by radiation, or the system may adjust the reference voltage used to read memory cells. In another example, the system may perform a fault repair operation by re-programming cells that have erroneously transitioned from a program state to an erase state. The system may selectively perform different radiation-mitigation techniques in a tiered approach based on the sensed amount of radiation in order to limit the adverse effects of the more invasive techniques.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: September 19, 2023
    Assignee: Board of Trustees of the University of Alabama, for and on behalf of the University of Alabama in Huntsville
    Inventors: Biswajit Ray, Aleksandar Milenkovic
  • Patent number: 11762599
    Abstract: A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Abdelhakim S. Alhussien, Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat
  • Patent number: 11763903
    Abstract: A nonvolatile memory device includes; a memory cell array including a meta data region storing chip-level information, control logic identifying a target cell in response to a command, machine learning (ML) logic inferring an optimum parameter based on the chip-level information and physical information associated with the target cell applied as inputs to an artificial neural network model, and a buffer memory configured to store weight parameters of the artificial neural network model.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: September 19, 2023
    Inventors: Sehwan Park, Jinyoung Kim, Youngdeok Seo, Dongmin Shin
  • Patent number: 11755410
    Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Ching-Huang Wang, Yi-Chun Shih, Meng-Chun Shih, C. Y. Wang
  • Patent number: 11740959
    Abstract: An initial level of sensing voltage is set based on one or more characteristics of the segment of the memory device. A count for operational cycles for a segment of a memory device is set. Responsive to determining that a number of operational cycles performed on the segment of the memory device has reached the set count of operational cycles, the sensing voltage is varied with respect to the initial level of sensing voltage. The sensing voltage is adjusted to a new level based on wearing of the segment of the memory device during the number of operational cycles performed on the segment of the memory device.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Zhongguang Xu, Murong Lang, Zhenming Zhou
  • Patent number: 11735273
    Abstract: Apparatus and methods for recovery after an abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: August 22, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohsen Purahmad, Chao-Han Cheng, Dongxiang Liao, Bo Lei
  • Patent number: 11734106
    Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: August 22, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern
  • Patent number: 11726874
    Abstract: A request to retrieve user data stored at a memory device is received and a first error control operation associated with the user data is performed. An indication of a failure of the first error control operation is received, and in response, a subset of system data stored at the memory device is identified. A second error control operation is performed on the subset of the system data to retrieve the subset of the system data stored at the memory device, and the user data is read by using the subset of the system data retrieved based on the performing of the second error control operation.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Rayaprolu, Sivagnanam Parthasarathy, Sampath K. Ratnam, Peter Feeley, Kishore Kumar Muchherla
  • Patent number: 11682467
    Abstract: A nonvolatile memory device includes a plurality of memory blocks and a control logic circuit configured to perform a first page on-chip valley search (OVS) operation on memory cells connected to one wordline of a memory block selected in response to an address, among the plurality of memory blocks, in response to a first read command. The control logic circuit is further configured to change a read level of at least one state using detection information of the first page OVS operation, and to perform a second page read operation on the memory cells using the changed read level in response to a second read command.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: June 20, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinyoung Kim, Sehwan Park, Youngdeok Seo, Ilhan Park
  • Patent number: 11681580
    Abstract: A semiconductor system includes a controller configured to, in a write operation, output write data and a write error code through at least any one of input/output lines, and in a read operation, receive read data and a read error code through at least any one of the input/output lines and detect a failure of the input/output lines depending on whether the read data is error-corrected; and a semiconductor device configured to, in the write operation, correct an error of the write data based on the write error code, store the error-corrected write data and store the write error code, and in the read operation, correct an error of the write data based on the write error code stored in the write operation, output the error-corrected write data as the read data, and output the write error code stored in the write operation, as the read error code.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: June 20, 2023
    Assignee: SK hynix Inc.
    Inventor: Choung Ki Song
  • Patent number: 11675530
    Abstract: Provided is an operating method of a memory controller which comprises receiving first decision data of M bits from a memory device, where M is a natural number; converting the M-bit first decision data into second decision data of N bits, where N is a natural number less than M; and attempting a first decoding using the second decision data.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: June 13, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wi Jik Lee, Dong-Min Shin, Young Jun Hwang, Hong Rak Son
  • Patent number: 11669250
    Abstract: Techniques manage a wear degree of a storage system. Such techniques involve: receiving respectively, for multiple storage devices in the storage system, multiple access histories of the multiple storage devices in a previous time period; determining respectively multiple wear increments of the multiple storage devices at a future time point based on the multiple access histories of the multiple storage devices; acquiring a wear balance degree of the storage system at the future time point based on the multiple wear increments of the multiple storage devices at the future time point; and migrating data among the multiple storage devices in response to determining that the wear balance degree satisfies a preset condition. Accordingly, it is possible to determine the wear degree of each storage device in the storage system more accurately and ensure that the wear degree of each storage device is in a balanced state.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: June 6, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Chi Chen, Huijuan Fan
  • Patent number: 11657863
    Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 11646070
    Abstract: Methods, systems, and devices for memory cell sensing using an averaged reference voltage are described. A memory device may generate the averaged reference voltage that is specific to operating conditions or characteristics. The averaged reference voltage thus may track variations in cell use and cell characteristics. The memory device may generate the averaged reference voltage by shorting together reference nodes to determine an average of values associated with the reference nodes. The reference nodes may be associated with a codeword, which may store values corresponding to the reference nodes. The codeword may be balanced or nearly balanced to include equal or nearly equal quantities of different logic values.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: May 9, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Patent number: 11637122
    Abstract: A semiconductor device includes a first gate stack structure and a second gate stack structure, which face each other; channel patterns extending in a first direction to penetrate the first gate stack structure and the second gate stack structure; memory patterns extending along outer walls of the channel patterns; and a source contact structure disposed between the first gate stack structure and the second gate stack structure, wherein the source contact structure includes a vertical part extending in the first direction and horizontal protrusion parts protruding toward a sidewall of the first gate stack structure and a sidewall of the second gate stack structure from both sides of the vertical part.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 25, 2023
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 11636908
    Abstract: A memory device to calibrate voltages used to read a group of memory cells. For example, the memory device measures first signal and noise characteristics of a group of memory cells by reading the group of memory cells at first test voltages that are separated from each other by a first voltage interval. An estimate of a read level of the group of memory cells is determined based on the first signal and noise characteristics. The memory device then measures second signal and noise characteristics of the group of memory cells by reading the group of memory cells at second test voltages that are separated from each other by a second voltage interval that is smaller than the first voltage interval. An optimized read voltage for the read level is computed from the second signal and noise characteristics.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: April 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Walter Di Francesco, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Jeffrey Scott McNeil, Jr.
  • Patent number: 11630593
    Abstract: Reading data stored at a free block of a storage device is read prior to allocating the free block for storage of data. A determination as to whether a number of bit flips of the data stored at the free block is below a threshold is made. The free block is added to a pool of active free blocks to be allocated for the storage of data upon determining that the number of bit flips of the data stored at the free block is below the threshold.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: April 18, 2023
    Assignee: Pure Storage, Inc.
    Inventors: Shuyi Shao, Yuhong Mao, Peter E. Kirkpatrick
  • Patent number: 11630721
    Abstract: A memory system includes a controller configured to transfer first data for a program operation, and a memory device configured to perform an error check operation for determining whether second data received from the controller are equal to the first data and the program operation for storing the first data.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: April 18, 2023
    Assignee: SK hynix Inc.
    Inventor: Tae-Hoon Kim
  • Patent number: 11626176
    Abstract: The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. The embodiments comprise a system and method for receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and when the current word is not the last physical word in the sector, changing a next index bit.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: April 11, 2023
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Guangming Lin, Xiaozhou Qian, Xiao Yan Pi, Vipin Tiwari, Zhenlin Ding
  • Patent number: 11626185
    Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Ryun Kim, Yoon-Na Oh, Hyung-Jin Kim, Hui-Kap Yang, Jang-Woo Ryu
  • Patent number: 11615029
    Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jiangang Wu, Qisong Lin, Jung Sheng Hoei, Yunqiu Wan, Ashutosh Malshe, Peng-Cheng Chen
  • Patent number: 11610639
    Abstract: A reading method for a non-volatile memory device, includes performing a normal read operation using a default read level in response to a first read command; and performing a read operation using a multiple on-chip valley search (OVS) sensing operation in response to a second read command, when read data read in the normal read operation are uncorrectable.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: March 21, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eunhyang Park, Jinyoung Kim, Jisang Lee, Sehwan Park, Ilhan Park
  • Patent number: 11605441
    Abstract: A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 14, 2023
    Inventors: Sunghye Cho, Kiheung Kim, Sungrae Kim, Junhyung Kim, Kijun Lee, Myungkyu Lee, Changyong Lee, Sanguhn Cha
  • Patent number: 11581048
    Abstract: A method and solid-state storage device are disclosed for validating erasure status of data blocks on a solid-state drive. The method includes assigning each data block of a plurality of data blocks on the solid-state drive, a block identifier and an erasure status, the block identifier being system data, user data, or unmapped data, and the erasure status being erased or not erased.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: February 14, 2023
    Assignee: CIGENT TECHNOLOGY, INC.
    Inventor: Tony Edward Fessel
  • Patent number: 11574700
    Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: February 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jooyong Park, Minsu Kim, Daeseok Byeon, Pansuk Kwak
  • Patent number: 11537484
    Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sri Rama Namala, Lu Tong, Kristopher Kopel, Sheng-Huang Lee, Chang H. Siau
  • Patent number: 11527287
    Abstract: Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Karthik Sarpatwari, Nevil N. Gajera, Lingming Yang, John F. Schreck
  • Patent number: 11521703
    Abstract: Various implementations described herein are related to a method for identifying multi-bank memory architecture having multiple banks including a first bank and a second bank. The method may receive a faulty row address having a faulty bank selection bit, and also, the method may select the first bank or the second bank for row redundancy operations based on the faulty bank selection bit.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: December 6, 2022
    Assignee: Arm Limited
    Inventors: Amandeep Kaur, Andy Wangkun Chen, Penaka Phani Goberu, Khushal Gelda
  • Patent number: 11507281
    Abstract: A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: November 22, 2022
    Assignee: Futurewei Technologies, Inc.
    Inventor: Yiren Huang
  • Patent number: 11507294
    Abstract: A method of managing a storage appliance is provided. The method includes (a) partitioning a cache of the storage appliance at least into multiple regions dedicated to respective storage drives of a plurality of storage drives of the storage appliance; (b) in response to the storage appliance receiving a first storage command directed to a first storage drive, allocating space for fulfillment of the first storage command within the region of cache dedicated to the first storage drive; (c) in response to the storage appliance receiving a second storage command directed to a second storage drive, allocating space for fulfillment of the second storage command within the region of cache dedicated to the second storage drive; and (d) fulfilling, by the storage appliance, the first and second storage commands by moving data to and from their respective allocated space in the cache. An apparatus, system, and computer program product for performing a similar method are also provided.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: November 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Amitai Alkalay, Boris Glimcher
  • Patent number: 11495311
    Abstract: A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks of the block. Erase verify is performed between erase voltage pulses for NAND strings in the outer sub-blocks while skipping erase verify for NAND strings in the inner sub-blocks. Performing erase verify between erase voltage pulses for NAND strings in the inner sub-blocks is started at a predetermined number of erase voltage pulses after the NAND strings in the outer sub-blocks successfully erase verify.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: November 8, 2022
    Assignee: SanDisk Technologies LLC
    Inventor: Kazuhiko Sanada