Error Correction (e.g., Redundancy, Endurance) Patents (Class 365/185.09)
  • Patent number: 10482948
    Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device includes a latch selectably coupled to a column of the memory cells and configured to store a data value moved from the sensing circuitry. The memory device includes a controller configured to direct movement of the data value from the sensing circuitry to the latch.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 10474528
    Abstract: A system and method pertains to operating non-volatile memory systems. Technology disclosed herein efficiently uses memory available in non-volatile storage devices in a non-volatile memory system. In some aspects, non-volatile storage devices enforce a redundancy coding stripe across the non-volatile storage devices formed from chunks of data having internal addresses assigned in a coordinated scheme across the storage devices. In some aspects, non-volatile storage devices enforce a redundancy coding stripe across the non-volatile storage devices at the same internal addresses in the respective non-volatile storage devices.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: November 12, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vladislav Bolkhovitin, Warren Fritz Kruger, Brian W O'Krafka, Sanjay Subbarao
  • Patent number: 10468112
    Abstract: A first bit of an aggressor codeword is written to a first memory cell, wherein the write to the first memory cell disturbs a set of one or more victim codewords by contributing to a cumulative effect that can change a value of a victim codeword in the set based on proximity to the first memory cell. A second bit of the aggressor codeword is written to a second memory cell, wherein the write to the second memory cell disturbs at most the one or more victim codewords of the set by contributing to the cumulative effect based on proximity to the second memory cell. The second memory cell is separated from the first memory cell by at least a third memory cell, wherein the third memory cell stores a first bit of a second codeword.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: November 5, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Justin Eno
  • Patent number: 10467091
    Abstract: An error correcting method of a memory system includes: reading read data and an error correction code from a plurality of memory chips; correcting an error of the read data using the error correction code; temporarily storing the read data and the error correction code in a buffer when the correcting of the error fails; writing a certain input test pattern in the plurality of memory chips, reading an output test pattern written in the plurality of memory chips, and detecting a fail chip in which a chipkill occurs; recorrecting, based on a location of the detected fail chip, the error of the read data stored in the buffer using the error correction code stored in the buffer; and rewriting error-corrected read data and the error correction code in the plurality of memory chips.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 5, 2019
    Assignee: SK hynix Inc.
    Inventors: Jong-Hyun Park, Sung-Eun Lee, Ja-Hyun Koo, Seung-Gyu Jeong
  • Patent number: 10445173
    Abstract: A method for programming a non-volatile memory in a programming operation is provided. The non-volatile memory has a number of cells and each of part of the cells stores data having at least 2 bits at least corresponding to a first page and a second page. The first programming-verifying operation including programming the first page and verifying whether the first page is successfully programmed is performed. When a first original fail-bit number for the first page is more than a predetermined fail-bit value, a second programming-verifying operation to the first page is performed to obtain a first over-counting fail-bit number for the first page and reduce the first original fail-bit number by the first over-counting fail-bit number. When the reduced first original fail-bit number is not more than the predetermined fail-bit value, the first page is set as successfully programmed.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 15, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Chang Huang, Kun-Tse Lee
  • Patent number: 10446256
    Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: October 15, 2019
    Assignee: Rambus Inc.
    Inventors: Adrian E. Ong, Fan Ho
  • Patent number: 10445199
    Abstract: The present disclosure generally relates to methods for managing bad pages in storage devices. When a page is bad or faulty, a spare page is used to store the data because the bad or faulty page is unreliable for data storage. When the time comes to read the data from the bad page or write data onto the page, there needs to be some direction to the spare page. The bad or faulty page may contain a pointer to direct to the location of the spare page or metadata containing directions to the location of the spare page. A hash function may be used to calculate that the stored data in the bad or faulty page is incorrect and, once decoded, provide direction to the spare page. By using pointers, metadata or hash functions, additional data tables are unnecessary and data storage is more efficient.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 15, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Kiran Kumar Gunnam
  • Patent number: 10438685
    Abstract: A memory device includes a first fail address register that stores a fail address, an input address register that stores an input address, a data comparison circuit that compares write data to be stored in a memory cell corresponding to the input address with read data read from the memory cell, an address comparison circuit that compares the fail address and the input address, and a second fail address register that stores bits of the fail address in parallel based on a first comparison result of the write data with the read data and a second comparison result of the fail address with the input address.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyungkyu Kim, Sang-Hoon Jung
  • Patent number: 10431321
    Abstract: A transconductance test method implemented in a flash memory device detects memory cells with low transconductance and provides an output identifying memory cells, if any, having been classified as having a low transconductance (low gm). In some embodiments, the transconductance test method implements multi-step testing using a pair of gate bias levels for each test step. Accurate detection of memory cells with low transconductance can be realized.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: October 1, 2019
    Assignee: Integrated Silicon Solutions, (Cayman) Inc.
    Inventor: Sung Jin Yoo
  • Patent number: 10417091
    Abstract: Data is read from memory cells in the memory device. The read data is transferred over a link to a memory controller that is external of the memory device. While the transferring of the read data is ongoing, error detection of the read data is performed inside the memory device using an error correction code.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: September 17, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Gregg B. Lesartre
  • Patent number: 10417082
    Abstract: A memory system comprising: a memory device including a plurality of memory dies each having a plurality of the memory blocks; and a controller suitable for performing a command operation to the memory dies, wherein the memory device comprises means for performing an error check operation to a first data provided from the controller to store the first data the memory device.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Tae-Hoon Kim
  • Patent number: 10410732
    Abstract: Systems and methods are described for predicting potential failures in flash memory devices by probing for memory cells with marginal programming characteristics. A method includes receiving a write request. The method also includes applying a predetermined number of programming pulses to a plurality of memory cells within a block of a flash memory device. The method also includes applying a verify pulse to each respective one of the plurality of memory cells. The method also includes storing programming status of the plurality of memory cells into a set of latches. The method also includes determining, based on the stored programming status, a total number of memory cells within the block that fall outside of one or more predetermined expected ranges. The method also includes identifying the block as a block in risk when the total number of memory cells satisfies a predetermined risk threshold.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: September 10, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Tomer Tzvi Eliash, Arthur Shulkin, James Yin Tom, Eran Sharon
  • Patent number: 10403375
    Abstract: A storage device includes a plurality of nonvolatile memory devices each exchanging data by using a data strobe signal and a data signal, and a storage controller categorizing the plurality of nonvolatile memory devices into a plurality of groups and performing training in units of the plurality of groups. The storage controller performs data training on a first nonvolatile memory device selected in a first group of the plurality of groups and sets a delay of a data signal of a second nonvolatile memory device included in the first group by using a result value of the data training for the first nonvolatile memory device.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chulseung Lee, Soon Suk Hwang, ChoongEui Lee
  • Patent number: 10395750
    Abstract: A dynamic random access memory (DRAM) device includes a plurality of bank groups of first storage cells, each bank group arranged as a plurality of banks, each bank arranged as a plurality of rows, and each row including a plurality of dynamic storage cells. The DRAM device further includes a post-package repair (PPR) storage array arranged as a plurality of entries, wherein the DRAM device is configured to map a first row failure in a first bank group to a first entry of the PPR storage array, and to map a second row failure in a second bank group to a second entry of the PPR storage array.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: August 27, 2019
    Assignee: Dell Products, LP
    Inventors: Stuart Allen Berke, Vadhiraj Sankaranarayanan
  • Patent number: 10372355
    Abstract: Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jianmin Huang, Kulachet Tanpairoj, Harish Singidi, Ting Luo
  • Patent number: 10360981
    Abstract: A semiconductor memory device includes a plurality of blocks of memory cells, including first, second, and third blocks of a first group of blocks and fourth fifth and sixth blocks of a second group of blocks, a plurality of word lines for each of the blocks, a first decode circuit for the first group, and a second decode circuit for the second group. When the first block is selected, the first decode circuit transfers a first voltage to the word lines of the first block, transfers a second voltage lower than the first voltage to the word lines of the second block, and causes the word lines of the third block to go into an electrically floating state, and the second decode circuit causes the words lines of the fourth block, the fifth block, and the sixth block into the electrically floating state.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: July 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noriyasu Kumazaki, Koji Kato
  • Patent number: 10360989
    Abstract: A method of operating an electronic device includes: generating a fuse read output based on reading a fuse cell at a predetermined data location in a fuse array, wherein the predetermined data location is configured to store predetermined data pattern; comparing the fuse read output to the predetermined data pattern; and generating a read-enable trigger based on the fuse read output matching the predetermined data pattern, wherein the read-enable trigger is for reading content stored in the fuse array and for broadcasting the content to circuits within the electronic device.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Raghukiran Sreeramaneni, John E. Riley, Yu-Feng Chen
  • Patent number: 10360947
    Abstract: Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tyson M. Stichka, Preston Thomson, Scott Anthony Stoller, Christopher Bueb, Jianmin Huang, Kulachet Tanpairoj, Harish Singidi
  • Patent number: 10347356
    Abstract: Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Patent number: 10340947
    Abstract: In a method of controlling reclaim of a nonvolatile memory device including a plurality of memory blocks, wherein each of the memory blocks includes a plurality of pages, a recovery read operation is performed on first data using an optimal read voltage determined based on the first data, when the first data includes errors which are not correctable, wherein the first data is read from a first page of a first memory block of the memory blocks, and, when the errors of the first data are corrected after the recovery read operation is performed, whether to perform a reclaim of the first page is determined based on threshold voltage distributions of memory cells of the first page, wherein the memory cells are disposed in a region of interest adjacent to the optimal read voltage.
    Type: Grant
    Filed: April 23, 2017
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shin-Ho Oh, Woo-Hyun Kang, Min-Kyu Kim
  • Patent number: 10325669
    Abstract: An error information storage circuit configured to write information stored in a plurality of fuse sets to a plurality of fuse latch sets of a core block and/or to write test data to the plurality of fuse latch sets. The test data is internally generated depending on a fuse clock signal, and the test data has values which cause opposite levels to be written in adjacent latches of the plurality of fuse latch sets.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong Sam Kim
  • Patent number: 10325658
    Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-Sang Lee
  • Patent number: 10318181
    Abstract: Methods, systems and computer-readable storage media for increasing spare space in a storage subsystem including a flash memory, extending a lifetime of the storage subsystem to achieve a stored selected minimum lifetime based at least in part as a result of the increasing spare space, and identifying at least one aspect associated with the lifetime of the storage subsystem. The storage subsystem may include compressed data stored in the flash memory.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak
  • Patent number: 10319439
    Abstract: A resistive processing unit includes a first analog memory element, a second analog memory element connected in series with the first analog memory element, and a control circuit coupled to the first analog memory element and the second analog memory element. The control circuit is configured to read a synaptic weight value of the resistive processing unit by collecting a differential current from the first analog memory element and the second analog memory element on at least one of a read column line and a read row line coupled to a terminal coupling the first analog memory element and the second analog memory element.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yulong Li, Paul M. Solomon
  • Patent number: 10310734
    Abstract: Tier access mode for three dimensional (3D) memory devices. A 3D memory device has multiple memory elements that are each addressable by a two dimensional address including a wordline address and a bitline address, and a third dimension with a sub-block selector indicating one of multiple portions of a tier of memory elements in the memory device. A memory controller generates a memory access command, such as read or program, to access a first portion of the memory and sends the command to the memory device. The memory device charges a first wordline and a first sub-block in response to receiving the command. For a consecutive access command to access a second portion of the memory, the memory device maintains the first wordline charged without discharging it, and charges a second sub-block selector in response to the consecutive command.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventor: Toru Tanzawa
  • Patent number: 10297337
    Abstract: Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: May 21, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Wanfang Tsai, Hung-Szu Lin, Yi-Fang Chen
  • Patent number: 10275307
    Abstract: A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: April 30, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen
  • Patent number: 10204007
    Abstract: The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory. The systems and methods may include a soft information correction circuit that is operable to receive soft information corresponding to information accessed from a block of memory cells, and modify the soft information based upon a variance of the soft information and a median of the soft information to create corrected soft information, the corrected soft information being used to mitigate inter-cell interference in the block of memory cells.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: February 12, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Fan Zhang, Shu Li, Jun Xiao, Haitao Xia
  • Patent number: 10198194
    Abstract: Placing data within a storage device, including: receiving, by a storage device, information describing an expected longevity of data stored on the storage device; determining, by the storage device, a location for storing the data in dependence upon the expected longevity of the data; adjusting a garbage collection schedule in dependence upon data placement; and providing, to a storage array controller, garbage collection statistics.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: February 5, 2019
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Ethan Miller
  • Patent number: 10185658
    Abstract: Systems, methods and/or devices are used for efficient implementation of optimized host-based garbage collection strategies using xcopy and arrays of flash devices. In one aspect, a method of managing a storage system having one or more storage devices includes a host-based garbage collection operation that includes identifying two or more logical stripes in accordance with data storage information stored at the host system, and enabling a process of coalescing valid data in the two or more logical stripes. Further, the use of an internal copy operation (e.g., xcopy), allows the host-based garbage collection operation to occur without transferring data back to the host, thus minimizing the number of I/O operations between the host and storage devices. Additionally, use of the host-based garbage collection operation allows more sophisticated garbage collection algorithms (e.g., matching the current workload) to be used, and ensures that multiple logical stripes are available to write data.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: January 22, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Brian W. O'Krafka, Vladislav Bolkhovitin, Vivek Shivhare
  • Patent number: 10181971
    Abstract: A method for processing a signal modulated with a variable carrier frequency includes calculating a coefficient for demodulation of the signal. The method also includes demodulating the signal by calculating discrete intermediate values utilizing the coefficient for a predefined maximum number of steps and calculating the signal with the aid of the intermediate values of the coefficient. The value of the coefficient is respectively calculated on the basis of carrier frequencies for each step.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: January 15, 2019
    Assignee: CONTINENTAL TEVES AG & CO. OHG
    Inventor: Heinrich Acker
  • Patent number: 10180797
    Abstract: Provided are a computer program product, system and method for determining adjustments to the spare space in a storage device unavailable to a user based on a current consumption profile of a storage device. A current write amplification is based on storage writes to a media at a storage device and host writes from a host to the storage device. An adjustment to the current write amplification is determined to produce an adjusted write amplification based on an estimated lifespan of the storage device, a maximum storage writes for the storage device, and the storage writes at the storage device since the storage device was powered-on. A determination is made to an adjustment to spare space based on the adjusted write amplification. The spare space and the free space available to the user are reconfigured to adjust the spare space by the determined adjustment to the spare space.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: January 15, 2019
    Assignee: INTEL CORPORATION
    Inventor: Knut S. Grimsrud
  • Patent number: 10170202
    Abstract: A memory system includes a semiconductor storage device that includes a plurality of blocks, and a controller configured to designate a block of the semiconductor storage device as a partial bad block if, after performing a write operation on the block, status information read from the semiconductor storage device indicates that the write operation failed, and read data that is returned when a read operation is performed on data written pursuant to the write operation has errors that are correctable. The controller is configured to manage a partial bad block differently from a bad block.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: January 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Iwai, Hideaki Tsunashima, Akio Okazaki
  • Patent number: 10169128
    Abstract: Resistive switching memory architectures disclosed herein are capable of achieving fast read/write times and, particularly in the case of multi-bank parallel processing, executing many read or write operations per second. Because resistive switching memory is not guaranteed to be error free, resistive memory controllers can be programmed for error management when paired with such memory architectures. To reduce error management overhead, a dedicated error pin is provided to mitigate or avoid the need for a status read in conjunction with each read or write operation issued to a memory device. A status read can be implemented in response to an error signal on the dedicated error pin, but otherwise can be avoided.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 1, 2019
    Assignee: CROSSBAR, INC.
    Inventors: Mehdi Asnaashari, Robin Sarno, Ruchirkumar D. Shah
  • Patent number: 10162538
    Abstract: A data storage device includes a controller and a memory. The memory is coupled to the controller. The memory includes storage elements coupled to bit lines. The controller is configured to access bit line integrity data corresponding to a region of the memory, the bit line integrity data indicating a number of bit lines. The controller is also configured to store data related to a memory operation threshold based on the number of bit lines.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 25, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mark Shlick, Refael Ben-Rubi, Uri Shir, Ahiad Turgeman, Uri Peltz
  • Patent number: 10157097
    Abstract: Techniques for codeword decoding are described. In an example, a system accesses information about a block of a storage device of the system. The block includes data lines and redundant lines. The data lines are available to store data and include a bad data line that is unreliable for data storage. The redundant lines include a redundant line that replaces the bad data line, and a free redundant line that remains available after replacement of all bad data lines from the data lines. The information includes an identifier of the bad data line and an identifier of the free redundant line. The system accesses a codeword stored in the block. A portion of the codeword is stored in the free redundant line. The system decodes the codeword based on the identifier of the bad data line and the identifier of the free redundant line.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: December 18, 2018
    Assignee: SK Hynix Inc.
    Inventors: Fan Zhang, June Lee, Chenrong Xiong, Aman Bhatia, Naveen Kumar, David Pignatelli
  • Patent number: 10146604
    Abstract: Utilities for use in actively detecting the occurrence of bad blocks in NAND flash storage devices and diagnosing the devices as faulty at some point before complete failure of the devices (e.g., before a number of allowable bad blocks has been reached) to allow a corresponding service processor to continue to write to available blocks for a period of time until a replacement NAND flash device can be identified. The utilities may also be utilized to predict the future occurrence of bad blocks in NAND flash devices, such as during the “burn-in” process of the devices (e.g., which tests the quality of the NAND flash device before being placed into service to weed out devices with defects).
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: December 4, 2018
    Assignee: Oracle International Corporation
    Inventors: David Rudy, George Kechriotis, Patrick O'Grady, James Gemmell
  • Patent number: 10134474
    Abstract: An apparatus includes a first plane of memory cells including an associated first buffer, a second plane of memory cells including an associated second buffer. The apparatus also includes a controller configured to transfer data corresponding to a first memory state the first buffer and transfer data corresponding to a second memory state to the second buffer. The apparatus also includes state machine configured to apply program pulses to the first and second planes of memory cells. The apparatus also includes read/write circuitry configured to independently confirm that the first and second planes of memory cells have reached the first and second memory states.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: November 20, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Yi-Chieh Chen
  • Patent number: 10135464
    Abstract: A method for decoding low-density parity check (LDPC) codes, includes computing an initial syndrome of an initial output, obtaining an initial number of unsatisfied checks based on the computed initial syndrome, and when the initial number of unsatisfied checks is greater than zero, computing a reliability value with a parity check, performing a bit flip operation, computing a subsequent syndrome of a subsequent output, and ending decoding when a number of unsatisfied checks obtained based on the computed subsequent syndrome is equal to zero.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: November 20, 2018
    Assignee: SK Hynix Inc.
    Inventors: Chung-Li Wang, Lingqi Zeng, Yi-Min Lin
  • Patent number: 10127984
    Abstract: Embodiments include a method of operating a storage device including a flash memory, comprising: calculating a reuse period of a selected memory block in the flash memory; determining a set of wordlines of the selected memory block for writing data based on the reuse period of the selected memory block; and writing the data into the set of wordlines.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangkwon Moon, Heewon Lee, Seongjun Ahn
  • Patent number: 10120585
    Abstract: An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled with the plurality of memory devices, configured to determine a range of read reference voltages having a plurality of read reference voltages, the read reference voltages achieving a minimal rBER; calculate an optimal read reference voltage in accordance with at least the range of read reference voltages; achieve a rBER in accordance with at least the optimal read reference voltage; and execute error correction process with at least the optimal read reference voltage.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: November 6, 2018
    Assignee: SK Hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Yu Cai, HyungSeok Kim, June Lee, David Pignatelli
  • Patent number: 10115458
    Abstract: A memory system includes a plurality of non-volatile memories, one or more temperature sensors each of which is disposed in or adjacent to one of the non-volatile memories, and a controller. The controller is configured to maintain a temperature increase amount and a reference temperature for each of the non-volatile memories, and select one of the non-volatile memories having a pending command as a next memory to be accessed based on a current temperature, the temperature increase amount, and the reference temperature of the selected non-volatile memory, and access the selected non-volatile memory to perform the pending command.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: October 30, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Ge Wang
  • Patent number: 10109329
    Abstract: A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: October 23, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marcella Carissimi, Marco Pasotti, Fabio De Santis
  • Patent number: 10102059
    Abstract: A method for operating a data storage device including a plurality of pages includes performing a read operation to a first page of the nonvolatile memory device according to a read voltage; adjusting the read voltage based on a number of error bits in the read-out data according to the read voltage; performing the read operation to the first page according to the adjusted read voltage; and performing a re-program operation to the first page based on a number of on cells as a result of the read operation according to the adjusted read voltage.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: October 16, 2018
    Assignee: SK Hynix Inc.
    Inventor: Ji Man Hong
  • Patent number: 10096366
    Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: October 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Akamine, Masanobu Shirakawa, Tokumasa Hara
  • Patent number: 10078548
    Abstract: According to one embodiment, a memory controller controlling write to and read from a 3D NAND flash memory including a plurality of blocks, one block being constituted by a plurality of pages stacked in a depth direction includes a frame generator that generates frame data including an error detecting code or an error correcting code, and a frame divider that divides the frame data to generate a plurality of divided frames including a first divided frame and a second divided frame. The first divided frame and the second divided frame are written into different pages from one another.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: September 18, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takuya Haga
  • Patent number: 10073741
    Abstract: In one aspect of the present disclosure, there is provided a memory system comprising a memory device configured to temporarily store data therein, the data being loaded thereon for programming a selected page among multiple pages, the memory device further configured to program the selected page using the data; and a controller configured to send the data to the memory device, wherein the controller is further configured to control the memory device such that, in a failure event of the program for the selected page, the memory device re-programs another page using the data temporarily stored therein without receipt of further data from the controller.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventors: Won Sun Park, Mi Ock Chi
  • Patent number: 10073634
    Abstract: A method includes storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data in a volatile buffer and then writing the buffered data to the analog memory cells while overwriting at least some of the data in the volatile buffer with success indications. Upon detecting a failure in writing the buffered data to the analog memory cells, recovered data is produced by reading both the volatile buffer and the analog memory cells, assigning reliability metrics to respective bits of the recovered data depending on whether the bits were read from the volatile buffer or from the analog memory cells, and applying ECC decoding to the recovered data using the reliability metrics. The recovered data is re-programmed.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: September 11, 2018
    Assignee: Apple Inc.
    Inventors: Shai Ojalvo, Eyal Gurgi, Yoav Kasorla
  • Patent number: 10074441
    Abstract: A memory device includes a pass/fail check circuit configured to compare the number of memory cells, which are verified as being a program fail based on a result of verifying program operations of a first group of memory cells of a plurality of memory cells, with a first reference bit number, and to check whether the first group of memory cells is a pass or fail and a control circuit configured to control the pass/fail check circuit to recheck whether the first group of memory cells is the pass or fail based on a second reference bit number smaller than the first reference bit number when the first group of memory cells is found to be the pass based on a result of a pass/fail check operation of the pass/fail check circuit.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventors: Byoung-Sung You, Jae-Hyoung Ko
  • Patent number: 10067827
    Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: September 4, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels