Logic Connection (e.g., Nand String) Patents (Class 365/185.17)
  • Patent number: 11004515
    Abstract: There may be provided a controller including an erase count monitor and a command generator. The erase count monitor may store and update an erase count value for the memory block. The erase count value may indicate a number of times an erase operation is performed for the memory block. The command generator may be configured to generate, based on the erase count value, a set command for setting a first select transistor among the select transistors to which an erase operation voltage is to be applied during the erase operation of the memory block, and a second select transistor among the select transistors to be floated when the erase operation voltage is to be applied to the first select transistor.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventor: Hae Soo Kim
  • Patent number: 11004518
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 11, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
  • Patent number: 11004516
    Abstract: Apparatus including an array of memory cells comprising a plurality of strings of series-connected memory cells, a plurality of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of series-connected memory cells, and a controller configured during an erase operation of the plurality of strings of series-connected memory cells to apply a first voltage level to a node connected to an end of a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells, and apply a second voltage level to a particular access line of the plurality of access lines concurrently with applying the first voltage level to the node, wherein the second voltage level has a magnitude greater than the first voltage level, and is lower than the first voltage level.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jun Xu
  • Patent number: 10997097
    Abstract: A memory device includes a memory controller to transmit or receive input/output (“I/O”) data via an I/O signal, as well as transmit command data, address data, or parameter data via another signal in parallel with transmitting or receiving the I/O data. The memory device also includes a memory module communicably coupled to the memory controller. The memory module receives the command data, address data, or parameter data from the memory controller to perform an operation.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: May 4, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sneha Bhatia, Vinayak Ghatawade
  • Patent number: 10998049
    Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 4, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Wenzhe Wei, Hongtao Liu, Kaikai You, Da Li, Ying Huang, Yali Song, Dejia Huang
  • Patent number: 10998062
    Abstract: A memory system includes a plurality of blocks of memory blocks, each including a plurality of memory cells. The method for programming the memory system includes during a program process, performing a first program operation to program a first memory block, waiting for a delay time after the first program operation is completed, after waiting for the delay time, performing an all-level threshold voltage test to determine if threshold voltages of the first memory block are greater than corresponding threshold voltages, and performing a second program operation to program the first memory block according to a result of the all-level threshold voltage test.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: May 4, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Haibo Li, Qiang Tang
  • Patent number: 10998063
    Abstract: An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: May 4, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qiang Tang, Xiang Fu
  • Patent number: 10998041
    Abstract: In a read scan operation, a first read level window is scanned for a first candidate read level that activates the fewest number of memory cells in relation to other candidate read levels within that window. A second read level window for a second candidate read level is then configured based on a correlation between at least one of the two adjacent memory states and one or more other adjacent memory states associated with the second read level window. The second read level window is scanned for a second candidate read level that activates the fewest number of memory cells, or results in the fewest bit errors, in relation to other candidate read levels within the second read level window. Next, a read operation is configured to use the first candidate read level and the second candidate read level.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: May 4, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dudy Avraham, Alex Bazarsky, Rotem Feinblat, David Rozman
  • Patent number: 10991713
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Keisuke Nakatsuka, Fumitaka Arai, Shinya Arai, Yasuhiro Uchiyama
  • Patent number: 10991402
    Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: April 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akio Sugahara, Yoshikazu Harada, Shoichiro Hashimoto
  • Patent number: 10991441
    Abstract: A flash device endurance test method is provided. A flash device to be tested, which has a plurality of memory cells, includes multiple ports with the same and different test conditions. The method includes connecting the ports of the same test condition to the same pulse generation unit, and connecting the ports of different test conditions to different pulse generation units; generating by all of the pulse generation units, synchronous pulse voltage signals of N cycles, wherein one time of erasing-writing of the flash device is considered to be one of the cycles; and testing threshold voltages of erasing and writing states in each cycle.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 27, 2021
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Hongliang Du
  • Patent number: 10985179
    Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yi Hu, Merri L. Carlson, Anilkumar Chandolu, Indra V. Chary, David Daycock, Harsh Narendrakumar Jain, Matthew J. King, Jian Li, Brett D. Lowe, Prakash Rau Mokhna Rau, Lifang Xu
  • Patent number: 10978165
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes a memory cell and a controller having a memory storing a write parameter used in a write operation to the memory cell. The controller instructs the non-volatile semiconductor memory to perform the write operation to the memory cell using the write parameter, receives, from the non-volatile semiconductor memory, a result of checking of the write parameter which is obtained in the write operation and updates the write parameter stored in the memory on the basis of the result of checking of the write parameter.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: April 13, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Masanobu Shirakawa
  • Patent number: 10978152
    Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 13, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rajdeep Gautam, Hardwell Chibvongodze, Ken Oowada
  • Patent number: 10978153
    Abstract: An operation method for a 3D NAND flash includes writing data into a WLn layer of the plurality of wordline layers of an unselect bit line of the plurality of bit lines in a write operation; and applying a first pass voltage on at least a first WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines and applying a second pass voltage on at least a second WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines; wherein the first pass voltage is lower than the second pass voltage to reduce a difference of channel potential between the WLn layer and the at least a first WL layer when a pre-pulse phase is removed from a verify phase.
    Type: Grant
    Filed: June 21, 2020
    Date of Patent: April 13, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Hongtao Liu, Song Min Jiang, Dejia Huang, Ying Huang, Wenzhe Wei
  • Patent number: 10971238
    Abstract: Three-dimensional semiconductor memory devices are provided. A three-dimensional semiconductor memory device includes a plurality of word line blocks including a plurality of cell strings that are connected in parallel between a bit line and a common source line. Each of the cell strings includes a plurality of memory cell transistors that are stacked on a substrate in a vertical direction, a plurality of ground selection transistors that are connected in series between the plurality of memory cell transistors and the substrate, and a string selection transistor that is between the plurality of memory cell transistors and the bit line. In each of the cell strings, at least one of the plurality of ground selection transistors has a first threshold voltage, and remaining ones of the ground selection transistors have a second threshold voltage different from the first threshold voltage. Related methods of operating three-dimensional semiconductor memory devices are also provided.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 6, 2021
    Inventors: Kohji Kanamori, Yongseok Kim, Kyunghwan Lee, Junhee Lim
  • Patent number: 10971231
    Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 6, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rajdeep Gautam, Hardwell Chibvongodze, Ken Oowada
  • Patent number: 10957403
    Abstract: A semiconductor device includes a first current circuit, a first resistor, a second resistor, a second current circuit, and a third resistor. The first current circuit is configured to output a first current to a first node using a first voltage supplied thereto. The first resistor is connected to the first node. The second resistor has a first end connected to a second node that is at a same voltage level as the first node and a second end. The second current circuit is configured to output a second current to a third node using a second voltage, which is higher than the first voltage, supplied thereto. The third resistor is connected between the second end of the second resistor and the third node.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: March 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoko Deguchi, Masahiro Yoshihara, Yoshihiko Kamata, Takuyo Kodama
  • Patent number: 10950316
    Abstract: Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
  • Patent number: 10950309
    Abstract: Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shigekazu Yamada, Tomoharu Tanaka
  • Patent number: 10942796
    Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Ashutosh Malshe, Violante Moschiano, Peter Feeley, Gary F. Besinga, Sampath K. Ratnam, Walter Di-Francesco, Renato C. Padilla, Jr., Yun Li, Kishore Kumar Muchherla
  • Patent number: 10937490
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: March 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Patent number: 10930356
    Abstract: The memory controller may include a command generator generating and outputting first and second read commands to a memory device so that respective first and second read operations are performed using a first read voltage, a calculator receiving first and second read data in response to the read commands, comparing the first and second read data each other, and calculating a number of first inverted cells and a number of second inverted cells based on a result of the comparing, each of the first inverted cells having a bit value that inverted from a first bit value to a second bit value, and each of the second inverted cells having a bit value that inverted from the second bit value to the first bit value, and a read voltage determiner changing the first read voltage depending on the number of first inverted cells and the number of second inverted cells.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Jiman Hong
  • Patent number: 10916558
    Abstract: NOR flash memory that includes three-dimensional memory cells is provided. In the NOR flash memory of the present disclosure, one memory cell includes one memory transistor and one selection transistor. A common source 5 is formed over a silicon substrate 9, and an active region 3 extending in a vertical direction to electrically connect to the common source 5 is formed. A control gate 4 of the memory transistor and a selection gate line 2 of the selection transistor are formed to surround a side portion of the active region 3, and a top portion of the active region 3 is electrically connected to a bit line 1.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 9, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Riichiro Shirota
  • Patent number: 10910059
    Abstract: According to the present embodiment, a nonvolatile semiconductor memory device includes a memory string group including k stacked memory strings, each of the memory strings including a plurality of nonvolatile memory cells connected in series, a selection transistor group including k selection transistors, each of the k selection transistors corresponding to each of the k memory strings respectively, the selection transistor group divided into n selection transistor sub-groups, each of the n selection transistor sub-groups including k/n selection transistors, n bit lines arranged in parallel to each of the k memory strings, and n bit line contacts arranged perpendicularly, each of the n bit line contacts connected to each of the n bit lines, respectively, each of the n bit line contacts connected to the k/n selection transistors belonging to the each of the n selection transistor sub-group respectively.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hidehiro Shiga
  • Patent number: 10910045
    Abstract: A storage device includes a memory device including a memory cell array and a page buffer group coupled to the memory cell array, and a memory controller configured to store a plurality of cache data chunks to be sequentially programmed, and configured to input a next cache data chunk corresponding to a next program sequence to the page buffer group, when programming of Least Significant Bit (LSB) data of a cache data chunk among the plurality of cache data chunks is completed.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Joo Young Lee, Hoe Seung Jung
  • Patent number: 10910310
    Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Eric H. Freeman, Michael A. Smith
  • Patent number: 10896734
    Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device to program a selected physical page of the semiconductor memory device. The method may include performing a plurality of program loops. Each of the program loops may include: applying a bit line voltage based on data input to a page buffer of the semiconductor memory device; applying a two-step program pulse to a word line coupled to the selected physical page; performing a program verify operation on the selected physical page using a double verify scheme; and determining a bit line voltage to be applied in a subsequent program loop based on a result of the program verify operation.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: January 19, 2021
    Assignee: SK hynix Inc.
    Inventor: In Gon Yang
  • Patent number: 10892016
    Abstract: A method to operate a 3D semiconductor charge trap memory device, the method comprising; executing a memory set-up operation, wherein said memory set-up operation comprises a preload of a plurality of memory cells followed by a partial erase; and then executing a memory operation on said memory cells, wherein each memory cell of said plurality of memory cells comprises a charge trap layer, wherein said memory operation comprises first writing a first memory state by loading a charge into said charge trap layer, and then second writing a second memory state by removing said charge to a partially erased state. Various 3D devices, processing flows and methods are also disclosed.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 12, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky
  • Patent number: 10873483
    Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: December 22, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kensuke Yamamoto, Kosuke Yanagidaira
  • Patent number: 10867678
    Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a memory stack disposed above the peripheral device and including a plurality of conductor/dielectric layer pairs, and a plurality of memory strings. Each of the memory strings extends vertically through the memory stack and includes a drain select gate and a source select gate above the drain select gate. Edges of the conductor/dielectric layer pairs in a staircase structure of the memory stack along a vertical direction away from the substrate are staggered laterally toward the memory strings.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 15, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jun Chen, Jifeng Zhu, Zhenyu Lu, Yushi Hu, Jin Wen Dong, Lan Yao
  • Patent number: 10861510
    Abstract: A majority voting processing device performs majority voting on respective bits of information data piece including r-number of bits (r is an integer of 2 or greater). The device includes a memory including a plurality of memory element groups each including r-number of memory elements that store data for the corresponding r-number of bits, respectively, the plurality of memory element groups each being provide for one address. A memory access unit writes each bit of the information data piece in k-number (k is an odd number of 3 or greater) of the memory elements in the memory element group corresponding to one address, and reads out the k-number of bits written in the k-number of the memory elements corresponding to that one address. A majority voter that performs majority voting on the k-number of bits read out from the memory by the memory access unit.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: December 8, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Nobukazu Murata
  • Patent number: 10854293
    Abstract: Methods of operating a memory include activating a respective memory cell of each string of series-connected memory cells of a plurality of strings of series-connected memory cells, selectively activating a target memory cell of a selected string of series-connected memory cells of the plurality of strings of series-connected memory cells depending upon its data state, and deactivating a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Toru Tanzawa, Han Zhao
  • Patent number: 10854260
    Abstract: The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device a magnetic memory component and a current selector component coupled to the magnetic memory component. The current selector component includes a first transistor having a first gate with a corresponding first threshold voltage. The first transistor comprises a charge storage layer configured to selectively store charge so as to adjust a current through the first transistor. The memory device further includes control circuitry configured to determine a bit error rate of the magnetic memory component and adjust a charge stored in the charge storage layer based on the determined bit error rate.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 1, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Gian Sharma, Amitay Levi
  • Patent number: 10854300
    Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: December 1, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Vinh Diep, Zhengyi Zhang
  • Patent number: 10854288
    Abstract: A semiconductor memory apparatus includes an access line control circuit. The access line control circuit applies a selected bias voltage to a selected access line coupled with a target memory cell and applies a first unselected bias voltage to an unselected access line adjacent to the selected access line. A second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 1, 2020
    Assignee: SK hynix Inc.
    Inventor: Jin Su Park
  • Patent number: 10854304
    Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include performing a sense operation on a particular memory cell of a first string of series-connected memory cells selectively connected to a first data line, applying a first voltage level to the access line for a second memory cell of the first string, applying a second voltage level higher than the first voltage level to the access line for the particular memory cell, applying a third voltage level to the first data line concurrently with applying the first voltage level and concurrently with applying the second voltage level, and applying a fourth voltage level higher than the third voltage level to a second data line selectively connected to a second string of series-connected memory cells concurrently with applying the third voltage level to the first data line.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jun Xu, Yingda Dong
  • Patent number: 10847540
    Abstract: A 3D memory device, the device including: a first horizontal bit-line; a second horizontal bit-line disposed above the first horizontal bit-line, where the first horizontal bit-line and the second horizontal bit-line function as a source or a drain for a plurality of parallel vertically-oriented memory transistors, where the first horizontal bit-line and the second horizontal bit-line are self-aligned being formed following the same lithography step; and conductive memory control lines, where a first portion of the conductive memory control lines are disposed at least partially directly underneath the plurality of parallel vertically-oriented memory transistors, and where a second portion of the conductive memory control lines are disposed at least partially directly above the plurality of parallel vertically-oriented memory transistors.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: November 24, 2020
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Patent number: 10847233
    Abstract: Memory devices including a controller configured to cause the memory device to apply a positive first voltage level to a first data line selectively connected to a first string of series-connected memory cells while applying a second voltage level, higher than the first voltage level, to a second data line selectively connected to a second string of series-connected memory cells; while applying the first voltage level to the first data line and applying the second voltage level to the second data line, applying a third voltage level to a particular access line coupled to a memory cell of a first string of series-connected memory cells selected for programming, wherein a differential between the third voltage level and the first voltage level is configured to increase a threshold voltage of the memory cell selected for programming, as well as other apparatus containing similar memory devices.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Yijie Zhao, Krishna Parat
  • Patent number: 10839910
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Won-Taeck Jung
  • Patent number: 10839908
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takashi Kobayashi, Yoichi Minemura, Eietsu Takahashi, Masaki Kondo, Daisuke Hagishima
  • Patent number: 10840183
    Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: November 17, 2020
    Inventors: Seok-Jung Yun, Sung-Hun Lee, Jee-Hoon Han, Yong-Won Chung, Seong Soon Cho
  • Patent number: 10839914
    Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 17, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, Inc.
    Inventors: Zhenlei Z. Shen, Nian Niles Yang, Gautham Reddy
  • Patent number: 10839923
    Abstract: Non-volatile, high performance memory devices balance speed and reliability, which can include channel boosting to reduce data error rates in the memory cells. Vertical NAND strings exhibit greater program disturb (errors) the higher the wordline is on the string. The present disclosure applies a boosted bit line voltage or an increased precharge time when the programming reaches a level (wordline number) where it has been determined that errors due to program disturb may be an issue. The boost to the bit line may occur after a stored wordline value or based on a calculated number of errors at a previous wordline. In an example, the bit line stays the same as the prior world line programming operation until the likely program disturb is determined.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: November 17, 2020
    Assignee: SanDisk Technologies LLC
    Inventor: Xiang Yang
  • Patent number: 10833112
    Abstract: An image sensor includes a first transfer gate formed over a substrate, and including a first projection; a second transfer gate formed over the substrate, neighboring the first transfer gate, and including a second projection; and a floating diffusion formed in the substrate, and partially overlapping with the first transfer gate and the second transfer gate, wherein the first projection and the second projection face each other.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 10, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung-Kun Park, Hye-Won Mun
  • Patent number: 10832785
    Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: November 10, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
  • Patent number: 10833089
    Abstract: An embodiment may include a method of forming an integrated circuit. The method may include forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers. Each of the first pair of vertically stacked transistors are of the same type and are connected in series. The method may include forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers. The second pair of transistors are a different type than the first pair of vertically stacked transistors. The method may include forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
  • Patent number: 10832777
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: November 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiro Shiino, Eietsu Takahashi
  • Patent number: 10825525
    Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Luigi Pascucci, Paolo Rolandi
  • Patent number: 10811431
    Abstract: A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 20, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang