Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

Abstract: A semiconductor storage device includes: a substrate layer; and a stacked body that is provided on the substrate layer. The semiconductor storage device includes a columnar portion that includes a semiconductor body extending within the stacked body in a stacking direction. The semiconductor storage device includes: an insulating layer provided on the plurality of terrace portions; and a plurality of columnar bodies extending in a first direction and provided within the insulating layer. The semiconductor storage device includes slit portions that split the stacked body into a plurality of string units. Each of the columnar bodies adjacent to each of the slit portions has a core film, the semiconductor body, a tunnel insulating film, and a block insulating film formed in sequence from a shaft center side to an outer periphery side of the columnar body, and the columnar body does not have the charge storage portion.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.

Abstract: A memory system separately programs memory cells connected by a common word line to multiple sets of data states with the set of data states having higher threshold voltage data states being programmed before the set of data states having lower threshold voltage data states. The memory system also separately programs memory cells connected by an adjacent word line to the multiple sets of data states such that memory cells connected by the adjacent word line are programmed to higher data states after memory cells connected by the common word line are programmed to higher data states and prior to memory cells connected by the common word line are programmed to lower data states.

Abstract: A semiconductor device includes: a substrate extending in a first direction and a second direction intersecting with the first direction; a plurality of input/output pads disposed at one side of the substrate; a first circuit adjacent to the input/output pads in the first direction; a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit; a first memory cell array overlapping the first circuit; a second memory cell array overlapping the second circuit; first metal source patterns overlapping the first memory cell array and being spaced apart from each other in the second direction; and a second metal source pattern overlapping the second memory cell array and formed to have a width wider than a width of each of the first metal source patterns in the second direction.

Abstract: Apparatuses and techniques are described for detecting a defect in a memory cell array during program operations. A defect can be detected by comparing the programming speed of memory cells connected to different word lines, for one or more programmed data states. The comparison can involve adjacent word lines in a block, or word lines in different blocks and planes. The comparison involves comparing two word lines in terms of a number of program-verify loops used to reach the programmed data states or to transition between programmed data states. If a program loop delta is not within an allowable range for one or more of the programmed data states, it can be concluded that a defect is present. The block which has the slower programming word line can be identified as a bad block.

Abstract: A semiconductor memory device of embodiments includes: a substrate; a memory pillar; first to sixth conductive layers provided above the substrate; first to sixth memory cells formed between the first to sixth conductive layers and the memory pillar, respectively; and a control circuit. The control circuit applies a first voltage to the first, second, a sixth conductive layer and applies a second voltage to the third, fifth conductive layer, then applies a third voltage to the first conductive layer, applies a fourth voltage to the sixth conductive layer, and applies a fifth voltage to the second conductive layer, and then applies a sixth voltage to the first conductive layer, applies a seventh voltage to the sixth conductive layer, and applies an eighth voltage lower than the fifth voltage to the second conductive layer.

Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a first NAND string including a first channel corresponding to a first cell to be inhibited to program, and a controller configured to control a word line driver and a bit line driver to do the following operations: prior to applying a program voltage to a selected word line, charging a first bit line electrically coupling with the first channel to a first voltage level for charging the first channel to the first voltage level, charging an array common source electrically coupling with the first bit line for further charging the first channel to a second voltage level higher than the first voltage level, and cutting off the electrical coupling between the first bit line and the first channel for preparing to apply the program voltage to the selected word line.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2N levels, where N is an integer greater than 1. The level corresponds to one of 2N pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a row of target memory cells, such that each target memory cell is programmed into one of K intermediate levels based on the corresponding piece of N-bits data, wherein 2N-1<K<2N. The peripheral circuit is also configured to program, in a second pass after the first pass, the row of target memory cells, such that each target memory cell is programmed into one of the 2N levels based on the corresponding piece of N-bits data.

Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells connected to word lines, peripheral circuits configured to generate operation voltages to be applied to the word lines, and control logic configured to control the peripheral circuits in response to a program command, a read command, or an erase command. The peripheral circuits include a voltage generator that adjusts a section of threshold voltage distributions of memory cells to be programmed among the memory cells, according to a distance between the word lines.

Abstract: A semiconductor storage device includes: a plurality of first memory cells; a word line connected to gates of the first memory cells; a voltage generation circuit configured to generate voltage to be supplied to the word line on the basis of a set value; and a control unit configured to execute a write sequence that includes a plurality of loops, each loop including a program operation to increase a threshold voltage of at least part of the first memory cells to thereby write data to the first memory cells and a verify operation to verify the data written to the first memory cells. The voltage generation circuit generates voltage to be supplied to the word line at start of the verify operation on the basis of a first set value, and the control unit adjusts the first set value in accordance with progress of the write sequence.

Abstract: Described are systems and methods for performing memory programming operations in the overwrite mode. An example memory device includes: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: responsive to identifying a first data item to be stored by a portion of the memory array, causing a first memory programming operation to be performed to program, to a first target threshold voltage, a set of memory cells included by the portion of the memory array; and responsive to identifying a second data item to be stored by the portion of the memory array, causing a second memory programming operation to be performed to program the set of memory cells to a second target threshold voltage exceeding the first target threshold voltage.

Abstract: A memory system includes a memory device with a memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: A memory device can include a nonvolatile memory (NVM) cell array, data path circuits, coupled between the NVM cell array and an output of the device, that are configured to enable access to the NVM cell array via a plurality of bit lines. A first charge pump can generate a first voltage supply. A second charge pump can generate a second voltage supply. Switch circuits are configured to, in a first mode, couple the first voltage supply to data path circuits, and in a second mode, couple the second voltage supply to the data path circuits. The first charge pump, the second charge pump, the switch circuits, the data path circuits and the NVM cell array are formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Abstract: In a method of programming in a nonvolatile memory device including a memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, wherein the peripheral circuit region is vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory block in the memory cell region including a plurality of stacks disposed in a vertical direction is provided where the memory block includes cell strings each of which includes memory cells connected in series in the vertical direction between a source line and each of bitlines. A plurality of intermediate switching transistors disposed in a boundary portion between two adjacent stacks in the vertical direction is provided, where the intermediate switching transistors perform a switching operation to control electrical connection of the cell strings, respectively.

Abstract: According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m?1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.

Abstract: An in-memory computing device includes in some examples a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a nine-transistor current-based SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switching transistor, which is controlled by input signals on an input line, to an output line associates with the column of memory cells the memory cell is in. The current source includes a switching transistor controlled by the state of the six-transistor SRAM cell, and a current regulating transistor adapted to generate a current at a level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line is increased by a factor of 2 in each successive column of the memory cells.

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

Abstract: According to one embodiment, a semiconductor memory device includes: first and second select transistors; first and second select gate lines; first and second interconnects; first and second memory cell transistors; and first and second word lines. In a write operation, after execution of a verify operation, in a period in which the second select transistor is ON, a voltage of the first word line changes from a first voltage to a second voltage and a voltage of the second word line changes from a third voltage applied in the verify operation to a fourth voltage, and after the voltage of the first word line changes to the second voltage and the voltage of the second word line changes to the fourth voltage, a voltage of the second select gate line changes from a fifth voltage to a sixth voltage.

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material.

Abstract: Technology for two-sided adjacent memory cell interference mitigation in a non-volatile storage system is disclosed. During reading of target memory cells, the storage system applies a suitable magnitude read pass voltage to a first unselected word line adjacent to a target word line to compensate for interference from adjacent cells on the first unselected word line while applying a suitable magnitude read reference voltage to the target word line to compensate for interference from adjacent cells on a second unselected word line on the other side of the target word line. The read pass voltage may compensate for interference due to charge being added to when programming cells on the first unselected word line after programming the target cells. The read reference voltage may compensate for interference due to charge movement near the target cells that results from charge stored in the cells on the second unselected word line.

Abstract: A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.

Abstract: A storage system caches, in volatile memory, data read from non-volatile memory. After detecting an uncorrectable error in the data cached in the volatile memory, the storage system replaces the cached data with data re-read from the non-volatile memory and updated to reflect any changes made to the data after it was stored in the non-volatile memory. The storage system can also analyze a pattern in data adjacent to the uncorrectable error and predict corrected data based on the pattern.

Abstract: A semiconductor structure includes a substrate, an insulating layer disposed on the substrate, an active layer disposed on the insulating layer, a first semiconductor device formed in a first device region of the active layer, a charge trap structure through the active layer and surrounding the first device region, and a charge trap layer between the insulating layer and the substrate and extending laterally to underlie the first device region and the charge trap structure.

Abstract: An analog CAM and an operation method thereof are provided. The analog CAM includes a matching line, an analog CAM cell and a sense amplifier. Each of the at least one analog CAM includes a first floating gate device having a N type channel and a second floating gate device having a P type channel. A match range is set through programming the first floating gate device and the second floating gate device. The sense amplifier is connected to the matching line. If an inputting signal is within the match range, a voltage of the matching line is pulled down to be equal to or lower than a predetermined level. The sense amplifier outputs a match result if the voltage of the matching line is pulled down to a predetermined level.

Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.

Abstract: Systems and methods for providing memory access commands to memory circuitry using a multi-clock cycle memory command protocol is described. A command decoder (or controller) of the memory circuitry may efficiently receive a memory access request (or a memory command) provided using multiple clock cycles. For example, the command decoder may receive a header and a first portion of address bits of target memory cells of the memory command in a first clock cycle and a second portion of the address bits of the target memory cells in a subsequent clock cycle. Accordingly, the memory circuitry may receive a memory command provided over multiple clock cycles with one header. Such memory commands may efficiently include a high number of address bits received using input circuitry of the memory circuitry.

Abstract: The present technology relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit configured to perform a program operation on a selected memory block among the plurality of memory blocks, and control logic configured to control the peripheral circuits to perform a retention acceleration operation including boosting a channel of a plurality of cell strings included in the selected memory block between a program voltage applying operation and a program verify operation during the program operation.

Abstract: An apparatus is described. The apparatus includes a non volatile memory chip. The non volatile memory chip includes an interface to receive access commands, a three dimensional array of non volatile storage cells, and, a controller to orchestrate removal of charge in a column of stacked ones of the non volatile storage cells after a verification process that determined whether or not a particular cell along the column was programmed with a correct charge amount. The removal of the charge pushes the charge out of the column by changing respective word line potentials along a particular direction along the column. Cells that are coupled to the column are programmed in the particular direction. Disturbance of neighboring cells during programming is less along the particular direction than a direction opposite that of the particular direction.

Abstract: Algorithms for fast data retrieval, low power consumption in a 3D or planar non-volatile array of memory cells, connected between an accessible drain string and a floating, not directly accessible, source string, in a NOR-logic type of architecture, are presented.

Abstract: A memory device includes: a plurality of memory cells grouped into a plurality of planes; page buffer groups corresponding to respective ones of the plurality of planes, the page buffer groups including a plurality of page buffer circuits, each of the plurality of page buffer circuits including cache latches which are configured to receive data to be stored in memory cells in the plurality of planes; and control logic for controlling the page buffer groups to simultaneously initialize cache latches corresponding to at least two planes, among the cache latches, in response to a multi-plane program command, wherein the multi-plane program command instructs a multi-plane program operation of simultaneously storing data in plural planes among the plurality of planes.

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: A sensitive amplifier and a storage device are provided, and the sensitive amplifier includes: a voltage clamp circuit which provides a stable reading voltage for the storage unit; a power switch circuit which cuts off power supply for the voltage clamp circuit when the voltage clamp circuit is not operating; a discharge circuit which discharges the voltage clamp circuit before the voltage clamp circuit operates; a pre-charge circuit which pre-charges the voltage clamp circuit when the voltage clamp circuit starts operating; and a current comparison circuit which is connected to an output of the voltage clamp circuit, compares the reading current with a reference current, and outputs a comparison result.

Abstract: A semiconductor memory device includes a memory block with string units including a plurality of memory strings of memory cell transistors connected in series. Word lines are connected memory cell transistors in a same row and bit lines are respectively connected to one of the memory strings in each string unit. The bit lines are divided into different groups. A control circuit performs erasing on of the memory cell transistors in the memory block. The control circuit executes the erase verification on only a subset of memory strings in each string unit of the memory block rather than all memory strings.

Abstract: A non-volatile memory device receives a read command and an address from a controller, and performs a data recovery read operation in response to the read command. In the data recovery read operation, an operation of obtaining aggressor group information from a memory cell connected to a word line adjacent to a word line selected according to the address, and an operation of recovering data corresponding to the obtained aggressor group information in a memory cell connected to the word line selected according to the address, are repeatedly performed on each of a plurality of aggressor groups.

Abstract: In certain aspects, a memory device includes an array of memory cells including a plurality of rows of memory cells, a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform an erase operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line. To perform the erase operation, the peripheral circuit is configured to discharge an unselected word line coupled to an unselected row of memory cells of the plurality of rows of memory cells from an initial voltage to a discharge voltage in a first time period, and float the unselected word line in a second time period after the first time period.

Abstract: A non-volatile memory includes a plurality of blocks and a controller. Each of the plurality of blocks includes a plurality of pages, and each of the plurality of pages includes a plurality of storage units. The controller is configured to perform: receiving an erase command for a target block of the plurality of blocks; executing a read operation on each page of the target block; and executing a first erase operation to apply word line voltages to the plurality of pages, where the word line voltages are determined by a read result of the read operation of each page. An operation method of a non-volatile memory and an electronic device are also provided.

Abstract: Implementations of the present disclosure provide 3D memory devices and methods for operating the 3D memory devices. In an example, a 3D memory device includes a plurality of memory layers and a dummy memory layer between the plurality of memory layers and a NAND memory string extending through the memory layers and the dummy memory layer. The NAND memory string includes a source, a drain, and a plurality of memory cells at intersections with the plurality of memory layers and between the source and the drain. The 3D memory device also includes a peripheral circuit configured to erase the plurality of memory cells. To erase the plurality of memory cells, the peripheral circuit includes a word line driving circuit configured to apply a positive bias voltage on the dummy memory layer.

Abstract: Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

Abstract: A semiconductor memory device comprises a first word line coupled to first and second memory cell transistors, first and second bit lines, and a controller. In a first program loop, a controller applies a first voltage to first and second bit lines in a program operation, and classifies the first and second memory cell transistors into first and second groups by applying a first verify voltage to the first word line in a verify operation. In a program operation of each of program loops that are executed after the first program loop, the controller applies the first voltage to the first bit line when a verification of the first memory cell transistor has not been passed, and applies a second voltage to the second bit line when a verification of the second memory cell transistor has not been passed.

Abstract: A multi-layer vector-matrix multiplication (VMM) apparatus is provided. The multi-layer VMM apparatus includes a three-dimensional (3D) NAND flash structure having multiple transistor array layers each includes a number of transistors configured to store a respective weight matrix and a number of word lines configured to receive respective selection voltages corresponding to a respective input vector. Accordingly, each of the transistor array layers can perform a respective VMM operation by multiplying the respective selection voltages with the respective weight matrix. Thus, by providing the respective selection voltages to each of the multiple transistor array layers in a sequential order, it may be possible to carry out a multi-layer VMM operation in the 3D NAND flash structure with reduced footprint, thus making it possible to support a deep neural network (DNN) via such advanced techniques as in-memory computing.

Abstract: Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction.

Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

Abstract: A variety of applications can include memory devices designed to provide stabilization of selector devices in a memory array of the memory device. A selector stabilizer pulse can be applied to a selector device of a string of the memory array and to a memory cell of multiple memory cells of the string with the memory cell being adjacent to the selector device in the string. The selector stabilizer pulse can be applied directly following an erase operation to the string to stabilize the threshold voltage of the selector device. The selector stabilizer pulse can be applied as part of the erase algorithm of the memory device. Additional devices, systems, and methods are discussed.

Abstract: A memory circuit includes a memory array and a control circuit. A first column of the memory array includes a select line, first and second bit lines, a first subset of memory cells coupled to the select line and the first bit line, and a second subset of memory cells coupled to the select line and the second bit line. The control circuit is configured to simultaneously activate each of the select line and the first bit line and, during a period in which the select line and first bit line are simultaneously activated, activate a first plurality of word lines, each word line of the first plurality of word lines being coupled to a memory cell of the first subset of memory cells.

Abstract: A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.

Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.