Logic Connection (e.g., Nand String) Patents (Class 365/185.17)
  • Patent number: 10658039
    Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: May 19, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Iwai, Hiroshi Nakamura
  • Patent number: 10650894
    Abstract: A semiconductor memory device of an embodiment includes a substrate, a first conductive layer provided above the substrate, the first conductive layer being spaced apart from the substrate in a first direction, and the first conductive layer being provided parallel to a substrate plane, a second conductive layer provided adjacent to the first conductive layer in a second direction intersecting the first direction, the second conductive layer being provided parallel to the substrate plane, a third conductive layer provided above the first conductive layer, the third conductive layer being spaced apart from the first conductive layer in the first direction, and the third conductive layer being provided parallel to the substrate plane, a fourth conductive layer provided above the second conductive layer, the fourth conductive layer being spaced apart from the second conductive layer in the first direction, and the fourth conductive layer being provided parallel to the substrate plane, a fifth conductive layer pr
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya Kato, Yusuke Shimada, Fumitaka Arai
  • Patent number: 10643723
    Abstract: At a time of writing first data to a first memory cell, second data which is written later to an adjacent second memory cell is referred to, and when a value of the second data corresponds to a first threshold level, a verify voltage is set to a first verify voltage, and when the value of the second data corresponds to a second threshold level greater than the first threshold level, the verify voltage is set to a second verify voltage smaller than the first verify voltage.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: May 5, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yusuke Umezawa
  • Patent number: 10643684
    Abstract: A memory controller executes a non-homogeneous bitline biasing program verify operation on bitlines of a memory array, and a homogeneous bitline biasing program verify operation on the bitlines. A count of bitlines responding in a particular way to each type of biasing is used to ascertain the integrity of the memory array.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: May 5, 2020
    Assignee: SanDisk Technologies LLC
    Inventor: Xiang Yang
  • Patent number: 10644011
    Abstract: A non-volatile memory having memory cells is provided. The memory cell includes a source region and a drain region, a select gate, a dummy select gate, a floating gate, an erase gate, and a control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the select gate and the source region, and a top portion of the floating gate has corners in symmetry. The height of the floating gate is lower than the height of the select gate. The erase gate is provided on the source region and covers the corner at the side of the source. The control gate is disposed on the erase gate and the floating gate.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: May 5, 2020
    Assignee: IoTMemory Technology Inc.
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Yu-Ming Cheng
  • Patent number: 10643703
    Abstract: A method for controlling a memory system, including a controller chip and a non-volatile memory chip which includes a calibration control circuit, a first output buffer, and a first resistance element, includes receiving a read command from the controller, setting a ready/busy signal to a busy state based on the read command, executing a calibration operation which controls an impedance of the first output buffer based on the read command, setting the ready/busy signal to a ready state, and sending data to the control chip in response to the read command. The calibration control circuit calibrates the impedance of the first output buffer circuit by using the first resistance element within a period in which the ready/busy signal is the busy state.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: May 5, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Inoue, Daisuke Arizono
  • Patent number: 10643705
    Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit. The approach can be extended from binary weights to multi-bit weight values by use of multiple differential memory cells for a weight.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 5, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Won Ho Choi, Pi-Feng Chiu, Wen Ma, Martin Lueker-Boden
  • Patent number: 10636468
    Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Higashi, Yuuichi Kamimuta, Tsunehiro Ino
  • Patent number: 10629266
    Abstract: Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to a plurality of memory cells selected for programming during a programming operation, concurrently enabling for programming each memory cell of the plurality of memory cells selected for programming while applying the programming pulse, applying a subsequent programming pulse having a plurality of different voltage levels to the selected access line, and, for each group of memory cells of a plurality of groups of memory cells of the plurality of memory cells selected for programming, enabling that group of memory cells for programming while the subsequent programming pulse has a corresponding voltage level of the plurality of different voltage levels.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: April 21, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Aaron S. Yip
  • Patent number: 10629256
    Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: April 21, 2020
    Assignee: R&D 3 LLC
    Inventor: Ravindraraj Ramaraju
  • Patent number: 10629272
    Abstract: Techniques for reducing read disturb of memory cells. A discharge process reduces a channel gradient in a NAND string by using a two-step ramp up of adjacent word lines of the selected word line. The voltages of the adjacent word lines can be provided at an intermediate level while the selected word line voltage is spiked up to a read pass voltage and then decreased. The voltages of the adjacent word lines can then be increased from the intermediate level to a read pass voltage and maintained at that level during the sensing of the memory cells. The voltage of the selected word line is decreased from a read pass voltage to a positive control gate read voltage at the end of the discharge process.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 21, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Hong-Yan Chen, Wei Zhao
  • Patent number: 10614862
    Abstract: An assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Ugo Russo
  • Patent number: 10607704
    Abstract: Provided herein is a semiconductor memory device exhibiting improved operating speed and a method of operating the semiconductor memory device. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a read operation on the memory cell array. The control logic may control an operation of the peripheral circuit. The control logic may control the peripheral circuit to perform a repair column masking operation on a selected memory block of the plurality of memory blocks, perform a first test operation on first drain select transistors included in the selected memory block, perform the first test operation on second drain select transistors different from the first drain select transistors while a result of the repair column masking operation remains.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventor: Sang Sik Kim
  • Patent number: 10593408
    Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: June-Hong Park, Ki-Whan Song, Bong-Soon Lim, Su-Chang Jeon, Jin-Young Kim, Chang-Yeon Yu, Dong-Kyo Shim, Seong-Jin Kim
  • Patent number: 10573384
    Abstract: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: February 25, 2020
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventor: Jun Liu
  • Patent number: 10573388
    Abstract: A non-volatile storage system comprises memory cells arranged in groups of memory cells that include programmable select gates and one or more control circuits in communication with the memory cells. The one or more control circuits configured to identify a select gate that needs to be programmed and program the select gate identified to be programmed if a temperature at the non-volatile memory cells is greater than a minimum temperature and defer programming of the select gate identified to be programmed until the temperature at the non-volatile memory cells is greater than the minimum temperature. In some embodiments, the one or more control circuits are configured to perform dummy memory operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not high enough.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: February 25, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mahim Raj Gupta, Mohsen Purahmad, Bo Lei, Joanna Lai, Xiying Costa
  • Patent number: 10573386
    Abstract: To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wan-Dong Kim, Tae-Hyun Kim, Sang-Wan Nam, Sang-Soo Park, Jae-Yong Jeong
  • Patent number: 10559368
    Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for memory cells, where the program disturb can affect both memory cells and select gates in a NAND structure. During a pre-charge phase of a programming operation, a drain side select gate may be biased to a higher voltage than an adjacent word line, resulting in a disturb of the select gate due to hot-electron injection. This can raise the threshold voltage of the select gate, causing error in reading the NAND string or even making it inaccessible. To help avoid this problem, during a program pre-charge, the voltage applied to the select gate is raised in a sequence of steps, rather than driving the select gate directly to its final pre-charge voltage level.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: February 11, 2020
    Assignee: SanDisk Technologies LLC
    Inventor: Xiang Yang
  • Patent number: 10553301
    Abstract: Non-volatile memory and processes for reprogramming data posing a potential reliability concern are provided. A process is provided for distinguishing between cross-temperature effects and read disturb effects as part of determining whether to perform a maintenance operation such as reprogramming. A process is provided that compensates for cross-temperature effects while testing to determine whether to perform a maintenance operation. Applying temperature compensation attempts to remove cross-temperature effects so that testing accurately detects whether read disturb has occurred, without the effects of temperature. By reducing cross-temperature effects, maintenance operations can be more accurately scheduled for memory that has experienced read disturb, as opposed to cross-temperature effects.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: February 4, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Narayan K, Sateesh Desireddi, Aneesh Puthoor, Dharmaraju Marenahally Krishna, Arun Thandapani, Divya Prasad, Thendral Murugaiyan, Piyush Dhotre
  • Patent number: 10553605
    Abstract: A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Mo Gu, Kyeong Jin Park, Hyun Mog Park, Byoung Il Lee, Tak Lee, Jun Ho Cha
  • Patent number: 10546257
    Abstract: Optimization of event aggregation in an event-driven system is provided. An event queue is queried for a current event. A workload affinity coefficient that describes the current event, at least in part, is read. A database is searched for one or more matching workload affinity coefficients. The current event and one or more events that are respectively associated with one or more matching workload affinity coefficients are aggregated, thereby generating an aggregated event.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sean Dunne, Martin A. Flint, Liam Harpur, Peter M. McGrath
  • Patent number: 10546646
    Abstract: An improved low-power sense amplifier for use in a flash memory system is disclosed. The reference bit line and selected bit line are pre-charged during a limited period and with limited power consumed. The pre-charge circuit can be trimmed during a configuration process to further optimize power consumption during the pre-charge operation.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: January 28, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Xiaozhou Qiang, Xiao Yan Pi, Kai Man Yue, Li Fang Bian
  • Patent number: 10541029
    Abstract: Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: January 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Peter Sean Feeley, Koji Sakui, Akira Goda
  • Patent number: 10541037
    Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 21, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Dengtao Zhao, Deepanshu Dutta
  • Patent number: 10535408
    Abstract: Memories having a controller configured to apply a first voltage level to channel regions of memory cells of an array of memory cells coupled to a plurality of access lines; apply a second voltage level, lower than the first voltage level, to a first access line; apply a third voltage level, lower than the second voltage level, to a second access line while applying the second voltage level to the first access line and while applying the first voltage level to the channel regions of the memory cells; and increase the voltage level applied to the second access line to the second voltage level and decrease the voltage level applied to the first access line to a fourth voltage level, lower than the second voltage level and different than the third voltage level, while applying the first voltage level to the channel regions of the memory cells.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Aaron S. Yip
  • Patent number: 10535604
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: January 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Patent number: 10529429
    Abstract: A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a plurality of memory layers stacked on a semiconductor substrate, wherein each of the plurality of memory layers includes one or more connection control transistors, one or more drain select transistors, a plurality of memory cells, and a source select transistor electrically coupled in series between a plurality of bit lines and a common source line, and the plurality of memory layers share the plurality of bit lines, and the common source lines electrically coupled to each of the plurality of memory layers are electrically disconnected.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10522227
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 31, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Takashi Kobayashi, Yoichi Minemura, Eietsu Takahashi, Masaki Kondo, Daisuke Hagishima
  • Patent number: 10515711
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells coupled between a common source line and a bit line, and a voltage generator applying operating voltages to word lines coupled to the memory cells or discharging potential levels of the word lines, wherein during a program verify operation, the voltage generator applies a program verify voltage and a pass voltage as the operating voltages to the word lines, and subsequently applies a set voltage to the common source line during a period in which the memory cells are turned on.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 24, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10510424
    Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of pages; a voltage supply unit configured to provide operating voltages to the plurality of pages; a plurality of page buffers coupled to a plurality of bit lines of the memory cell array and configured to control and sense currents flowing through the plurality of bit lines in response to a page buffer sensing signal; and a control logic configured to control the voltage supply unit and the plurality of page buffers such that the plurality of pages are successively programmed, and to control a potential level of the page buffer sensing signal depending on a program sequence of the plurality of pages during a program verify operation of a program operation.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: December 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Won Hee Lee
  • Patent number: 10510768
    Abstract: A 3D memory device comprises: a substrate; a plurality of U-shaped memory cells strings each including a first, bit line-side string portion or pillar, a second, source line-side string portion or pillar and a buried string portion formed in the substrate and connected to a first end of the first string portion and to a first end of the second string portion, the U-shaped memory cells strings including stacks of memory cells along the first and second string portions. Bit line selectors are arranged at a second end of the first string portions opposed to the first end, for the selective connection to respective bit lines; source line selectors are arranged at a second end of the second string portions opposed to the first end, for the selective connection to respective source lines.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Trinandable S.r.l.
    Inventor: Sabrina Barbato
  • Patent number: 10497444
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung
  • Patent number: 10482963
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a first stacked region, and a first structure body. The first stacked region includes first and second selection gate electrodes, first electrodes arranged in a first direction and provided between the first and second selection gate electrodes, second electrodes arranged in the first direction and provided between the second selection gate electrode and the first electrodes, and third electrodes arranged in the first direction and provided between the first electrodes and the second electrodes. A first spacing between two mutually-adjacent first electrodes is wider than a third spacing between two mutually-adjacent third electrodes. A second spacing between two mutually-adjacent second electrodes is wider than the third spacing.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: November 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Daisuke Hagishima
  • Patent number: 10460813
    Abstract: A nonvolatile memory device according to some embodiments of the inventive concepts may include a memory cell array, a first page buffer connected to the memory cell array via a first plurality of bit lines, and a second page buffer connected to the memory cell array via a second plurality of bit lines. The first page buffer circuit may include a first bit line selection circuit, a first bit line shut-off circuit, and a first latch circuit. The second page buffer may include a second bit line selection circuit, a second bit line shut-off circuit, and a second latch circuit. The first and second bit line selection circuits, the first and second bit line shut-off circuits, and the first and second latch circuits may be sequentially arranged in a direction away from the memory cell array. A width of the data lines may be greater than a width of the bit lines.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: October 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jeung-hwan Park
  • Patent number: 10461126
    Abstract: The present disclosure relates to a memory circuit having a shared control device for access to target and complementary memory devices for improved differential sensing. The memory circuit has a control device arranged within a substrate and having a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal. A first memory device has a first lower electrode separated from a first upper electrode by a first data storage layer. The first upper electrode is coupled to the third terminal and the first lower electrode is coupled to a first bit-line. A second memory device has a second lower electrode separated from a second upper electrode by a second data storage layer. The second upper electrode is coupled to the second bit-line and the second lower electrode is coupled to the third terminal.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yang Tsai, Kuo-Ching Huang, Tong-Chern Ong
  • Patent number: 10460806
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: October 29, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiro Shiino, Eietsu Takahashi
  • Patent number: 10454721
    Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: October 22, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kensuke Yamamoto, Kosuke Yanagidaira
  • Patent number: 10438656
    Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Aliasgar S. Madraswala, Bharat M. Pathak, Binh N. Ngo, Naveen Vittal Prabhu, Karthikeyan Ramamurthi, Pranav Kalavade
  • Patent number: 10438673
    Abstract: Provided are an erasing method, erasing apparatus for memory cells and a storage medium to perform erase loops with a more appropriate erasing voltages. The method includes performing erase loops on a target erasing block by sequentially using first erasing voltages Vn; and when a predetermined condition is reached, proceeding to perform erase loops on the target erasing block by sequentially using second erasing voltages Um until the target erasing block is successfully erased. Vn=V1+(n?1)×d1, where n denotes erase loop counts of the first erasing voltages, n is an integer greater than or equal to 1, and V1 and d1 are positive numbers. Um=Vn+(m?1)×d2, where m denotes erase loop counts of the second erasing voltages, m is an integer greater than or equal to 2, and d2 is a positive number not equal to d1.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 8, 2019
    Assignee: SHINE BRIGHT TECHNOLOGY LIMITED
    Inventor: Minyi Chen
  • Patent number: 10439002
    Abstract: A connection unit is provided adjacently to the cell array unit and electrically connected to a peripheral circuit unit positioned downwardly of the cell array unit. The cell array unit has a configuration in which a variable resistance layer is provided at intersections of a plurality of word lines extending in a horizontal direction and a plurality of bit lines extending in a vertical direction. The connection unit includes a lower wiring line layer in which a base portion bundling a plurality of the word lines is formed, and a middle wiring line layer and upper wiring line layer formed upwardly thereof. The lower wiring line layer includes: a first penetrating electrode connecting the plurality of word lines and the peripheral circuit unit; and a second penetrating electrode connecting at least one of the middle wiring line layer and upper wiring line layer and the peripheral circuit unit.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenichi Murooka
  • Patent number: 10431273
    Abstract: A semiconductor memory device according to an embodiment includes: a row decoder and a memory cell array including a first block. The first block includes: a first region, a second region adjacent to the first region in the first direction, and a third region configured to connect the first region and the second region. The memory cell array further includes: a first insulating layer buried in a first trench between the first region and the second region and in contact with the third region; a first contact plug provided in the first insulating layer and electrically connected to the row decoder; and a first interconnect configured to connect a selection gate line and the first contact plug.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Takuya Futatsuyama
  • Patent number: 10424369
    Abstract: A semiconductor memory device includes memory cells connected to word lines and bit lines. In a verification operation, a controller applies first and second verification voltages to a word line in sequence, a first voltage to a first bit line of a first cell and a second voltage to second bit line during first level verification, and, if the first cell passes first voltage level verification, the first voltage is then applied to both the first and second bit lines while the second verification voltage is applied to the word line.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: September 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshikazu Harada
  • Patent number: 10424382
    Abstract: Devices and techniques for increased NAND performance under high thermal conditions are disclosed herein. An indicator of a high-temperature thermal condition for a NAND device may be obtained. A workload of the NAND device may be measured in response to the high-temperature thermal condition. Operation of the NAND device may then be modified based on the workload and the high-temperature thermal condition.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Sebastien Andre Jean
  • Patent number: 10418109
    Abstract: A memory device and a programming method for a memory cell array are provided. The memory device includes a memory cell array, a selection switch, a row decoder, a voltage generator, and a memory controller. The memory controller controls the row decoder according to input data to adjust a control path sequence of address control signals, and the memory controller simultaneously controls the voltage generator to adjust a data path sequence of input data signals, so as to perform a programming operation on memory cells of the memory cell array.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: September 17, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Wen-Chiao Ho
  • Patent number: 10418104
    Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: September 17, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 10403721
    Abstract: A field effect transistor, a memory element, and a manufacturing method of a charge storage structure are provided. The memory element includes a plurality of field effect transistors, and each of the field effect transistors includes a substrate, a source region, a drain region, a gate conductive layer, and a charge storage structure. Both the source region and the drain region are located in the substrate and connected to an upper surface of the substrate. The source and drain regions are spaced apart from each other to define a channel region therebetween. The gate conductive layer is disposed over the upper surface and overlaps with the channel region. The charge storage structure disposed between the gate conductive layer and the channel region includes a ferroelectric material and a paraelectric material so that the charge storage structure has better capability of trapping charges and a higher switching speed.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: September 3, 2019
    Assignee: NUSTORAGE TECHNOLOGY CO., LTD.
    Inventors: Fu-Chou Liu, Yung-Tin Chen
  • Patent number: 10388391
    Abstract: A memory device may include a plurality of memory blocks and one or more peripheral circuits. Each of the plurality of memory blocks may include a plurality of cell strings. The one or more peripheral circuits may perform one or more operations on a selected memory block among the plurality of memory blocks. The operations may include turning off select transistors of the cell strings included in the selected memory block, increasing channel voltages of the cell strings included in the selected memory block by applying a pass voltage to all word lines coupled to the selected memory block, turning on the select transistors included in the selected memory block, and performing a read or a verify operation on the selected memory block.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10388386
    Abstract: A semiconductor device includes first and second memory cells, a first word line, and a first and second bit lines, and a row control circuit. The first memory cell has a first gate electrode and a first channel having one end and another end. The second memory cell has a second gate electrode and a second channel having one end and another end. The first word line electrically connected with each of the first gate electrode and the second gate electrode. The first and second bit lines electrically connected with the first and second channels, respectively. When a threshold voltage of each of the first and second memory cells are caused to be shifted, the semiconductor device causes a first voltage between the first gate electrode and the first channel and a second voltage between the second gate electrode and the second channel to be differentiated.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: August 20, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yusuke Umezawa, Shigeru Kinoshita
  • Patent number: 10381095
    Abstract: In order to have different subsets of memory cells of a non-volatile memory system erase at the same speed, it is proposed to perform erasing by separately controlling the speed of erase for the different subsets in response to observing speed information for the subsets during the erasing.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: August 13, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Kei Date, Hideto Tomiie
  • Patent number: 10381085
    Abstract: Apparatus and methods of operating such apparatus include applying a first voltage level to a source connected to a first end of a string of series-connected memory cells, applying a second voltage level to a data line connected to a second end of the string of series-connected memory cells, and applying a third voltage level to a first access line coupled to a first memory cell of the string of series-connected memory cells concurrently with applying the first and second voltage levels, wherein the magnitude of the third voltage level is greater than the magnitude of both the first voltage level and the second voltage level, and wherein a polarity and the magnitude of the third voltage level are expected to decrease a threshold voltage of the first memory cell when concurrently applying the first, second and third voltage levels.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: August 13, 2019
    Assignee: Micron Technogy, Inc.
    Inventor: Jun Xu