Logic Connection (e.g., Nand String) Patents (Class 365/185.17)
  • Patent number: 11373717
    Abstract: A memory device may include: a control circuit comprising a first verification component suitable for counting the number of memory cells in the selected word line having an excessively high threshold voltage as excessive memory cells, after a program operation is completed; and a second verification component suitable for counting the number of failed bits when the number of excessive memory cells counted is greater than or equal to an excess threshold value, and suitable for outputting a pass or fail signal for the program operation according to the count of at least one of the first verification component and the second verification component.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: June 28, 2022
    Assignee: SK hynix Inc.
    Inventor: Sang-Sik Kim
  • Patent number: 11373716
    Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a cell string having memory cells stacked perpendicular to a surface of a substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell after the first memory cell is completely programmed, the second memory cell being connected to a second word line closer to the substrate than the first word line, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 28, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wandong Kim, Jinwoo Park, Seongjin Kim, Sang-wan Nam
  • Patent number: 11361799
    Abstract: A semiconductor memory device including a substrate; an array of memory cells arranged in rows and columns on the substrate, each memory cell comprising a vertical pillar-shaped active region having upper and lower source/drain regions and a channel region, and a gate stack formed around the channel region; a plurality of bit lines on the substrate, each bit line located below a column of memory cells and electrically connected to the lower source/drain regions of the memory cells; and a plurality of word lines on the substrate, each word line extending in a row direction and connected to gate conductors of the memory cells in a row of memory cells, each word line comprising first portions extending along peripheries of the memory cells and second portions extending between the first portions, the first portions of the word line extending in a conformal manner with sidewalls of the upper source/drain regions.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 14, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11355506
    Abstract: A first-tier structure includes a first vertically alternating sequence of first continuous insulating layers and first continuous sacrificial material layers and a first-tier retro-stepped dielectric material portion overlying first stepped surfaces of the first vertically alternating sequence. A second vertically alternating sequence of second continuous insulating layers and second continuous sacrificial material layers is formed over the first-tier structure. A vertically alternating stack of insulating plates and dielectric material is formed over the first-tier retro-stepped dielectric material portion. Alternatively, dielectric pillar structures may be formed in lieu of the vertically alternating stack. After formation of memory stack structures, electrically conductive layers replace portions of the first and second continuous sacrificial material layers.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 7, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hirofumi Tokita, Takayuki Maekura, Romain Mentek
  • Patent number: 11342034
    Abstract: Multiple apparatus and methods of the specification include a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 11334265
    Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh
  • Patent number: 11335421
    Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may be configured to perform a plurality of program loops, each including a program pulse apply operation and a program verify operation, on selected memory cells of the plurality of memory cells. The control logic may be configured to control, in response to a suspend command, the peripheral circuit to suspend an n-th program loop of the plurality of program loops, where n is a natural number of 1 or more, and configured to control, in response to a resume command, the peripheral circuit to resume the suspended n-th program loop after performing a recovery pulse apply operation compensating for charges detrapped from a channel area of the selected memory cells.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: May 17, 2022
    Assignee: SK hynix Inc.
    Inventor: Min Kyu Jeong
  • Patent number: 11328754
    Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current during program operations using pre-charge timing control based on an inhibit bit line count acquired from data latches. When the inhibit bit line count is within a bit line count range, the controller pre-charges bit lines in memory during a first time period to a first target voltage, and when the inhibit bit line count is outside the bit line count range, the controller pre-charges the bit lines during a second, earlier time period to a second, smaller target voltage. The controller is thus configured to reduce current and minimize operation overlaps in the earlier time period during the middle of the program operation where current is highest. Thus, a balance in power consumption and performance may be achieved during program operations using timing control.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: May 10, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yu-Chung Lien, Juan Lee, Huai-Yuan Tseng
  • Patent number: 11328780
    Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device in which groups of memory cells are programmed from checkpoint states to respective data states. In a first program pass, groups of memory cells are programmed to respective checkpoint states with verify tests. Each checkpoint state is associated with a set of data states. In a second program pass, the memory cells are programmed closer to their assigned data state with a specified number of program pulses. In a third program pass, the memory cells are programmed to their assigned data state by applying program pulses and performing verify tests. The number of checkpoint states and the number of data states associated with each checkpoint state can be optimized based on a spacing between the verify voltages of the data states.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: May 10, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Huiwen Xu, Jun Wan, Bo Lei
  • Patent number: 11328768
    Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: May 10, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Maurizio Francesco Perroni, Fabio Enrico Carlo Disegni, Davide Manfré, Cesare Torti
  • Patent number: 11328761
    Abstract: The memory device includes a memory block, a voltage generator, a pass switch group connecting or blocking the global lines and the local lines to each other or from each other in response to a block selection voltage, a decoder, and a logic circuit configured to control the decoder and the voltage generator so that the local lines are floated after initializing a channel of the strings and a voltage of the global lines is lower than a voltage of the global lines when initializing the channel of the strings, when a program operation of selected memory cells included in a selected page of the memory block is completed, the channels of the strings are initialized and the local lines are floated.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventors: Chi Wook An, Kyung Sub Park, Un Sang Lee
  • Patent number: 11322212
    Abstract: A semiconductor memory device according to an embodiment includes a string, a bit line, a well line, and a sequencer. The string includes first and second select transistors, and memory cell transistors using a ferroelectric material. The bit line and the well line are connected to the first and second select transistors, respectively. At a time in an erase verify operation, the sequencer is configured to apply a first voltage to the memory cell transistors, to apply a second voltage lower than the first voltage to the first select transistor, to apply a third voltage lower than the first voltage to the second select transistor, to apply a fourth voltage to the bit line, and to apply a fifth voltage higher than the fourth voltage to the well line.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: May 3, 2022
    Assignee: Kioxia Corporation
    Inventor: Takashi Maeda
  • Patent number: 11322213
    Abstract: A method comprises determining a verify voltage for a next iteration of a verify operation to be performed on memory cells a first set of memory cells of a selected word line, and determining data states for a second set of memory cells of at least one neighboring word line. The method further comprises determining, based on the data states, a verify voltage configuration that includes bit line voltage biases or sense times, and performing the next iteration of the verify operation on the selected word line by using the verify voltage configuration to iteratively verify whether respective memory cells, of the second set of memory cells, have threshold voltages above the verify voltage, wherein determining the data states, determining the verify voltage configuration, and performing the next iteration are to be repeated until a program stop condition is satisfied.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: May 3, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Muhammad Masuduzzaman, Deepanshu Dutta
  • Patent number: 11315653
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) and method for controlling the DRAM. The DRAM has a first operation mode and a second operation mode. The DRAM includes a control module and a connecting module. The connecting module includes an input/output (I/O) pad and a determining circuit. The I/O pad is configured to receive a first input signal. The determining circuit includes a detector and a first determining unit. The detector is configured to compare the first input signal to a reference signal so as to generate a first signal. The first determining unit is configured to receive the first signal and generate a first output signal according to the first signal. The control module is configured to control the DRAM being operated under the first operation mode or the second operation mode according to the first output signal.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 26, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Jen Chen
  • Patent number: 11309027
    Abstract: A semiconductor memory device includes a cell string with a plurality of selection transistors, a plurality of dummy transistors and a plurality of memory cell transistors coupled in series therein and a pass transistor (TR) unit with a plurality of pass transistors that transmit a plurality of driving signals to the cell string. The pass TR unit includes a plurality of first pass transistors transmitting a first driving signal with a first level voltage, among the plurality of driving signals, to the plurality of selection transistors, respectively, and a plurality of second pass transistors transmitting a second driving signal with a second level voltage that is higher than the first level voltage, among the plurality of driving signals, to a plurality of dummy transistors, respectively. Each of the second pass transistors has a larger channel area than each of the first pass transistors.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Sung Wook Jung
  • Patent number: 11309038
    Abstract: A memory device may include: a memory cell array including a plurality of planes; and a voltage generation circuit including a master pump component and at least one or more sub-pump components that respectively correspond to the planes. During an interleaved operation, the master pump component may generate a first output voltage in response to a first pump clock, and the sub-pump components may generate second output voltages in response to second pump clocks. The master pump component and the sub-pump components may respectively provide the first output voltage and the second output voltages to the corresponding planes. During a non-interleaved operation, the master pump component and the sub-pump components may generate the first output voltage in response to the first pump clock and provide the first output voltage to a selected plane of the plurality of planes.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyun Chul Cho
  • Patent number: 11309436
    Abstract: A semiconductor memory device includes, a stack structure, and a channel structure passing through the stack structure, wherein the channel structure includes a channel layer passing through the stack structure and a memory layer surrounding the channel layer, the stack structure includes a gate contacting the channel layer, and the channel layer and the gate form a Schottky junction.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Hae Chang Yang
  • Patent number: 11302399
    Abstract: A semiconductor storage device includes first and second memory cells, first and second word lines connected to the first and second memory cells, respectively, a bit line connected to the first and second memory cells, and a sense amplifier including a sense node. During a first read, a controller applies a first read voltage to the second word line and determines a read result. During a second read, the controller discharges the sense node for a first time period while applying a second read voltage to the first word line to determine a first read result, and discharges the sense node for a second time period while applying the second read voltage to determine a second read result. The controller determines read data based on the first read result, the second read result, and the read result of the second memory cell.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Kosuke Yanagidaira, Takuyo Kodama, Takeshi Hioka
  • Patent number: 11296106
    Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented; and a level of memory control circuits, where the memory control circuits is disposed either above or below the plurality of memory cells.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: April 5, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky
  • Patent number: 11282847
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally there-along in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough
  • Patent number: 11276467
    Abstract: A vertical NAND string in a channel-stacked 3D memory device may be programmed using ISPP scheme, wherein a preparation step is introduced immediately after each verification step and before the start of a corresponding verification step. During the preparation step, the electrons accumulated in the channel may be drained by the selected bit line for enhancing the coupling effect of the channel, thereby reducing program disturb and increasing program speed.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 15, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Hongtao Liu, Lei Jin, Shan Li, Yali Song
  • Patent number: 11276437
    Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 11276445
    Abstract: A data storage device includes a nonvolatile memory device including dies including word line groups in which word lines are grouped; and a controller. The controller includes a word line health rating logic configured to determine a health rating of each word line and a health rating of each word line group based on state information on each of health rating factors associated with the word lines; a memory including a word line health rating table in which the health rating of each word line and the health rating of each word line group are stored; and a mapping logic configured to generate a management target logical super block by mapping one word line group having a lowest health rating and word line groups having a highest health rating, and generate a normal logical super block by mapping word line groups having intermediate health ratings.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: March 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Nack Hyun Kim, Shin Hye Lee, Min Kyu Lee
  • Patent number: 11270776
    Abstract: Apparatuses and techniques are described for reducing a peak current consumption during a program operation for a memory device. A higher current peak occurs in a first program loop of the program operation when a set of word lines is in a discharged state, also referred to as a first read condition. A current reduction countermeasure can be used when ramping up voltages of unselected word lines to a read pass voltage during the verify phase of the program loop. The countermeasure can involve reducing the ramp up rate, reducing the read pass voltage, or delaying the start of the ramp up for a portion of the word lines.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: March 8, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 11269542
    Abstract: A memory system includes: a nonvolatile memory device including a plurality of memory blocks each including a plurality of pages, the plurality of memory blocks including at least one bad block and normal block; and a controller performing a backup operation of copying data from an over-read page into a back-up page when the over-read page whose number of read requests is equal to or greater than a first reference number is detected among the plurality of pages in the normal block, and reading the data from the back-up page in response to a read request for the over-read page after the backup operation, the controller performing an operation of setting a page which is programmable/readable as the back-up page, and not using a page which is unprogrammable/unreadable, among the plurality of pages in the bad block.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Eujoon Byun
  • Patent number: 11270773
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: March 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
  • Patent number: 11264398
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: March 1, 2022
    Assignee: Kioxia Corporation
    Inventor: Naoki Yasuda
  • Patent number: 11257545
    Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 22, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Wenzhe Wei, Hongtao Liu, Kaikai You, Da Li, Ying Huang, Yali Song, Dejia Huang
  • Patent number: 11257541
    Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 22, 2022
    Assignee: Kioxia Corporation
    Inventors: Naomi Takeda, Masanobu Shirakawa, Akio Sugahara
  • Patent number: 11250915
    Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: February 15, 2022
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Maejima, Katsuaki Isobe, Naohito Morozumi, Go Shikata, Susumu Fujimura
  • Patent number: 11250892
    Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current during program operations using pre-charge ramp rate control based on an inhibit bit line count acquired from data latches. When the inhibit bit line count is within a bit line count range, the controller pre-charges bit lines in memory at a first ramp rate to a first target voltage, and when the inhibit bit line count is outside the bit line count range, the controller pre-charges the bit lines at a second, faster ramp rate to a second, smaller target voltage. The inhibit bit line count may increase throughout a program operation, and the bit line count range may be configured for the middle of the program operation where current is typically high. Thus, a balance in power consumption and performance may be achieved during program operations using ramp rate control.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: February 15, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yu-Chung Lien, Juan Lee, Huai-Yuan Tseng
  • Patent number: 11238937
    Abstract: Memories having a controller configured to apply a particular multi-step programming pulse to a selected access line of a programming operation, enable for programming memory cells that have a particular desired data state for the programming operation and are deemed to have a threshold voltage lower than a first threshold voltage level while applying a first step of a multi-step programming pulse to the selected access line, and enable for programming memory cells that have the particular desired data state for the programming operation and are deemed to have a threshold voltage lower than a second threshold voltage level and higher than the first threshold voltage level while applying a second step of the multi-step programming pulse, lower than the first step of the multi-step programming pulse, to the selected access line.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Eric N. Lee
  • Patent number: 11238946
    Abstract: A memory might include a common source, a first data line and a second data line, an array of memory cells, a plurality of access lines, and a controller. The array of memory cells might include a first string of memory cells selectively connected between the first data line and the common source and a second string of memory cells selectively connected between the second data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of the first string of memory cells and a control gate of a respective memory cell of the second string of memory cells. The controller may access the array of memory cells. The controller might be configured to implement a source-side seeding operation concurrently with a data line set operation.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jun Xu, Yingda Dong
  • Patent number: 11238941
    Abstract: A semiconductor memory device comprises a bit line and source line, a first memory cell and first and second transistors connected therebetween, a second memory cell and third and fourth transistors connected therebetween, and first through fifth wirings connected to the first and the second memory cells and gate electrodes of the first to the fourth transistors. At a first timing of a read operation, voltages of the first through third wirings are larger than voltages of the fourth and fifth wirings. At a second timing, voltages of the second and third wirings are larger than voltages of the fourth and fifth wirings. At a third timing, voltages of the fourth and fifth wirings are larger than their voltages at the second timing. At a fourth timing, voltages of the second and third wirings are larger than a voltage of the fourth wiring.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: February 1, 2022
    Assignee: Kioxia Corporation
    Inventor: Hiroki Date
  • Patent number: 11239250
    Abstract: Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A trench is formed in a stack over a substrate of the semiconductor device where the stack includes alternating first layers and second layers. The trench has a first sidewall and a second sidewall opposite to the first sidewall. Channel materials are formed along the first and second sidewalls of the trench, respectively. The trench is further divided into multiple units by replacing portions of the channel materials with first dielectric structures. Remaining portions of the channel materials along the first and second sidewalls form first and second channel structures of first and second strings of transistors, respectively. The second layers are replaced with first and second gate structures of the first and second strings of transistors, respectively. Each of the first and second strings of transistors is vertically stacked over the substrate.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: February 1, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Qiguang Wang
  • Patent number: 11237612
    Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: February 1, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jonathan S. Parry, Stephen L. Miller, Liang Yu
  • Patent number: 11238935
    Abstract: A semiconductor memory device includes a memory cell array, a well voltage control circuit, and a source voltage control circuit. Before writing data, first and second transistors respectively connected to a select gate line and a word line are turned on at a first timing, and a ground voltage is applied to the first transistor at a second timing and to the second transistor at a third timing. The source voltage control circuit applies a first voltage to the source line at a fourth timing that is simultaneous with or after the first timing and before the second timing, and the well voltage control circuit applies the first voltage to the well region at a fifth timing that is simultaneous with or after the first timing and before the second timing, and applies a ground voltage to the well region at a sixth timing that is after the fifth timing.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: February 1, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Xu Li
  • Patent number: 11232840
    Abstract: A semiconductor device including a page buffer is disclosed, which reduces the number of lines of the page buffer. The semiconductor device includes a plurality of bit lines, classified into a first group and a second group, that are arranged alternating, a first page buffer circuit coupled to the plurality of bit lines and a plurality of connection lines corresponding to the plurality of bit lines, and a second page buffer circuit coupled to the plurality of connection lines. Each of the first group and the second group includes a plurality of bit-line pairs classified into odd bit lines and even bit lines. The plurality of connection lines includes odd connection lines and even connection lines, and odd connection lines corresponding to the odd bit lines are arranged contiguous to each other, and even connection lines corresponding to the even bit lines are arranged contiguous to each other.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: January 25, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Lae Oh, Dong Hyuk Kim, Tae Sung Park, Soo Nam Jung
  • Patent number: 11227664
    Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a memory block, a voltage generation circuit configured to operate in a first mode in which an operating voltage is generated using an internal voltage or a second mode in which the operating voltage is generated using an external voltage, and to provide the operating voltage to the memory block, and a control logic configured to measure and store a first rising time during which the operating voltage rises to a target level in the first mode, and to control the voltage generation circuit so that a second rising time during which the operating voltage rises to the target level in the second mode is equal to or longer than the first rising time.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: January 18, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyun Chul Cho
  • Patent number: 11227832
    Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer including first to third portions which are arranged along a first direction and differ in position from one another in a second direction; a conductive layer including a fourth portion extending in the second direction and a fifth portion extending in the first direction; a first insulating layer between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug coupled to the fourth portion; a second contact plug coupled to the first semiconductor layer in a region where the first insulating layer is formed; a first interconnect; and a first memory cell apart from the fifth portion in the first direction and storing information between the semiconductor layer and the first interconnect.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: January 18, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji Hosotani, Fumitaka Arai, Keisuke Nakatsuka, Nobuyuki Momo, Motohiko Fujimatsu
  • Patent number: 11222900
    Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 11, 2022
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiro Shimojo, Tomoya Sanuki
  • Patent number: 11222674
    Abstract: A memory device includes a top select cell, a top dummy cell and a string of memory cells. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top select line. The top dummy cell has a control terminal coupled to a top dummy word line. The string of memory cells has control terminals coupled to respective word lines. A method operating the memory device includes prior to a program operation, applying a pre-pulse voltage to the top dummy word line, the top select line and the bit line while applying a low voltage to the word lines, and then sequentially applying the low voltage to the top dummy word line, the top select line and the bit line while applying the low voltage to the word lines.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: January 11, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Shan Li, Kaikai You, Ying Cui, Jianquan Jia, Kaiwei Li, An Zhang
  • Patent number: 11222697
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: January 11, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung
  • Patent number: 11217283
    Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: January 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junha Lee, Seonkyoo Lee, Jeongdon Ihm, Byunghoon Jeong
  • Patent number: 11217312
    Abstract: A semiconductor device includes a first memory block including a first memory string, a second memory block including a second memory string, a common source line commonly coupled to the first memory block and the second memory block, a first bit line coupled to the first memory string, a second bit line coupled to the second memory string, a first page buffer for accessing the first memory string through the first bit line, and a second page buffer for accessing the second memory string through the second bit line. The first bit line and the first page buffer are electrically connected to each other when the first memory block is selected.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 11211132
    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a plurality of memory cells coupled to a control circuit. The control circuit is configured to receive data indicating a data state for each memory cell of a set of memory cells of the plurality of memory cells and program, in multiple programming loops, the set of memory cells according to the data indicating the data state for each memory cell of the set of memory cells. The control circuit is further configured to determine that the programming of the set of memory cells is in a last programming loop of the multiple programming loops and in response to the determination, receive data indicating a data state for each memory cell of another set of memory cells of the plurality of memory cells.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: December 28, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Piyush A. Dhotre, Sahil Sharma, Niles Yang, Phil Reusswig
  • Patent number: 11205493
    Abstract: Apparatuses and techniques are described for reducing read disturb in a memory device by reducing the channel gradient and therefore reducing the charge injection to the memory cell. Channels of unselected NAND strings are boosted before reading memory cells in selected NAND strings. The boosting involves applying a positive voltage to source ends and drain ends of the unselected NAND strings, while drain-side select gate transistors are turned on and then off and a voltage signal of non-adjacent word lines of a selected word line, WLn, increases to a read pass voltage. A voltage signal of adjacent word lines of WLn is increased to a peak level to increase the channel conduction for faster read, where the peak level is less than the read pass voltage, decreased to a reduced level to reduce a channel gradient and therefore reduce a read disturb, then increased to the read pass voltage.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: December 21, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Abu Naser Zainuddin, Henry Chin, Jiahui Yuan
  • Patent number: 11200960
    Abstract: A memory system includes a memory device including a plurality of memory blocks, each block having a plurality of pages to store data; and a controller suitable for detecting a number of error bits from data stored in the plurality of pages; summing the number of error bits; generating a bad word line list based on the sum of the error bits; and performing a test read operation on the plurality of pages based on the bad word line list.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: December 14, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 11200958
    Abstract: Memories might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to perform a sense operation on a particular memory cell of a string of series-connected memory cells, discharge the access line for a second memory cell of the string of series-connected memory cells to a first voltage level and discharge the access line for the particular memory cell to a second voltage level higher than the first voltage level after completion of the sense operation, and discharge the access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level after initiating the discharge of the access line for the particular memory cell.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Cantarelli, Augusto Benvenuti, Massimo Ernesto Bertuccio
  • Patent number: 11200955
    Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 14, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Taeck Jung, Sang-Wan Nam, Jinwoo Park, Jaeyong Jeong