Abstract: A memory device comprising: a plurality of memory blocks each including a plurality of word lines arranged between a first and second select line, a peripheral circuit performs an erase operation by applying an erase voltage to a source or drain line of a selected memory block, and a control logic controls, in a period in which the erase operation is performed, the peripheral circuit to: sequentially select the plurality of word lines included in the selected memory block at least one by one from a word line closest to the first and second select line to a word line farthest from the first and second select line, apply a first erase permission voltage to the selected word lines, and apply a second erase permission voltage, which have a higher potential level than the first erase permission voltage, to remaining word lines except the selected word lines.

Abstract: A semiconductor memory device includes a memory block, and control logic. The memory block includes a plurality of memory cells. The control logic controls a peripheral circuit to perform a read operation on selected memory cells among the plurality of memory cells. The read operation includes a bit line precharge operation, an evaluation operation, and a sensing operation. The control logic is configured to control the peripheral circuit to float a common source line coupled to the memory block during at least a partial period of a period of the bit line precharge operation, in which a voltage of a plurality of bit lines coupled to the memory block increases.

Abstract: Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.

Abstract: A memory device for performing temperature compensation and an operating method thereof are provided. The memory device includes a memory cell array; a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a page buffer connected to each of the plurality of bit lines, and configured to perform a pre-charge operation during a pre-charge period for data reading; and a control logic configured to differently control the pre-charge operation of the page buffer circuit according to a detected temperature, wherein the pre-charge period includes a first period in which the plurality of bit lines are overdriven and a second period in which the plurality of bit lines are driven at a voltage lower than that of the first period, and the first period where the detected temperature is a first temperature is set to be shorter than the second period where the detected temperature is a second temperature higher than the first temperature.

Abstract: A circuit includes a linear regulator coupled with a memory array and a pump regulator coupled with a charge pump, the charge pump to provide a supply voltage to the linear regulator. A digital-to-analog converter (DAC) has an output coupled with the pump regulator. Control logic is coupled with the DAC and is to perform operations including causing a digital input value to be provided to the DAC to selectively adjust the supply voltage based on a programmable offset value.

Abstract: Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.

Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.

Abstract: The present technology relates to an electronic device. A memory device configured to perform a sensing operation based on a charge degree of a sensing node includes a memory cell array including a plurality of memory cells, a peripheral circuit including a page buffer connected to a selected memory cell among the plurality of memory cells through a bit line, and configured to perform a sensing operation on the selected memory cell, and control logic configured to control the peripheral circuit to precharge a source line among lines connected to the memory cell array and perform the sensing operation based on a degree at which a sensing node in the page buffer is charged, during the sensing operation.

Abstract: Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.

Abstract: Methods of operating a memory device are disclosed. A method may include receiving a write command, and in response to the write command, performing a write operation without precharging a local input/output line subsequent to receipt of the write command and prior to performing the write operation. Another method may include receiving a read command, performing a read operation in response to the read command, and receiving an additional command without precharging the local input/output line subsequent to performing the read operation and prior to receiving the additional command. Memory devices and systems are also disclosed.

Abstract: Apparatus having a string of series-connected memory cells, a plurality of access lines with each access line of the plurality of access lines connected to a control gate of a respective memory cell of the plurality of memory cells, and a controller for access of the string of series-connected memory cells and configured to cause the memory to increase a threshold voltage of a particular memory cell of the string of series-connect memory cells to a voltage level higher than a predetermined pass voltage to be received by a control gate of the particular memory cell during a read operation on the string of series-connected memory cells, and concurrently change a respective data state of each memory cell of a plurality of memory cells of the string of series-connected memory cells.

Abstract: Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times.

Abstract: A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer.

Abstract: A memory device, and a method of operating the same, includes a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells. The memory device also includes a peripheral circuit configured to perform a sensing operation of sensing selected memory cells coupled to a selected word line selected from among the plurality of word lines. The memory device further includes control logic configured to control the peripheral circuit apply a turn-on voltage to a block word line coupled to the selected word line when the sensing operation is terminated and when potentials of the plurality of word lines are increased due to a recovery operation for channels of the plurality of memory cells after the plurality of word lines have been discharged.

Abstract: Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.

Abstract: The present technology relates to an electronic device. A memory device capable of reducing a time consumed in a program operation includes a memory cell array, a page buffer group connected to the memory cell array through a plurality of bit lines and a voltage generator configured to generate voltages to apply to each of a plurality of page buffers included in the page buffer group. Each of the plurality of page buffers includes a precharge circuit that controls potential levels of the plurality of bit lines to be maintained at precharge levels.

Abstract: A method of peak power management (PPM) for a memory chip with multiple memory dies is provided, where each of the multiple memory dies includes a PPM circuit having a PPM contact pad and PPM contact pads of the multiple memory dies are electrically connected. The PPM method includes the following steps: switching on a pull-down driver of the PPM circuit on a selected memory die of the memory chip; verifying a PPM enablement signal regulated by a pull-down current flowing through the pull-down driver; and performing a peak power operation on the selected memory die when the PPM enablement signal indicates that a total current of the memory chip is less than a maximum total current allowed for the memory chip.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.

Abstract: A circuit includes a linear regulator operatively coupled with a memory array, the linear regulator including a primary switch to generate a regulated voltage usable to program memory cells of the memory array. A first digital-to-analog converter (DAC) includes an output coupled with the linear regulator. A pump regulator is operatively coupled with a charge pump, where the charge pump is to provide a supply voltage to the linear regulator. A second DAC includes an output coupled with the pump regulator. Control logic, operatively coupled with the first DAC and the second DAC, is to perform operations including: causing a first digital input value to be provided to the first DAC to selectively smooth noise on the supply voltage; and causing a second digital input value to be provided the second DAC to selectively adjust the supply voltage based on a programmable offset value.

Abstract: A memory device and method of operating the same. A memory device includes a memory block, a peripheral circuit, and a program operation controller. The memory block includes a first sub block connected to a first drain select line and a first source select line, and a second sub block connected to a second drain select line and a second source select line, and each of the first sub block and the second sub block is connected to a plurality of word lines and a common source line. The program operation controller controls the peripheral circuit to transfer a precharge voltage to the channel region through the common source line or a plurality of bit lines connected the memory block, and to apply a control voltage to the first and second source select lines at different time points or to apply the control voltage to the first and second drain select lines at different time points in the step of precharging the channel region.

Abstract: A program method for a memory device is provided. The memory device includes a plurality of memory cells, a bit line and word lines electrically connected to the plurality of memory cells. The plurality of memory cells includes a selected memory cell and unselected memory cells when the memory device is in a program operation. The program method including performing precharge steps, performing program steps and performing a verification step to the selected memory cell after the precharge steps and the program steps. Each of the precharge steps includes applying a precharge voltage to the bit line electrically connected to the unselected memory cells. Each of the program steps includes applying a program voltage to a word line of the word lines electrically connected to the selected memory cell.

Abstract: Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.

Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.

Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

Abstract: A memory device includes drain select lines, source select lines, a plurality of word lines arranged between the drain select lines and the source select lines, and a peripheral circuit configured to perform a program operation on selected memory cells connected to a selected word line among the plurality of word lines. The peripheral circuit includes a voltage generator configured to generate a voltage for initializing a channel of a plurality of memory cells respectively connected to the plurality of word lines in a program phase among a plurality of phases included in the program operation.

Abstract: A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line.

Abstract: A sense circuit of a memory cell includes a first switch, a sense node, a third switch, a connection node, a fourth switch, and a memory cell coupled in series. A boost driver is coupled to the sense node. A second switch and the connection node are coupled in series. The boost driver outputs a first voltage when the first, second, third, fourth switches are turned on. The third switch is then turned off and the boost driver outputs a second voltage higher than the first voltage such that the voltage level at the sense node is not higher than a system voltage. The third switch is turned on, then turned off and the boost driver outputs an intermediate voltage between the first voltage and the second voltage. A state of the memory cell is determined during output of the intermediate voltage.

Abstract: A memory device comprises, on an integrated circuit or multi-chip module, a memory including a plurality of memory blocks, a controller, and a refresh mapping table in non-volatile memory accessible by the controller. The controller is coupled to the memory to execute commands with addresses to access addressed memory blocks in the plurality of memory blocks. The refresh mapping table has one or more entries, an entry in the refresh mapping table mapping of an address identifying an addressed memory block set for refresh to a backup block address. The controller is responsive to a refresh command sequence with a refresh block address to execute a refresh operation, and is configured to restore mapping of the refresh block address to the backup block address upon power-on of the device, to scan the refresh mapping table for a set entry, and to register the set entry in the refresh mapping table.

Abstract: Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes a plurality of memory decks each including a plurality of memory layers in a vertical direction, and a plurality of first dummy memory layers between the first and second memory decks in the vertical direction. Each memory layer in a first memory deck of the plurality of memory decks is first programmed. The first programming includes applying a program voltage to the memory layer and a channel pass voltage smaller than the program voltage to each of the rest of the memory layers in the first memory deck. Each memory layer in a second memory deck of the plurality of memory decks above the first memory deck is second programmed. The second programming includes applying the program voltage to the memory layer and the channel pass voltage to each of the rest of the memory layers in the second memory deck.

Abstract: An electronic device includes a non-volatile memory and a controller. The controller receives data to be written to the non-volatile memory and determines a type of the data. Based on the type of the data, the controller selects a given duration of the data from among multiple durations of the data in the non-volatile memory. The controller sets values of one or more parameters for writing the data to the non-volatile memory based on the given duration. The controller writes the data to the non-volatile memory using the values of the one or more write parameters.

Abstract: When programming a memory device which includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, coarse programming is perform on two adjacent first and second word lines among the plurality of word lines. Next, an unselected bit line among the plurality of bit lines is pre-charged during a first period after performing the coarse programming on the first word line and the second word line. Also, the channel between the unselected bit line and the second word line is turned on at the start of the first period and turned off prior to the end of the first period. Then, fine programming is performed on the first word line during a second period subsequent to the first period.

Abstract: A memory device includes a memory cell block including a plurality of memory cells. The memory device also includes peripheral circuits configured to perform an erase operation by a gate induce drain leakage (GIDL) method by applying a first erase voltage and a second erase voltage to a source line of the memory cell block. The memory device further includes control logic configured to control the peripheral circuits to sequentially perform an operation of applying the first erase voltage and an operation of applying the second erase voltage during the erase operation, wherein memory cells having a plurality of program states, among the plurality of memory cells, are erased to have a pre-erase state during the operation of applying the first erase voltage.

Abstract: A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.

Abstract: Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Abstract: A semiconductor memory device includes memory cells, a first circuit that includes a first latch group including first and second data latch circuits and a second latch group including third and fourth data latch circuits, and a control circuit configured to control a write operation during which first and second data to be written into the memory cells are stored in the first and second data latch circuits, respectively, wherein the first and second data are also stored in the third and fourth data latch circuits, respectively, while the first and second data stored in the first and second data latch circuits, respectively, are being written in the memory cells.

Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.

Abstract: Disclosed is a semiconductor device in which an internal voltage fluctuation when a current jump occurs is restrained. The semiconductor device includes a plurality of blocks, each of which performs a given operation, and a current jump control circuit. The current jump control circuit monitors control signals in each of the blocks and calculates predicted values of consumption current of the blocks, based on results of monitoring at different timings, thereby controlling a fluctuation of consumption current of the blocks. The current jump control circuit controls operation of a subset or all of the blocks, if an increase of a predicted value of consumption current of the blocks is larger than a first value or a decrease of the predicted value is larger than a second value.

Abstract: Apparatus and methods are provided, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are provided.

Abstract: Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes memory decks each including memory layers in a vertical direction. Each memory layer in a first memory deck is first programmed. The first programming includes applying a program voltage to the memory layer and a first channel pass voltage smaller than the program voltage to each rest of the memory layers. Each memory layer in a second memory deck above the first memory deck is second programmed. The second programming includes applying the program voltage to the memory layer and the first channel pass voltage to each rest of the memory layers. The second programming further includes applying a second channel pass voltage smaller than the first channel pass voltage to each memory layer in the first memory deck.

Abstract: A sense amplifier includes a sense circuit coupled to a bitline and a sense node, a charge circuit coupled to the sense node and the sense circuit, a first current control transistor, an inverter circuit having a first latch node and a second latch node, coupled to the first current control transistor, and an input circuit coupled to the first latch node, the second latch node and the sense node. The first current control transistor includes a first terminal coupled to the system voltage source, a second terminal coupled to the inverter circuit, and a control terminal configured to receive a current control signal. The first current control transistor is a P-type transistor.

Abstract: A solid state storage system, and method of operation thereof, including: a system interface configured to receive host commands; a controller, coupled to the system interface, configured to identify frequently read data blocks from the host commands; a non-volatile memory, coupled to the controller, configured for access of the frequently read data blocks; an error correction code unit, coupled to the controller, configured to provide health monitor parameters for the frequently read data blocks verified by the controller; and a redundant frequently read data (RFRD) area, coupled to the error correction code unit, configured to transfer a recovered data from the frequently read data blocks.

Abstract: A memory device and a control method for a non-volatile memory are provided. The non-volatile memory includes a target erasing region and an unselected region. The control method includes: erasing a target memory cell in the target erasing region. The unselected region is a region, excluding the target erasing region, in the non-volatile memory. The step of erasing the target memory cell includes an erasing operation, a verification operation, and an erasing loop after failing to pass the verification operation. The number of times of performing the erasing loop is an integer greater than or equal to 0. The control method further includes: refreshing a pre-defined portion in the unselected region, wherein a capacity of the pre-defined portion is determined by the number of times of performing the erasing loop.

Abstract: Discussed herein are systems and methods for charging a bit line (BL) during programming of non-volatile memory cells. An embodiment of a memory device comprises a group of memory cells including a first memory cell coupled to a first BL and a second memory cell coupled to a second BL, and a BL charging circuit that provides an inhibit signal to the second BL in response to a control signal to program the first memory cell. To provide the inhibit signal, the BL charging circuit apply a supply voltage to the second BL for an initial wait time and, after the initial wait time, apply a higher voltage than the supply voltage, until the inhibit signal reaches a value of the supply voltage. The first memory cells is programmed in response to the established voltage on the second BL.

Abstract: Methods, systems and apparatus including computer-readable mediums for rearranging data for refresh operations in memory systems such as NAND flash memory devices are provided. In one aspect, a method includes: determining that a particular logical page in a logical block fails based on error bits in a particular physical page that is in a first physical block mapped with the logical block and corresponds to the particular logical page, logical pages in the logical block being mapped to physical pages in the first physical block with an initial mapping order, and executing a refresh operation on the first physical block with a rearranged mapping order for the logical block, the rearranged mapping order being different from the initial mapping order. For the refresh operation, the logical pages in the logical block are mapped to physical pages in a second physical block with the rearranged mapping order.

Abstract: Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages having an refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.

Abstract: A data storage apparatus and a method for preventing data error using the same are provided. The data storage apparatus includes a memory and a memory controller. The memory includes a plurality of blocks. The memory controller is coupled to the memory and configured to perform the following operations: recording a read count of a target block of the memory; performing an error bit check on a free storage space of the target block when the read count of the target block meets a condition; and programming a dummy data to the free storage space of the target block in response to the determination that the check result is negative.

Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.

Abstract: Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.