Line Charging (e.g., Precharge, Discharge, Refresh) Patents (Class 365/185.25)
  • Patent number: 11226772
    Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: January 18, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Mark Murin, Hua-Ling Cynthia Hsu, Tomer Eliash, Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 11211392
    Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 28, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Sarath Puthenthermadam, Yanli Zhang, Huai-yuan Tseng, Peng Zhang
  • Patent number: 11205487
    Abstract: A memory device includes drain select lines, source select lines, a plurality of word lines arranged between the drain select lines and the source select lines, and a peripheral circuit configured to perform a program operation on selected memory cells connected to a selected word line among the plurality of word lines. The peripheral circuit includes a voltage generator configured to generate a voltage for initializing a channel of a plurality of memory cells respectively connected to the plurality of word lines in a program phase among a plurality of phases included in the program operation.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Hee Joo Lee
  • Patent number: 11200944
    Abstract: A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: December 14, 2021
    Assignee: SK hynix Inc.
    Inventors: Joon Woo Choi, Chang Ki Baek
  • Patent number: 11114168
    Abstract: A sense circuit of a memory cell includes a first switch, a sense node, a third switch, a connection node, a fourth switch, and a memory cell coupled in series. A boost driver is coupled to the sense node. A second switch and the connection node are coupled in series. The boost driver outputs a first voltage when the first, second, third, fourth switches are turned on. The third switch is then turned off and the boost driver outputs a second voltage higher than the first voltage such that the voltage level at the sense node is not higher than a system voltage. The third switch is turned on, then turned off and the boost driver outputs an intermediate voltage between the first voltage and the second voltage. A state of the memory cell is determined during output of the intermediate voltage.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: September 7, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Ke Liang, Liang Qiao, Chunyuan Hou
  • Patent number: 11087858
    Abstract: A memory device comprises, on an integrated circuit or multi-chip module, a memory including a plurality of memory blocks, a controller, and a refresh mapping table in non-volatile memory accessible by the controller. The controller is coupled to the memory to execute commands with addresses to access addressed memory blocks in the plurality of memory blocks. The refresh mapping table has one or more entries, an entry in the refresh mapping table mapping of an address identifying an addressed memory block set for refresh to a backup block address. The controller is responsive to a refresh command sequence with a refresh block address to execute a refresh operation, and is configured to restore mapping of the refresh block address to the backup block address upon power-on of the device, to scan the refresh mapping table for a set entry, and to register the set entry in the refresh mapping table.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: August 10, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shuo-Nan Hung, Chun-Lien Su
  • Patent number: 11061583
    Abstract: An electronic device includes a non-volatile memory and a controller. The controller receives data to be written to the non-volatile memory and determines a type of the data. Based on the type of the data, the controller selects a given duration of the data from among multiple durations of the data in the non-volatile memory. The controller sets values of one or more parameters for writing the data to the non-volatile memory based on the given duration. The controller writes the data to the non-volatile memory using the values of the one or more write parameters.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: July 13, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Andrew G. Kegel, Steven E. Raasch
  • Patent number: 11062782
    Abstract: Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes a plurality of memory decks each including a plurality of memory layers in a vertical direction, and a plurality of first dummy memory layers between the first and second memory decks in the vertical direction. Each memory layer in a first memory deck of the plurality of memory decks is first programmed. The first programming includes applying a program voltage to the memory layer and a channel pass voltage smaller than the program voltage to each of the rest of the memory layers in the first memory deck. Each memory layer in a second memory deck of the plurality of memory decks above the first memory deck is second programmed. The second programming includes applying the program voltage to the memory layer and the channel pass voltage to each of the rest of the memory layers in the second memory deck.
    Type: Grant
    Filed: November 21, 2020
    Date of Patent: July 13, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Ming Wang, Hong Tao Liu, Yali Song
  • Patent number: 11024371
    Abstract: When programming a memory device which includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, coarse programming is perform on two adjacent first and second word lines among the plurality of word lines. Next, an unselected bit line among the plurality of bit lines is pre-charged during a first period after performing the coarse programming on the first word line and the second word line. Also, the channel between the unselected bit line and the second word line is turned on at the start of the first period and turned off prior to the end of the first period. Then, fine programming is performed on the first word line during a second period subsequent to the first period.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: June 1, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Ying Cui, Jianquan Jia, Kaikai You
  • Patent number: 10998065
    Abstract: A memory device includes a memory cell block including a plurality of memory cells. The memory device also includes peripheral circuits configured to perform an erase operation by a gate induce drain leakage (GIDL) method by applying a first erase voltage and a second erase voltage to a source line of the memory cell block. The memory device further includes control logic configured to control the peripheral circuits to sequentially perform an operation of applying the first erase voltage and an operation of applying the second erase voltage during the erase operation, wherein memory cells having a plurality of program states, among the plurality of memory cells, are erased to have a pre-erase state during the operation of applying the first erase voltage.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventor: Hae Soon Oh
  • Patent number: 10998053
    Abstract: A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Jung Hwan Lee, Jung Mi Ko, Ji Hwan Kim, Kwang Ho Baek, Young Don Jung
  • Patent number: 10971234
    Abstract: Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Jung Hwan Lee, Jung Mi Ko, Ji Hwan Kim, Kwang Ho Baek, Young Don Jung
  • Patent number: 10950306
    Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Byung In Lee, Hee Joung Park, Keon Soo Shim, Sang Heon Lee, Jae Il Tak
  • Patent number: 10950307
    Abstract: A semiconductor memory device includes memory cells, a first circuit that includes a first latch group including first and second data latch circuits and a second latch group including third and fourth data latch circuits, and a control circuit configured to control a write operation during which first and second data to be written into the memory cells are stored in the first and second data latch circuits, respectively, wherein the first and second data are also stored in the third and fourth data latch circuits, respectively, while the first and second data stored in the first and second data latch circuits, respectively, are being written in the memory cells.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 16, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Naoya Tokiwa
  • Patent number: 10950310
    Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ting Luo, Kulachet Tanpairoj, Harish Reddy Singidi, Jianmin Huang, Preston Allen Thomson, Sebastien Andre Jean
  • Patent number: 10910021
    Abstract: Disclosed is a semiconductor device in which an internal voltage fluctuation when a current jump occurs is restrained. The semiconductor device includes a plurality of blocks, each of which performs a given operation, and a current jump control circuit. The current jump control circuit monitors control signals in each of the blocks and calculates predicted values of consumption current of the blocks, based on results of monitoring at different timings, thereby controlling a fluctuation of consumption current of the blocks. The current jump control circuit controls operation of a subset or all of the blocks, if an increase of a predicted value of consumption current of the blocks is larger than a first value or a decrease of the predicted value is larger than a second value.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: February 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Naoshi Ishikawa
  • Patent number: 10902927
    Abstract: Apparatus and methods are provided, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are provided.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 10892023
    Abstract: Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes memory decks each including memory layers in a vertical direction. Each memory layer in a first memory deck is first programmed. The first programming includes applying a program voltage to the memory layer and a first channel pass voltage smaller than the program voltage to each rest of the memory layers. Each memory layer in a second memory deck above the first memory deck is second programmed. The second programming includes applying the program voltage to the memory layer and the first channel pass voltage to each rest of the memory layers. The second programming further includes applying a second channel pass voltage smaller than the first channel pass voltage to each memory layer in the first memory deck.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: January 12, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Ming Wang, Hong Tao Liu, Yali Song
  • Patent number: 10867664
    Abstract: A sense amplifier includes a sense circuit coupled to a bitline and a sense node, a charge circuit coupled to the sense node and the sense circuit, a first current control transistor, an inverter circuit having a first latch node and a second latch node, coupled to the first current control transistor, and an input circuit coupled to the first latch node, the second latch node and the sense node. The first current control transistor includes a first terminal coupled to the system voltage source, a second terminal coupled to the inverter circuit, and a control terminal configured to receive a current control signal. The first current control transistor is a P-type transistor.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: December 15, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Min She, Qiang Tang
  • Patent number: 10838806
    Abstract: A solid state storage system, and method of operation thereof, including: a system interface configured to receive host commands; a controller, coupled to the system interface, configured to identify frequently read data blocks from the host commands; a non-volatile memory, coupled to the controller, configured for access of the frequently read data blocks; an error correction code unit, coupled to the controller, configured to provide health monitor parameters for the frequently read data blocks verified by the controller; and a redundant frequently read data (RFRD) area, coupled to the error correction code unit, configured to transfer a recovered data from the frequently read data blocks.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: November 17, 2020
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Fong-Long Lin, Shu-Cheng Lin
  • Patent number: 10803957
    Abstract: Discussed herein are systems and methods for charging a bit line (BL) during programming of non-volatile memory cells. An embodiment of a memory device comprises a group of memory cells including a first memory cell coupled to a first BL and a second memory cell coupled to a second BL, and a BL charging circuit that provides an inhibit signal to the second BL in response to a control signal to program the first memory cell. To provide the inhibit signal, the BL charging circuit apply a supply voltage to the second BL for an initial wait time and, after the initial wait time, apply a higher voltage than the supply voltage, until the inhibit signal reaches a value of the supply voltage. The first memory cells is programmed in response to the established voltage on the second BL.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 10802962
    Abstract: A memory device and a control method for a non-volatile memory are provided. The non-volatile memory includes a target erasing region and an unselected region. The control method includes: erasing a target memory cell in the target erasing region. The unselected region is a region, excluding the target erasing region, in the non-volatile memory. The step of erasing the target memory cell includes an erasing operation, a verification operation, and an erasing loop after failing to pass the verification operation. The number of times of performing the erasing loop is an integer greater than or equal to 0. The control method further includes: refreshing a pre-defined portion in the unselected region, wherein a capacity of the pre-defined portion is determined by the number of times of performing the erasing loop.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 13, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Chung-Meng Huang
  • Patent number: 10795770
    Abstract: Methods, systems and apparatus including computer-readable mediums for rearranging data for refresh operations in memory systems such as NAND flash memory devices are provided. In one aspect, a method includes: determining that a particular logical page in a logical block fails based on error bits in a particular physical page that is in a first physical block mapped with the logical block and corresponds to the particular logical page, logical pages in the logical block being mapped to physical pages in the first physical block with an initial mapping order, and executing a refresh operation on the first physical block with a rearranged mapping order for the logical block, the rearranged mapping order being different from the initial mapping order. For the refresh operation, the logical pages in the logical block are mapped to physical pages in a second physical block with the rearranged mapping order.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: October 6, 2020
    Assignees: Macronix International Co., Ltd., MegaChips Corporation
    Inventors: Yuchih Yeh, Naping Kuo, Yuko Tamagawa
  • Patent number: 10748598
    Abstract: Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages having an refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Ameen D. Akel
  • Patent number: 10714193
    Abstract: A data storage apparatus and a method for preventing data error using the same are provided. The data storage apparatus includes a memory and a memory controller. The memory includes a plurality of blocks. The memory controller is coupled to the memory and configured to perform the following operations: recording a read count of a target block of the memory; performing an error bit check on a free storage space of the target block when the read count of the target block meets a condition; and programming a dummy data to the free storage space of the target block in response to the determination that the check result is negative.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: July 14, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Yu-Hsuan Cheng
  • Patent number: 10691377
    Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Peter Sean Feeley, Ashutosh Malshe, Renato Padilla, Jr., Kishore Kumar Muchherla, Sampath Ratnam
  • Patent number: 10685721
    Abstract: Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 10679705
    Abstract: A controller controls a semiconductor memory device including a plurality of memory blocks. The controller may include a controller control unit and a storing unit. The controller control unit compares the number of times of a read of an original memory block among the plurality of memory blocks with a predetermined copy generation reference value, determines whether to generate copy data of original data stored in the original memory block, and generates a command corresponding to the determination. The storage unit stores the copy generation reference value and address information about the original memory block.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Geu Rim Lee, Young Gyun Kim
  • Patent number: 10615170
    Abstract: A semiconductor memory device, including: a substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate; a channel semiconductor layer extending in the first direction and including a first portion facing the plurality of the first conductive layers and a second portion further from the substrate than the first portion; a memory layer arranged between the first portion of the channel semiconductor layer and the plurality of the first conductive layers and including a memory part capable of storing data; and a first semiconductor layer connected to the second portion of the channel semiconductor layer, the first semiconductor layer including crystalline semiconductor containing a first impurity, and the channel semiconductor layer including a crystal grain having a crystal grain size larger than a thickness thereof.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuya Maeda, Hidenori Miyagawa
  • Patent number: 10600453
    Abstract: A memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including the plurality of memory cells, and a driving determination unit determining whether to perform at least one of a pre-charging operation, a development operation and a latching operation of page buffers connected to the memory cells provided with the read voltage.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: March 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han Jun Lee, Dong Hun Kwak, Yo Han Lee
  • Patent number: 10599346
    Abstract: A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device. The non-volatile semiconductor memory device can store data in memory blocks. The solid-state drive controller can, periodically, retrieve counts from a counter table, select a predetermined number of memory blocks corresponding to the lowest counts, and determine an integrity of the stored data in each of the predetermined number of memory blocks. Each count can correspond to a difference between a count limit and a number of read operations performed on one of the memory blocks.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: March 24, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Neil Buxton
  • Patent number: 10553292
    Abstract: A memory system includes a storage medium including a memory region group having a plurality of memory regions; a memory configured to store a plurality of region read counts respectively corresponding to the plurality of memory regions and a group read count corresponding to the memory region group; a count management circuit configured to, when a first memory region among the plurality of memory regions is read-accessed, based on a first region read count corresponding to the first memory region among the plurality of region read counts, increase the group read count and reduce remaining region read counts other than the first region read count among the plurality of region read counts; and a reliability management circuit configured to perform a reliability management operation for the memory region group, based on the group read count.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Yong Il Jung, Dae Seok Shin
  • Patent number: 10541033
    Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Taeck Jung, Sang-Wan Nam, Jinwoo Park, Jaeyong Jeong
  • Patent number: 10510419
    Abstract: Discussed herein are systems and methods for charging a bit line (BL) during programming of non-volatile memory cells. An embodiment of a memory device comprises a group of memory cells including a first memory cell coupled to a first BL and a second memory cell coupled to a second BL, and a BL charging circuit that provides an inhibit signal to the second BL in response to a control signal to program the first memory cell. To provide the inhibit signal, the BL charging circuit apply a supply voltage to the second BL for an initial wait time and, after the initial wait time, apply a higher voltage than the supply voltage, until the inhibit signal reaches a value of the supply voltage. The first memory cells is programmed in response to the established voltage on the second BL.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 10468110
    Abstract: A semiconductor memory device includes a cell string, a common source line controller, and a page buffer. The cell string includes a plurality of memory cells coupled in series between a common source line and a bit line. In a read operation, the common source line controller provides a channel current to the cell string through the common source line. The page buffer senses data stored in a selected memory cell among the plurality of memory cells by sensing a current of the bit line when the channel current is provided. The common source line controller precharges the bit line by providing the channel current to the cell string through the common source line. After the bit line is precharged, the page buffer senses the data stored in the selected memory cell by transmitting a voltage of the bit line to a sensing node.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: November 5, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10446243
    Abstract: A control method for a storage device is provided. The storage device includes a memory controller and a flash memory. The flash memory includes multiple blocks. The control method includes the following steps. Maintain a state table by the memory controller, wherein the state table records a disturbance count and a last check time of the blocks in the flash memory. Trigger a probe operation on a target block in the flash memory when at least one of the following conditions is met: (a) the disturbance count of the target block is greater than or equal to a disturbance count threshold; and (b) an elapsed time period of the target block is greater than or equal to an elapsed time threshold, wherein the elapsed time period of the target block starts from the last check time of the target block.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 15, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Tzu-Yi Yang, Yung-Sheng Chen
  • Patent number: 10446247
    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Noboru Shibata
  • Patent number: 10395742
    Abstract: A memory cell of a split gate type MONOS memory is formed over a plate-shaped fin being a part of a semiconductor substrate. In a data erase operation, in a selected memory cell on which erasing is performed, a drain region is applied with 0 V, a memory gate electrode is applied with a positive voltage, and accordingly, erasing is performed by the FN mechanism. Also, in the data erase operation, in an unselected memory cell on which the erasing is not performed, connected to the same memory gate line as the above-described selected memory cell, the drain region is in an open state, and the memory gate electrode is applied with the positive voltage, whereby an induced voltage region is generated in a channel region. Thus, a potential difference between the channel region and the memory gate electrode is small, and accordingly, the erasing is not performed.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: August 27, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tomoya Saito
  • Patent number: 10347765
    Abstract: A method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may further include forming a split fin structure from the substrate. The metal nitride is positioned in the split portion of the fin structure. The method may continue with removing the metal nitride from a source region and drain region portion of the split fin structure, in which the metal nitride remains in a channel region portion of the split fin structure. A gate structure may then be formed on a channel region portion of the fin structure. A back bias is applied to the semiconductor device using the metal nitride in the split portion of the fin structure as an electrode.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Xin Miao, Tenko Yamashita
  • Patent number: 10282105
    Abstract: Methods, systems and computer program products for extending the shelf life of non-volatile memory devices, aspects of which include detecting that the non-volatile memory device has been disconnected from a power supply and responsively resetting a timer, a first counter, and a second counter and incrementing the first counter and the second counter based on the timer. Based on a determination that the first counter has reached a first threshold value, aspects also include initiating a wireless charging a battery of the non-volatile memory device. Based on a determination that the second counter has reached a second threshold value, aspects also include initiating a refresh of a non-violate memory of the non-volatile memory device. Based on a determination that the refresh of the non-violate memory of the non-volatile memory device has been completed, aspects also include resetting the timer, the first counter, and the second counter.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prashanth K. Kasula, Trinadhachari Kosuru, Adam J. McPadden, Preetham H. Raghavendra, Janani Swaminathan
  • Patent number: 10255967
    Abstract: A memory device may include voltage regulation circuitry configured to supply a voltage signal between a high signal and a low signal. The memory device may include a first data line configured to provide a first charge to the voltage regulation circuitry during a first mode of operation of the memory device. The memory device may include a second data line configured to draw a second charge from the voltage regulation circuitry to control a voltage on the second data line during a second mode of operation of the memory device.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Harish N. Venkata
  • Patent number: 10223285
    Abstract: A data storage device utilized for storing at least one data includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks has a different respective physical address. The controller is coupled to the memory for mapping the physical addresses to a plurality of logical addresses. After the controller receives a conversion-requesting instruction, it converts a specific logical address from being mapped to a first physical address to being mapped to a second physical address.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: March 5, 2019
    Assignee: Silicon Motion, Inc.
    Inventor: Ya-Sung Chang
  • Patent number: 10170190
    Abstract: A method of controlling the operation of a memory controller includes, in a read operation of a non-volatile memory device, the memory controller counting a selected read count of a selected string in a selected memory block and/or counting a non-selected read count of a non-selected string in the selected memory block. The memory controller performs a reclaim operation of the selected memory block when the selected read count and/or the non-selected read count exceeds a read threshold. To move data of the selected memory block to another memory block by the reclaim operation, the memory controller may copy the data of the selected memory block to another block by using a changed page address.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: January 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Dae-Seok Byeon, Chi-Weon Yoon, Hae-Suk Shin
  • Patent number: 10170192
    Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: June-Hong Park, Ki-Whan Song, Bong-Soon Lim, Su-Chang Jeon, Jin-Young Kim, Chang-Yeon Yu, Dong-Kyo Shim, Seong-Jin Kim
  • Patent number: 10157680
    Abstract: Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one example, for a NAND string with 32 memory cell transistors corresponding with word lines WL0 through WL31 from the source-side end of the NAND string to the drain-side end of the NAND string, the memory cell transistor corresponding with word line WL16 may be programmed and program verified prior to programming the memory cell transistors corresponding with word lines WL15 and WL17.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: December 18, 2018
    Assignee: SANDISK TECHNOLOGIES LLP
    Inventors: Xiang Yang, Huai-Yuan Tseng, Xiaochang Miao, Deepanshu Dutta
  • Patent number: 10127985
    Abstract: A semiconductor memory device includes first and second memory cells, first and second word lines that are connected to the first and second memory cells, respectively, a first transistor connected to one end of the first word line, and second and third transistors respectively connected to first and second ends of the second word line. During a read operation on the first and second memory cells, when the first word line is selected, a first voltage is applied to the second word line, and then a second voltage is applied to the first word line, and when the second word line is selected, the first voltage is applied to the first word line, and then the second voltage is applied to the second word line. The second voltage is applied to the first word line for a longer duration than is applied to the second word line.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masashi Yamaoka
  • Patent number: 10121519
    Abstract: A semiconductor device includes a connector configured for connection to a host, a power circuit supplied with a first voltage from the host via the connector, the power circuit including first and second channels configured to generate second and third voltages, respectively, from the first voltage, a semiconductor memory supplied with the second voltage via the first channel, and a controller for the semiconductor memory, supplied with the third voltage via the second channel. When the first voltage is less than a first threshold, the power circuit turns off the first channel and the second channel.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: November 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Toyokazu Eguchi, Hajime Matsumoto
  • Patent number: 10108366
    Abstract: A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned a group read-count value. An adjustment of the group read-count values is triggered by a read command of a host. When one read-count value of the group read-count values exceeds a preset range, the controller performs a scan operation to non-volatile storage blocks of the non-volatile storage circuit corresponding to a corresponding logical block address group of the read-count value, so as to check a number of error bits. The controller decides whether to perform a storage block data-moving operation to the non-volatile storage block corresponding to the corresponding logical block address group based on results of the scan operation.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 23, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Sheng-Huei Huang, Yi-Lin Lai
  • Patent number: 10049752
    Abstract: In one embodiment, an apparatus comprises a memory array; a sense circuit comprising a first transistor and a sense node coupled to the first transistor and selectively coupled to a memory cell of the memory array via a data line; and a tracking circuit comprising a second transistor having a threshold voltage that is to track a threshold voltage of the first transistor, the tracking circuit to generate at least one sensing parameter of the sense circuit based on the threshold voltage of the second transistor.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Qiang Tang, Kalyan C. Kavalipurapu
  • Patent number: 10032787
    Abstract: A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoocheol Shin, Hongsoo Kim, Jaesung Sim