Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including periodically, at a predefined frequency, incrementing a value stored in an accumulator by a composite parameter value; responsive to receiving a program request specifying a data item to be programmed to a management unit of the memory device, obtaining a first value from the accumulator; storing the first value to a program reference table; programming the data item to the management unit; responsive to receiving a read request specifying the management unit, obtaining a second value from the accumulator; determining a read voltage value based on a difference of the first value and the second value; and performing a read operation, using the read voltage value, on the management unit.

Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

Abstract: Disclosed is a sense circuit with first and second branches connected to first and second inputs of an amplifier. The first branch includes series-connected first transistors between a voltage rail and a data line and a first node between two first transistors and connected to the first input. First transistors on either side of the first node receive corresponding gate bias voltages. The second branch includes series-connected second transistors between the voltage rail and a reference device and a second node between two second transistors and connected to the second input. One first transistor and one second transistor share a common control signal. The first and second branches independently and concurrently generate data and reference voltages on the first and second nodes and the difference between them is sensed by the amplifier. Also disclosed are a non-volatile memory structure incorporating the sense circuit and a method.

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

Abstract: A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or prevent Vt distribution window degradation, particularly for relatively low physical word lines. Additionally, the overall programming time and average current consumed can also be reduced.

Abstract: An information processing apparatus has strings connected to a first wiring and connected to second wirings. The string has one end connected to the first wiring and includes transistors being connected to each other, gates of which are connected to the second wirings. The transistors include a first transistor and a second transistor. The first transistor is set to a first threshold according to first data, and the second transistor is set to a second threshold according to second data in a complement relationship with the first data. Two second wirings of the second wirings are connected to gates of the first transistor and the second transistor, and one of the two second wirings is set to a potential level corresponding to third data, and another is set to a potential level corresponding to fourth data in a complement relationship with the third data.

Abstract: A memory system including a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The plurality of memory cells are arranged in rows and columns, each of the plurality of memory cells having a gate, a drain, and a source. In the plurality of word lines, each of the word lines having a corresponding row, wherein each of the word lines is coupled to the gates of the memory cells in the corresponding row. In the plurality of bit lines and the plurality of source lines, each of the bit lines and each of the source lines having a corresponding column, where each of the bit lines is connected to the drain of the memory cells in the corresponding column and each of the source lines is connected to the source of the memory cells in the corresponding column.

Abstract: A memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to perform an incremental step pulse program (ISPP) on the plurality of memory cells. The control logic is configured to control the peripheral circuit to perform the ISPP using bit line voltages set based on different bit line step voltages according to a target program state of each of the plurality of memory cells among a plurality of program states.

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, memory cell lines connecting respective lines of memory cells, and a page buffer circuit including page buffers coupled to the memory cell lines. Each page buffer includes a sensing latch circuit and a storage latch circuit. The sensing latch circuit includes a sensing transistor coupled to a sensing node and at least one sensing latch unit having a first node coupled to the sensing node and a second node coupled to a first terminal of the sensing transistor. The storage latch circuit includes at least one storage latch unit having third and fourth nodes coupled to the sensing node and a gate terminal of the sensing transistor. A second terminal of the sensing transistor is coupled to a ground.

Abstract: A processing device of a memory sub-system is configured to perform a plurality of write operations on a memory device comprising a plurality of memory units; responsive to performing each write operation on a respective first memory unit of the memory device, the processing device is configured to identify a candidate memory unit that has been written to by a at least a threshold fraction of the plurality of write operations performed on the memory device; determine whether a threshold refresh criterion is satisfied; and responsive to determining that the threshold refresh criterion is satisfied, refresh data stored at one or more of the memory units that are proximate to the candidate memory unit.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a health of a plurality of wordlines of a block of a plurality of blocks, receive key value (KV) pair data, select a wordline of the plurality of wordlines based on the health, and program the KV pair data to the selected wordline. The KV pair data includes a value length and a relative performance indicator. The controller is further configured to mark a block of the plurality of blocks due to a high bit error rate (BER) indication, where the marked block is KV operable only. The non-KV pair data stored in the marked block is relocated to a non-marked block.

Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.

Abstract: The invention provides a semiconductor device and a continuous reading method for suppressing fluctuations of a precharging voltage caused by an increase in a precharging time. The continuous reading method of a NAND flash memory of the invention includes the following steps: a first voltage (VCLMP1+Vth) is applied to a gate of a transistor (BLCLAMP) connected to a bit line and a voltage is supplied to the bit line via the transistor (BLCLAMP) to start precharging of the bit line; and a second voltage (VCLMP1+Vth??) lower than the first voltage is applied to the gate of the transistor (BLCLAMP) when the precharging time caused by the application of the first voltage has elapsed for a certain period of time.

Abstract: A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured to, if the at least one memory string passes the erase-verify test, inhibit the at least one memory string for erase including ramping up, to an erase voltage, of a voltage applied to a gate of a SGD transistor of the at least one memory string and to perform a next erase-verify iteration in the erase operation for remaining memory strings of the plurality of memory strings other than the at least one memory string.

Abstract: Methods of operating a memory device are disclosed. A method may include receiving a write command, and in response to the write command, performing a write operation without precharging a local input/output line subsequent to receipt of the write command and prior to performing the write operation. Another method may include receiving a read command, performing a read operation in response to the read command, and receiving an additional command without precharging the local input/output line subsequent to performing the read operation and prior to receiving the additional command. Memory devices and systems are also disclosed.

Abstract: A memory device includes memory cells in rows, word lines respectively coupled to the rows, and a control circuitry coupled to the memory cells via the word lines. The control circuitry is configured to apply a first program voltage to a first word line of the word lines. The first word line is coupled to a first row of the memory cells. The control circuitry is also configured to, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines. The second word line is coupled to a second row of the memory cells. The control circuitry is also configured to, after applying the second program voltage to the second word line, apply a first pre-charge voltage to the first word line and a second pre-charge voltage to the second word line. The second pre-charge voltage is greater than the first pre-charge voltage.

Abstract: A memory controller controls a memory device including a plurality of memory blocks. The memory controller is configured to: control the memory device to store data in a first area among areas of the memory device using a single level cell method, wherein the data are corresponded to a write booster request which is received from a host, perform a wear leveling operation, based on a size of the data stored in the first area, a program-erase count of each of memory blocks of the first area, and a number of free blocks in the memory device and form a mapping relationship between a logical block address, which is received from the host, and a physical block address corresponding the first area.

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

Abstract: Provided herein may be a memory device having a page buffer. The memory device may include a memory cell configured to store data, and a page buffer coupled to the memory cell through a bit line and configured to store data to be used in a program operation and to precharge the bit line to a first precharge voltage or a second precharge voltage lower than the first precharge voltage depending on the data during a program verify operation performed in the program operation.

Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

Abstract: A memory device comprising: a plurality of memory blocks each including a plurality of word lines arranged between a first and second select line, a peripheral circuit performs an erase operation by applying an erase voltage to a source or drain line of a selected memory block, and a control logic controls, in a period in which the erase operation is performed, the peripheral circuit to: sequentially select the plurality of word lines included in the selected memory block at least one by one from a word line closest to the first and second select line to a word line farthest from the first and second select line, apply a first erase permission voltage to the selected word lines, and apply a second erase permission voltage, which have a higher potential level than the first erase permission voltage, to remaining word lines except the selected word lines.

Abstract: A semiconductor memory device includes a memory block, and control logic. The memory block includes a plurality of memory cells. The control logic controls a peripheral circuit to perform a read operation on selected memory cells among the plurality of memory cells. The read operation includes a bit line precharge operation, an evaluation operation, and a sensing operation. The control logic is configured to control the peripheral circuit to float a common source line coupled to the memory block during at least a partial period of a period of the bit line precharge operation, in which a voltage of a plurality of bit lines coupled to the memory block increases.

Abstract: Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.

Abstract: A memory device for performing temperature compensation and an operating method thereof are provided. The memory device includes a memory cell array; a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a page buffer connected to each of the plurality of bit lines, and configured to perform a pre-charge operation during a pre-charge period for data reading; and a control logic configured to differently control the pre-charge operation of the page buffer circuit according to a detected temperature, wherein the pre-charge period includes a first period in which the plurality of bit lines are overdriven and a second period in which the plurality of bit lines are driven at a voltage lower than that of the first period, and the first period where the detected temperature is a first temperature is set to be shorter than the second period where the detected temperature is a second temperature higher than the first temperature.

Abstract: A circuit includes a linear regulator coupled with a memory array and a pump regulator coupled with a charge pump, the charge pump to provide a supply voltage to the linear regulator. A digital-to-analog converter (DAC) has an output coupled with the pump regulator. Control logic is coupled with the DAC and is to perform operations including causing a digital input value to be provided to the DAC to selectively adjust the supply voltage based on a programmable offset value.

Abstract: Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.

Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.

Abstract: The present technology relates to an electronic device. A memory device configured to perform a sensing operation based on a charge degree of a sensing node includes a memory cell array including a plurality of memory cells, a peripheral circuit including a page buffer connected to a selected memory cell among the plurality of memory cells through a bit line, and configured to perform a sensing operation on the selected memory cell, and control logic configured to control the peripheral circuit to precharge a source line among lines connected to the memory cell array and perform the sensing operation based on a degree at which a sensing node in the page buffer is charged, during the sensing operation.

Abstract: Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.

Abstract: Apparatus having a string of series-connected memory cells, a plurality of access lines with each access line of the plurality of access lines connected to a control gate of a respective memory cell of the plurality of memory cells, and a controller for access of the string of series-connected memory cells and configured to cause the memory to increase a threshold voltage of a particular memory cell of the string of series-connect memory cells to a voltage level higher than a predetermined pass voltage to be received by a control gate of the particular memory cell during a read operation on the string of series-connected memory cells, and concurrently change a respective data state of each memory cell of a plurality of memory cells of the string of series-connected memory cells.

Abstract: Methods of operating a memory device are disclosed. A method may include receiving a write command, and in response to the write command, performing a write operation without precharging a local input/output line subsequent to receipt of the write command and prior to performing the write operation. Another method may include receiving a read command, performing a read operation in response to the read command, and receiving an additional command without precharging the local input/output line subsequent to performing the read operation and prior to receiving the additional command. Memory devices and systems are also disclosed.

Abstract: Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times.

Abstract: A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer.

Abstract: A memory device, and a method of operating the same, includes a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells. The memory device also includes a peripheral circuit configured to perform a sensing operation of sensing selected memory cells coupled to a selected word line selected from among the plurality of word lines. The memory device further includes control logic configured to control the peripheral circuit apply a turn-on voltage to a block word line coupled to the selected word line when the sensing operation is terminated and when potentials of the plurality of word lines are increased due to a recovery operation for channels of the plurality of memory cells after the plurality of word lines have been discharged.

Abstract: Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.

Abstract: The present technology relates to an electronic device. A memory device capable of reducing a time consumed in a program operation includes a memory cell array, a page buffer group connected to the memory cell array through a plurality of bit lines and a voltage generator configured to generate voltages to apply to each of a plurality of page buffers included in the page buffer group. Each of the plurality of page buffers includes a precharge circuit that controls potential levels of the plurality of bit lines to be maintained at precharge levels.

Abstract: A method of peak power management (PPM) for a memory chip with multiple memory dies is provided, where each of the multiple memory dies includes a PPM circuit having a PPM contact pad and PPM contact pads of the multiple memory dies are electrically connected. The PPM method includes the following steps: switching on a pull-down driver of the PPM circuit on a selected memory die of the memory chip; verifying a PPM enablement signal regulated by a pull-down current flowing through the pull-down driver; and performing a peak power operation on the selected memory die when the PPM enablement signal indicates that a total current of the memory chip is less than a maximum total current allowed for the memory chip.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.

Abstract: A circuit includes a linear regulator operatively coupled with a memory array, the linear regulator including a primary switch to generate a regulated voltage usable to program memory cells of the memory array. A first digital-to-analog converter (DAC) includes an output coupled with the linear regulator. A pump regulator is operatively coupled with a charge pump, where the charge pump is to provide a supply voltage to the linear regulator. A second DAC includes an output coupled with the pump regulator. Control logic, operatively coupled with the first DAC and the second DAC, is to perform operations including: causing a first digital input value to be provided to the first DAC to selectively smooth noise on the supply voltage; and causing a second digital input value to be provided the second DAC to selectively adjust the supply voltage based on a programmable offset value.

Abstract: A memory device and method of operating the same. A memory device includes a memory block, a peripheral circuit, and a program operation controller. The memory block includes a first sub block connected to a first drain select line and a first source select line, and a second sub block connected to a second drain select line and a second source select line, and each of the first sub block and the second sub block is connected to a plurality of word lines and a common source line. The program operation controller controls the peripheral circuit to transfer a precharge voltage to the channel region through the common source line or a plurality of bit lines connected the memory block, and to apply a control voltage to the first and second source select lines at different time points or to apply the control voltage to the first and second drain select lines at different time points in the step of precharging the channel region.

Abstract: A program method for a memory device is provided. The memory device includes a plurality of memory cells, a bit line and word lines electrically connected to the plurality of memory cells. The plurality of memory cells includes a selected memory cell and unselected memory cells when the memory device is in a program operation. The program method including performing precharge steps, performing program steps and performing a verification step to the selected memory cell after the precharge steps and the program steps. Each of the precharge steps includes applying a precharge voltage to the bit line electrically connected to the unselected memory cells. Each of the program steps includes applying a program voltage to a word line of the word lines electrically connected to the selected memory cell.

Abstract: Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.

Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.

Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

Abstract: A memory device includes drain select lines, source select lines, a plurality of word lines arranged between the drain select lines and the source select lines, and a peripheral circuit configured to perform a program operation on selected memory cells connected to a selected word line among the plurality of word lines. The peripheral circuit includes a voltage generator configured to generate a voltage for initializing a channel of a plurality of memory cells respectively connected to the plurality of word lines in a program phase among a plurality of phases included in the program operation.

Abstract: A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line.