Tunnel Programming Patents (Class 365/185.28)
  • Patent number: 10438025
    Abstract: A memory device is disclosed. The memory device includes a memory bit array comprising a plurality of memory bits, wherein each memory bit is configured to present an initial logic state when the memory device is powered on, and an erasion circuit, coupled to the memory bit array, and configured to alter an intrinsic characteristic of at least one of the memory bits so as to alter the initial logic state of the at least one memory bit.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: October 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10325921
    Abstract: To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ONO film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ONO film) thicker than the ONO film is provided between the memory gate electrode and a top surface of the fin. This configuration can reduce concentration of an electric field onto a tip of the fin, so that deterioration of reliability of the ONO film can be prevented.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuyoshi Mihara
  • Patent number: 10325661
    Abstract: Methods of programming a memory include applying a programming voltage on an access line selected for a programming operation of a single page of the memory, applying a second voltage on an access line unselected for the programming operation, increasing the programming voltage for a first plurality of steps of the programming operation, and increasing the second voltage for a second plurality of steps of a first portion of the programming operation, then decreasing the second voltage at a particular point of the programming operation after completing the second plurality of steps and before completing the first plurality of steps.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yijie Zhao, Akira Goda
  • Patent number: 10262740
    Abstract: A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: April 16, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoki Nakagawa, Koji Hosono
  • Patent number: 10176998
    Abstract: A semiconductor device includes a substrate, a dielectric layer and a floating gate. The dielectric layer disposed on the substrate. The floating gate disposed on the dielectric layer. After a first programming process, the floating gate is configured to store first electrons that are to be combined with ions from the dielectric layer. After a second programming process, the floating gate is configured to store second electrons, and a number of the second electrons is larger than a number of the first electrons.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Wu, Meng-Chun Shih, Chin-Huang Wang
  • Patent number: 10141057
    Abstract: An erasing method of a single-gate non-volatile memory is provided. The single-gate non-volatile memory has a single floating gate. The erasing method includes applying a voltage to the drain without applying to the gate to create and control an inversion layer. Therefore the required erasing voltage is reduced and the erasing speed is improved to avoid the over-erase problem.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 27, 2018
    Assignee: Yield Microelectronics Corp.
    Inventors: Hsin-Chang Lin, Wen-Chien Huang, Wei-Tung Lo
  • Patent number: 10120579
    Abstract: Techniques for implementing a data management scheme for optimizing data storage are described herein. A deletion quantity or other metric relating to deletions of data within a first storage zone are tracked. Upon detection that the tracked deletion metric meets certain criteria, the data within the first storage zone are moved to a second storage zone. A verification of the data to be moved is also performed, and if such verification indicates that at least a portion of the data is corrupted, routines repairing and/or restoring at least the corrupted portion are initiated.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: November 6, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Kestutis Patiejunas, Colin L. Lazier, James Christopher Sorenson, III
  • Patent number: 10096602
    Abstract: Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: October 9, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE Pte. Ltd.
    Inventors: Shyue Seng Jason Tan, Kiok Boone Elgin Quek
  • Patent number: 9947687
    Abstract: A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: April 17, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Patent number: 9947375
    Abstract: Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 17, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Jae-Kwan Park
  • Patent number: 9917211
    Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: March 13, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Wei Zheng, Chi Chang, Unsoon Kim
  • Patent number: 9881930
    Abstract: A method that allows integrating complementary metal oxide semiconductor (CMOS) transistors and a non-volatile memory (NVM) transistor on a single substrate is provided. The NVM transistor includes a gate stack containing a high-k tunneling gate dielectric, a floating gate electrode, a high-k control gate dielectric and a control gate electrode. The high-k tunneling gate dielectric is formed form a first high-k dielectric layer employed in formation of a gate dielectric for a p-type field effect transistor (FET), the floating gate electrode is formed from a capping material layer employed in annealing the first high-k dielectric layer, and the high-k control gate dielectric is formed from a second high-k dielectric layer employed in formation of a gate dielectric for an n-type FET.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9842655
    Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (NVM). The program verify sequence can have one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified. The memory controller can detect an approximate percentage of memory cells for each program verify level in which data is successfully written. The memory controller can determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 12, 2017
    Assignee: Intel Corporation
    Inventors: Kalyan Kavalipurapu, Allahyar Vahidimowlavi, Erwin Yu
  • Patent number: 9837161
    Abstract: A memory is provided. The memory includes an array of non-volatile memory (NVM) cells arranged in a plurality sectors. A control gate driver circuit has an output coupled to control gates of the NVM cells in a sector in the plurality of sectors. An address decoder is coupled to the control gate driver circuit. And a latch circuit is coupled between the address decoder and the control gate driver circuit. The latch circuit stores a first value, and based on the stored first value, the control gate driver circuit output is floating.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: December 5, 2017
    Assignee: NXP USA, Inc.
    Inventors: Gilles Muller, Ronald J. Syzdek
  • Patent number: 9824764
    Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells that are NAND-connected; and a control circuit that executes a write sequence, the write sequence writing data to the memory cells, the write sequence including a plurality of write stages, one of the write stages applying to the memory cells a plurality of program pulses whose amplitudes increase by a certain increment, the write stages including 1st to Nth, where N is an integer of 2 or more, write stages, and an initial amplitude and the increment of the program pulse applied in the N?1th write stage being the same as an initial amplitude and the increment of the program pulse applied in the Nth write stage.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 21, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuki Kanamori, Yuji Nagai, Jun Nakai, Kenri Nakai
  • Patent number: 9817598
    Abstract: A memory device includes a first memory string including a first selection transistor and a first memory cell, a second memory string including a second selection transistor and a second memory cell, a bit line electrically connected to the first memory string and the second memory string, and a control circuit configured to perform a collective write operation on the first memory cell and the second memory cell by applying a voltage to turn on the first transistor, a voltage to turn on the second transistor, and then a program voltage at the same time to gates of the first and second memory cells.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: November 14, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Hidehiro Shiga, Masanobu Shirakawa, Tokumasa Hara
  • Patent number: 9805789
    Abstract: Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: October 31, 2017
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Gurtej S. Sandhu
  • Patent number: 9792993
    Abstract: A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: October 17, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching
  • Patent number: 9747995
    Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 29, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Il Shim, Jae-Hoon Jang, Donghyuk Chae, Youngho Lim, Hansoo Kim, Jaehun Jeong
  • Patent number: 9727570
    Abstract: Systems and methods are provided for unmapping unused logical addresses at mount-time of a file system. An electronic device, which includes a non-volatile memory (“NVM”), may implement a file system that, at mount-time of the NVM, identifies all of the logical addresses associated with the NVM that are unallocated. The file system may then pass this information on to a NVM manager, such as in one or more unmap requests. This can ensure that the NVM manager does not maintain data associated with a logical address that is no longer needed by the file system.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: August 8, 2017
    Assignee: APPLE INC.
    Inventors: Daniel J. Post, Eric Tamura, Vadim Khmelnitsky, Nir J. Wakrat, Matthew Byom
  • Patent number: 9703494
    Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to store a first page of data in a plurality of cells of the NAND flash memory in a first programming pass; and preserve the readability of the first page of data in the plurality of cells during a subsequent programming pass comprising a plurality of program loops, at least one of the plurality of program loops to comprise application of a first voltage to a first group of cells of the plurality of cells and application of a second voltage to a second group of cells of the plurality of cells, wherein the first group comprises cells that were not programmed in the first programming pass and the second group comprises cells that were programmed in the first programming pass.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Shantanu R. Rajwade, Pranav Kalavade
  • Patent number: 9685233
    Abstract: A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: June 20, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Chang Hsieh, Ti-Wen Chen, Yung Chun Li, Kuo-Pin Chang
  • Patent number: 9558837
    Abstract: A semiconductor memory device includes a memory cell array, a sense amplifier, a register, a controller. The memory cell array includes a memory cell. The sense amplifier connects to the bit line. The register holds write data, and a write voltage. The controller outputs a busy signal. The controller causes the register to hold the write data and the write voltage upon receiving the first command, and resumes the write operation based on the write data and the write voltage held in the register upon receiving the resumption command.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: January 31, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshikazu Harada, Akio Sugahara, Masahiro Yoshihara
  • Patent number: 9508733
    Abstract: A method of fabricating an embedded electronic device including charge trap memory cells that includes forming a tunnel insulation layer, a charge trap layer and a sacrificial insulation layer on a substrate having a first region and a second region. The tunnel insulation layer, the charge trap layer and the sacrificial insulation layer which are stacked on the second region of the substrate are selectively removed. A well region is formed in an upper region of the second region of the substrate. The sacrificial insulation layer remaining over the first region is removed to expose the charge trap layer remaining over the first region. A blocking insulation layer and a gate insulation layer are formed on the exposed charge trap layer over the first region and on the second region of the substrate, respectively.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: November 29, 2016
    Assignee: SK Hynix Inc.
    Inventors: Tae Ho Lee, Young Joon Kwon, Sung Kun Park
  • Patent number: 9502126
    Abstract: A method of operating a semiconductor memory device includes applying a read voltage to a selected word line on which a program operation is performed; applying a first pass voltage to at least one unselected word line adjacent to the selected word line; applying a second pass voltage to the at least one unselected word line when a first reference time elapses; and performing a read operation on memory cells connected to the selected word line according to the read voltage when a second reference time elapses.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: November 22, 2016
    Assignee: SK Hynix Inc.
    Inventor: Dong Hyun Kim
  • Patent number: 9477423
    Abstract: Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: October 25, 2016
    Assignee: Seagate Technology LLC
    Inventors: Yu Cai, Yunxiang Wu, Zhengang Chen, Erich Haratsch
  • Patent number: 9443930
    Abstract: A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: September 13, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junsoo Kim, Dongjin Lee, Dongsoo Woo, Jun-Bum Lee, Sang-Il Han
  • Patent number: 9437696
    Abstract: A semiconductor device includes a substrate having an element isolation region, a trench formed on the element isolation region, a gate electrode buried in the trench, and a plurality of active regions formed on both ends of the gate electrode, wherein a pin is formed under the gate electrode between the active regions.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: September 6, 2016
    Assignee: SK Hynix Inc.
    Inventors: Ji-In Kim, Do-Youn Kim
  • Patent number: 9437605
    Abstract: Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into word lines. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the layers. String select lines run above the conductive layers and define select gates of the pillars. Bit lines run above the SSLs. The pillars are arranged on a regular grid having a unit cell area ?, and adjacent ones of the string select lines have respective widths in the bit line direction which are at least as large as (?/pBL). Ground select lines run below the conductive layers and define ground select gates of the pillars. The ground select lines, too, may have respective widths in the bit line direction which are at least as large as (?/pBL).
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: September 6, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 9437311
    Abstract: A flash memory apparatus and an initialization method for programming operation thereof are provided. The initialization method includes: providing a plurality of increasing programming pulse voltages to operate a plurality of without program inhibit programming actions on memory cells of the flash memory, and operating a plurality of programming verification actions on the memory cells according to a programming verification voltage; obtaining a recorded programming voltage value according verified results of the programming verification actions; providing a plurality of increasing reading pulse voltages to operate a plurality of reading actions on the memory cells; obtaining a recorded reading voltage value according to read result of the reading actions; and obtaining an initial programming voltage and an incremental step programming pulse voltages according to the recorded programming voltage value, the recorded reading voltage value and a voltage value of the programming verification voltage.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 6, 2016
    Assignee: Powerchip Technology Corporation
    Inventor: Tsai-Ko Teng
  • Patent number: 9431093
    Abstract: A semiconductor device includes: a control block suitable for generating a clock control signal in response to a write training signal and a write-related information signal; and an input block suitable for receiving a data signal for a write training mode in response to the clock control signal and a clock signal.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: August 30, 2016
    Assignee: SK Hynix Inc.
    Inventor: Kyu-Bong Kong
  • Patent number: 9418025
    Abstract: An information processing device includes a storage device that stores information, and a controller that adjusts a consumption of read time of reading information to be read per unit data amount according to the priority of the information to be read from the storage device and a permitted read time during which read of information from the storage device is permitted. The permitted read time varies according to the processing time of another control different from the control of the read.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: August 16, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaki Iwakoshi
  • Patent number: 9418911
    Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: August 16, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Joo Shim, Hansoo Kim, Wonseok Cho, Jaehoon Jang, Woojin Cho
  • Patent number: 9412458
    Abstract: A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoya Tokiwa
  • Patent number: 9368605
    Abstract: A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a nonvolatile memory stack provided above the active region, a control gate electrode provided above the memory stack, a select gate electrode at least partially provided above the active region adjacent to the memory stack and a select gate insulation layer. The high voltage transistor includes an active region, a gate electrode and a gate insulation layer provided between the active region and the gate electrode. The select gate insulation layer of the nonvolatile memory device and the gate insulation layer of the high voltage transistor are at least partially formed of a same high-k dielectric material. The select gate electrode of the nonvolatile memory device and the gate electrode of the high voltage transistor are at least partially formed of a same metal.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: June 14, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Igor Lusetsky, Ralf van Bentum
  • Patent number: 9368210
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block includes a plurality of memory strings. In data write and read, the transfer circuit transfers a positive voltage to a select gate line associated with a selected memory string in a selected block, and a negative voltage to a select gate line associated with an unselected memory string in the selected block, and to a select gate line associated with an unselected block.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: June 14, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Maejima, Koji Hosono
  • Patent number: 9362302
    Abstract: A memory device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom level of conductive strips, a plurality of intermediate levels of conductive strips, and a top level of conductive strips. A reference conductor is disposed in a level between the bottom level of conductive strips and a substrate, isolated from the substrate by a layer of insulating material, and isolated from the bottom level by another layer of insulating material. A plurality of vertical active strips is disposed between the plurality of stacks in electrical contact with the substrate, and with the reference conductor. Charge storage structures are disposed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate levels and the vertical active strips. A bias circuit is configured to provide different bias arrangements to the reference conductor and the substrate.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: June 7, 2016
    Assignee: Macronix International Co., Ltd.
    Inventor: Erh-Kun Lai
  • Patent number: 9355861
    Abstract: A semiconductor device manufacturing method for etching a substrate having a multilayer film formed by alternately stacking a first film and a second film, and a photoresist layer to form a step-shaped structure is provided. The step-shaped structure is formed by repeatedly performing a first step of plasma-etching the first film by using the photoresist layer as a mask, a second step of exposing the photoresist layer formed on the substrate to a plasma generated from a processing gas containing argon gas and hydrogen gas by applying a high frequency power to a lower electrode while applying a negative DC voltage to an upper electrode, a third step of trimming the photoresist layer, and a fourth step of plasma-etching the second film.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: May 31, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Manabu Sato, Kazuki Narishige, Takanori Sato
  • Patent number: 9343161
    Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: May 17, 2016
    Assignee: SK hynix Inc.
    Inventors: Seong Hun Park, Jae Won Cha
  • Patent number: 9312009
    Abstract: A non-volatile memory includes a memory array, a row decoder, a column decoder, a write buffer and a sensing circuit. The column decoder includes a programming decoder and a reading decoder. The programming decoder is connected with n bit lines of the memory array. The reading decoder is connected with the n bit lines. During a program cycle, a programming control signal set is activated. Consequently, the programming decoder determines a selected memory cell, and a cell current generated by the selected memory cell flows to the write buffer through the programming decoder and a programming data line. During a read cycle, a reading control signal set is activated. Consequently, the reading decoder determines the selected memory cell, and the cell current generated by the selected memory cell flows to the sensing circuit through the reading decoder and a reading data line.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: April 12, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Tzu-Neng Lai, Chih-Hao Huang
  • Patent number: 9293470
    Abstract: Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and includes a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: March 22, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Haruka Sakuma, Kiwamu Sakuma, Masahiro Kiyotoshi
  • Patent number: 9281414
    Abstract: According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Yeon Won, Joon-Hee Lee, Seung-Woo Paek, Dong-Seog Eun
  • Patent number: 9269444
    Abstract: When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: February 23, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Henry Chin, Dana Lee
  • Patent number: 9263463
    Abstract: According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: February 16, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichiro Zaitsu, Kosuke Tatsumura, Mari Matsumoto
  • Patent number: 9263293
    Abstract: Embodiments of mechanisms of a semiconductor structure are provided. The semiconductor device structure includes a substrate and a floating gate having a first sidewall and a second sidewall formed over the substrate. The semiconductor device further includes an insulating layer formed over the substrate to cover the first sidewall and an upper portion of the second sidewall of the floating gate. The semiconductor device further includes a control gate formed over the insulating layer. In addition, the floating gate is formed in a shark's fin shape.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Ling Chang
  • Patent number: 9257443
    Abstract: According to an embodiment, a semiconductor memory device includes a semiconductor pillar, a first electrode film, a second electrode film, a first insulating film, a second insulating film, and a wiring film. The semiconductor member is extending in a first direction. The first electrode film is disposed at the lateral side of the semiconductor member away from the semiconductor member. The second electrode film is provided between the semiconductor member and the first electrode film. The first insulating film is provided between the semiconductor member and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode film. The wiring film is disposed in a wiring lead-out region adjacent to the memory cell region. And the first electrode film is formed of a material different from a material of the wiring film, and being electrically connected to the wiring film.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: February 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumie Kikushima, Tatsuya Kato, Wataru Sakamoto, Fumitaka Arai
  • Patent number: 9224483
    Abstract: Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification modes on the basis of an evaluated programming condition.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: December 29, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Moo Sung Kim
  • Patent number: 9208887
    Abstract: A non-volatile semiconductor memory device according to one embodiment includes: a cell array; and a data writing unit that repeatedly executes a write loop including a programming operation of applying a program voltage to a selected word line and a passage voltage to non-selected word lines during writing of data, in which, when a difference between the passage voltage used in an n-th write loop and the passage voltage used in an n+1-th write loop is expressed as ?Vn and when a condition of L<M (L and M are integers) is satisfied, the data writing unit executes the write loop using the passage voltage where ?V (L?1)<?VL, ?VL??V (M?1), and ?V (M?1)<?VM.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: December 8, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shigeo Kondo
  • Patent number: 9209198
    Abstract: Provided is a memory cell including a substrate, two doped regions of a first conductivity type, one doped region of a second conductivity type, two stacked structures, and a first isolation structure. The doped regions of the first conductivity type are respectively disposed in the substrate. The doped region of the second conductivity type is disposed in the substrate between the two doped regions of the first conductivity type. The stacked structures are disposed on the substrate and respectively cover the corresponding doped regions of the first conductivity type and a portion of the doped region of the second conductivity type. Each of the stacked structures includes one charge storage layer. The first isolation structure completely covers and is in contact with the bottom surface of each of the doped regions of the first conductivity type and the bottom surface of the doped region of the second conductivity type.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: December 8, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Wen-Jer Tsai
  • Patent number: 9171622
    Abstract: This technology provides a non-volatile memory device and a method of manufacturing the same, which may prevent an over-erase phenomenon and also increase the degree of integration, In an aspect, the non-volatile memory device includes a select gate formed over a substrate, a plurality of floating gates laterally formed with respect to the select gate and spaced apart from each other, to be independently programmable, and a plurality of junctions formed in the substrate and arranged to be controllable by the respective floating gates.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 27, 2015
    Assignee: SK Hynix Inc.
    Inventor: Young-Jun Kwon