Tunnel Programming Patents (Class 365/185.28)
  • Patent number: 11430526
    Abstract: In a coarse programming, the threshold voltage of the memory cell is programmed to a first level representative of N?1 bit values data according to a first mapping between combinations of values of N?1 possible bits and threshold levels. A group identification is representative of whether the first level is an odd or even numbered level in the first mapping. For a fine programming, the memory cell is read, based on the group identification, to obtain the N?1 bit values; and at least one additional bit is received to join the N?1 bit values to form at least N bit values. The threshold voltage of the memory cell is then finely programmed to a second level representative of the at least N bit values according to a second mapping between combinations of values of the at least N possible bits and threshold levels.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Phong Sy Nguyen, James Fitzpatrick, Kishore Kumar Muchherla
  • Patent number: 11430520
    Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 30, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Hideki Yamada, Marie Takada, Masanobu Shirakawa
  • Patent number: 11410726
    Abstract: Integrated circuit devices might include a controller configured to cause the integrated circuit device to apply a first voltage level to a first conductor while applying a second voltage level to a second conductor, apply a third voltage level to the first conductor while applying a fourth voltage level to the second conductor, and apply a fifth voltage level to the first conductor while applying the second voltage level to the second conductor. The second voltage level might correspond to a target voltage level for the second conductor. A difference between the third voltage level and the first voltage level might have a polarity opposite the polarity of a difference between the fourth voltage level and the second voltage level, and the same polarity of a difference between the fifth voltage level and the first voltage level. The fifth voltage level might correspond to a target voltage level for the first conductor.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo
  • Patent number: 11403228
    Abstract: Various embodiments described herein provide for a page program sequence for a block of a memory device, such as a negative-and (NAND)-type memory device, where all the wordlines are programmed with respect to a given set of page types (e.g., LP pages) prior to wordlines are programmed with respect to a next set of page types (e.g., UP and XP pages).
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kulachet Tanpairoj, Jianmin Huang, Tomoko Ogura Iwasaki, Kishore Kumar Muchherla, Peter Sean Feeley
  • Patent number: 11393530
    Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 11393512
    Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih
  • Patent number: 11355508
    Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, James A. Cultra, Sri Sai Sivakumar Vegunta
  • Patent number: 11335406
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of cell strings, a peripheral circuit, and control logic. Each of the cell strings includes a drain select transistor, a source select transistor, and a plurality of memory cells that are coupled in series between the drain select transistor and the source select transistor. The peripheral circuit may be configured to perform a program operation and a program verify operation on a cell string that is selected from among the plurality of cell strings. The control logic may be configured to control the peripheral circuit to boost a channel voltage of at least one unselected cell string, among the plurality of cell strings, based on a comparison between a degree of progress of the program operation and a reference degree of progress during the program verify operation.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: May 17, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Hoon Cho, Jae Sung Sim, Se Kyoung Choi
  • Patent number: 11309214
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first substrate, a buried dielectric layer inwardly positioned in the first substrate, a buried conductive layer including a lower portion positioned on the buried dielectric layer and an upper portion positioned on the lower portion, a buried capping layer positioned on the upper portion, and buried covering layers positioned between the buried capping layer and the buried dielectric layer and between the upper portion of the buried conductive layer and the buried dielectric layer. The buried conductive layer includes graphene.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: April 19, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11295809
    Abstract: One embodiment of a method for programming multiple-level memory cells includes programming lower page data to memory cells in a first pass of a multiple-pass programming operation. The method includes programming higher page data to the memory cells in a second pass of the multiple-pass programming operation such that higher page data subject to the programmed lower page data is programmed prior to higher page data subject to erase data.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Changhyun Lee, Akira Goda, William C. Filipiak
  • Patent number: 11222693
    Abstract: A data management method for a memory is provided. The memory includes memory pages. Each of the memory pages includes memory cells. A data update command corresponding to a logical address is received. The logical address maps to a physical address of a target memory page before receiving the data update command. First and second reading voltages are applied to obtain at least a first and a second target memory cell to be sanitized in the target memory page of the memory pages, a first programming voltage is applied to change the logical state of the first target memory cell to a logical state with a higher threshold voltage, and a second programming voltage is applied to change the logical state of the second target memory cell to a logical state with a higher threshold voltage. The first programming voltage is different from the second programming voltage.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: January 11, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yung-Chun Li, Wei-Chen Wang
  • Patent number: 11211395
    Abstract: A device comprises a column of cells disposed in multiple levels of word lines including a pillar comprising a first vertical conductive line, a second vertical conductive line, and a vertical semiconductor body disposed between and in contact with the first and second vertical conductive lines. A pillar select line is adjacent to and separated by a gate dielectric from the vertical semiconductor body to form a pillar select switch, the pillar select line disposed beneath the first and second vertical conductive lines. A bottom select line is disposed beneath the first and second vertical conductive lines and insulated from the pillar select line and the first and second vertical conductive lines. The bottom select line is in current-flow contact with the vertical semiconductor body of the pillar.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 28, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hsiang-Lan Lung
  • Patent number: 11176969
    Abstract: A memory circuit array includes a first read device and a first program device. The first read device is coupled to a first bit line. The first read device includes a first transistor coupled to a first word line, and a second transistor coupled to the first word line. The first program device is coupled to the first read device. The first program device includes a third transistor coupled to a second word line, and a fourth transistor coupled to the second word line.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Min-Shin Wu, Yao-Jen Yang
  • Patent number: 11158643
    Abstract: Structures for a non-volatile memory bit cell and methods of forming a structure for a non-volatile memory bit cell. A field-effect transistor has a channel region and a first gate electrode positioned over the channel region. A capacitor includes a second gate electrode that is coupled to the first gate electrode to define a floating gate. The first gate electrode has a non-rectangular shape.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: October 26, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lanxiang Wang, Shyue Seng Tan, Kiok Boone Elgin Quek, Xinshu Cai, Eng Huat Toh
  • Patent number: 11152380
    Abstract: A memory device may include a first conductivity region, and second and third conductivity regions arranged at least partially within the first conductivity region. The first and second conductivity regions may have a different conductivity type from at least a part of the third conductivity region. The memory device may include first and second gates arranged over the third conductivity region. The second conductivity region may be coupled to a source line, and the gates may be coupled to respective word lines. When a predetermined write voltage difference is applied between the source line and a word line, an oxide layer of the gate coupled to the word line may break down to form a conductive link between the gate electrode of the gate and the third conductivity region. The memory device may have a smaller cell area, and may be capable of operating at both higher and lower voltages.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 19, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Bin Liu, Shyue Seng Tan
  • Patent number: 11106373
    Abstract: Systems and methods for managing content in a flash memory. Content or data in a flash memory is overwritten when the write operation only requires bits to be set. This improves performance of the flash and extends the life of the flash memory.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: August 31, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Grant R. Wallace, Philip N. Shilane
  • Patent number: 11087836
    Abstract: Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 10, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Bernardo Rub, Mostafa El Gamal
  • Patent number: 11063772
    Abstract: A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: July 13, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Tsung-Mu Lai, Shih-Chen Wang
  • Patent number: 11048443
    Abstract: A circuit comprising a non-volatile memory array, an Input/Output (IO) circuit, a decoder circuit, a control circuit, and a read/write circuit. The non-volatile memory array couples to an address decoder that identifies a location within the non-volatile memory array for a storage command. The IO circuit couples to a decoder circuit through a control bus. The decoder circuit decodes a command address and storage command from a fixed length command sequence received by the IO circuit over the data bus. The decoder circuit may include a serial-in parallel out (SIPO) circuit for decoding and parallel operation. The control circuit couples to the IO and decoder circuits and generates control signals to execute decoded storage commands. The read/write circuit couples to the non-volatile memory array and the control circuit. The read/write circuit transfers data between the non-volatile memory array and the IO circuit in response to the storage commands.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: June 29, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Sajal Mittal, Sneha Bhatia, Vinayak Ghatawade
  • Patent number: 11043601
    Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Shiung Wu, Ya-Chin King, Chrong-Jung Lin
  • Patent number: 11037609
    Abstract: A semiconductor device includes a column operation control circuit and a bank column address generation circuit. The column operation control circuit generates first and second bank address control signals as well as first and second bank control pulses from first and second bank selection signals in response to a synthesis control pulse such that data in a first bank and data in a second bank are simultaneously outputted in a first mode. The bank column address generation circuit generates first and second bank column addresses for selecting the first and second banks from a column address in response to the first and second bank address control signals.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Tae Yong Lee
  • Patent number: 11011533
    Abstract: A memory structure including a first select transistor, a first floating gate transistor, a second select transistor, a second floating gate transistor, and a seventh doped region is provided. The first select transistor includes a select gate, a first doped region, and a second doped region. The first floating gate transistor includes a floating gate, the second doped region, and a third doped region. The second select transistor includes the select gate, a fourth doped region, and a fifth doped region. The second floating gate transistor includes the floating gate, the fifth doped region, and a sixth doped region. A gate width of the floating gate in the second floating gate transistor is greater than a gate width of the floating gate in the first floating gate transistor. The floating gate covers at least a portion of the seventh doped region.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 18, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Chia-Jung Hsu, Wein-Town Sun
  • Patent number: 10984858
    Abstract: A semiconductor storage device includes: a voltage generation circuit configured to generate a read voltage to be supplied to a selected word line to which a read-target memory cell transistor is connected and a read-pass voltage to be supplied to an adjacent word line; a word line driver configured to, when the read voltage transitions, apply the read voltage to the selected word line with a first kick voltage amount and apply the read-pass voltage to the adjacent word line with a second kick voltage amount; and a control circuit configured to set each of the first kick voltage amount and the second kick voltage amount to a voltage corresponding to an amount of the transition.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: April 20, 2021
    Assignee: Kioxia Corporation
    Inventor: Hiroki Date
  • Patent number: 10943949
    Abstract: A semiconductor storage device includes a plurality of memory cells and a first circuit. The first circuit is configured to read data from a subset of the memory cells, such as a page unit or the like, then determine whether the data as read from the subset contains an error. The first circuit calculates a bit error rate for the subset if the subset contains an error and performs a recovery processing on the subset if the calculated bit error rate is less than a first threshold value but greater than a second threshold value.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yosuke Kobayashi
  • Patent number: 10930331
    Abstract: A semiconductor device includes a memory string coupled between a source line and a bit line and including a plurality of memory cells, a plurality of word lines, a peripheral circuit configured to apply a program voltage to a word line, apply a first pass voltage to a word line coupled to a first memory cell adjacent to the selected memory cell, and apply a second pass voltage to a second memory cell adjacent to the selected memory cell, and control logic configured to control the peripheral circuit so that the first pass voltage has a higher voltage level than the second pass voltage when a program target level of the selected memory cell is lower than a first threshold value, and the first pass voltage has a lower voltage level than the second pass voltage when the program target level is higher than a second threshold value.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Jong Kyung Park, Ji Hyun Seo, Hye Eun Heo
  • Patent number: 10878896
    Abstract: Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: December 29, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Bernardo Rub, Mostafa El Gamal
  • Patent number: 10861512
    Abstract: A semiconductor device includes a column operation control circuit and a bank column address generation circuit. The column operation control circuit generates first and second bank address control signals as well as first and second bank control pulses from first and second bank selection signals in response to a synthesis control pulse such that data in a first bank and data in a second bank are simultaneously outputted in a first mode. The bank column address generation circuit generates first and second bank column addresses for selecting the first and second banks from a column address in response to the first and second bank address control signals.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Tae Yong Lee
  • Patent number: 10833126
    Abstract: A semiconductor memory device may include: a plurality of row lines extended in parallel to each other in a first horizontal direction; a plurality of column line stacks extended in parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, wherein each of the plurality of column line stacks includes a plurality of column lines extended in parallel to each other in a vertical direction; and a plurality of cell pillars that pass vertically through the column lines of the column line stacks, each of the plurality of cell pillars has a first end and a second end, wherein the first ends of the plurality of cell pillars are electrically coupled to the plurality of row lines, and the second ends of the plurality of cell pillars are floated. Each cell pillar includes a core and variable resistance memory layers.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: November 10, 2020
    Assignee: SK hynix Inc.
    Inventor: Seong-Hyun Kim
  • Patent number: 10748606
    Abstract: Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: August 18, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Bernardo Rub, Mostafa El Gamal
  • Patent number: 10726897
    Abstract: A magnetoresistive random access memory (MRAM) system is described. The system includes a sense amplifier circuit for sensing a data state of an MRAM data cell. The circuit includes a first leg and a second leg, and is configured to perform a two-phase read including a first phase in which a first transistor is coupled to a reference resistance circuitry and a second transistor is coupled to a data resistance circuitry, and a second phase in which the first transistor is coupled to the data resistance circuitry and the second transistor is coupled to the reference resistance circuitry. The circuit further includes a reference trim circuitry and a data trim circuitry configured to correct for device mismatch errors relating to the two-phase read of the sense amplifier circuit. The circuit further includes a comparator circuit configured to output the data state of the data cell.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Thomas Martin Maffitt, John Kenneth Debrosse, Matthew R Wordeman
  • Patent number: 10692875
    Abstract: A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 23, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Wang Xiang, Chia-Ching Hsu, Chun-Sung Huang, Yung-Lin Tseng, Wei-Chang Liu, Shen-De Wang
  • Patent number: 10665313
    Abstract: Techniques are described for detecting a short circuit between a word line and a source line in a memory device, and to a method for recovering from such a short circuit. In one aspect, the short circuit is detected in a program operation when a selected word line completes programming after an unusually low number of program loops. A further check is performed to confirm that there is a short circuit. The short circuited word line is then erased and a recovery read is performed for previously-programmed word lines. In another aspect, a short circuit is detected in a read operation.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 26, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Henry Chin, Jian Chen
  • Patent number: 10659225
    Abstract: A system stores data in data units in a cluster in a cloud computing system, the data stored in the data units being encrypted or unencrypted depending on whether encryption is enabled or disabled when storing data in the data units. The system identifies one or more data units to defragment and defragments the identified data units by writing the data from the identified data units to one or more new data units and by releasing the identified data units for storing new data. The system encrypts unencrypted data from the identified data units when writing the data from the identified data units to the one or more new data units.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 19, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Rushi Srinivas Surla, Shane Kumar Mainali, Andrew Edwards, Maneesh Sah, Weiping Zhang
  • Patent number: 10650903
    Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Il Shim, Jae-Hoon Jang, Donghyuk Chae, Youngho Lim, Hansoo Kim, Jaehun Jeong
  • Patent number: 10643708
    Abstract: A method for operating a low-current EEPROM array is disclosed. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method uses special biases to perform the bytes writing and erasing with low current, low voltage and low cost.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: May 5, 2020
    Assignee: Yield Microelectronics Corp.
    Inventors: Hsin-Chang Lin, Cheng-Yu Chung, Wen-Chien Huang
  • Patent number: 10593398
    Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masanobu Shirakawa, Takayuki Akamine
  • Patent number: 10559331
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages coupled to word lines, respectively, peripheral circuits configured to, during a program operation, perform program, verify, and discharge operations on memory cells coupled to a word line selected from among the word lines, and a control logic configured to control the peripheral circuits such that, during the discharge operation performed after the verify operation, word lines, included in a region in which the program operation has not completed, and word lines, included in a region in which the program operation has completed, among the word lines, are discharged at different times.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Hee Youl Lee, Sung In Hong
  • Patent number: 10515692
    Abstract: Methods of operating a memory device applying a programming pulse having a plurality of different voltage levels to an access line coupled to a plurality of memory cells, enabling a particular memory cell of the plurality of memory cells for programming while the programming pulse has a particular voltage level of the plurality of different voltage levels, and, after enabling the particular memory cell for programming, inhibiting the particular memory cell from programming while the programming pulse has a second voltage level of the plurality of different voltage levels, different than the particular voltage level.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Xiaojiang Guo, Ramin Ghodsi
  • Patent number: 10438025
    Abstract: A memory device is disclosed. The memory device includes a memory bit array comprising a plurality of memory bits, wherein each memory bit is configured to present an initial logic state when the memory device is powered on, and an erasion circuit, coupled to the memory bit array, and configured to alter an intrinsic characteristic of at least one of the memory bits so as to alter the initial logic state of the at least one memory bit.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: October 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10325661
    Abstract: Methods of programming a memory include applying a programming voltage on an access line selected for a programming operation of a single page of the memory, applying a second voltage on an access line unselected for the programming operation, increasing the programming voltage for a first plurality of steps of the programming operation, and increasing the second voltage for a second plurality of steps of a first portion of the programming operation, then decreasing the second voltage at a particular point of the programming operation after completing the second plurality of steps and before completing the first plurality of steps.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yijie Zhao, Akira Goda
  • Patent number: 10325921
    Abstract: To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ONO film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ONO film) thicker than the ONO film is provided between the memory gate electrode and a top surface of the fin. This configuration can reduce concentration of an electric field onto a tip of the fin, so that deterioration of reliability of the ONO film can be prevented.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuyoshi Mihara
  • Patent number: 10262740
    Abstract: A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: April 16, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoki Nakagawa, Koji Hosono
  • Patent number: 10176998
    Abstract: A semiconductor device includes a substrate, a dielectric layer and a floating gate. The dielectric layer disposed on the substrate. The floating gate disposed on the dielectric layer. After a first programming process, the floating gate is configured to store first electrons that are to be combined with ions from the dielectric layer. After a second programming process, the floating gate is configured to store second electrons, and a number of the second electrons is larger than a number of the first electrons.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Wu, Meng-Chun Shih, Chin-Huang Wang
  • Patent number: 10141057
    Abstract: An erasing method of a single-gate non-volatile memory is provided. The single-gate non-volatile memory has a single floating gate. The erasing method includes applying a voltage to the drain without applying to the gate to create and control an inversion layer. Therefore the required erasing voltage is reduced and the erasing speed is improved to avoid the over-erase problem.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 27, 2018
    Assignee: Yield Microelectronics Corp.
    Inventors: Hsin-Chang Lin, Wen-Chien Huang, Wei-Tung Lo
  • Patent number: 10120579
    Abstract: Techniques for implementing a data management scheme for optimizing data storage are described herein. A deletion quantity or other metric relating to deletions of data within a first storage zone are tracked. Upon detection that the tracked deletion metric meets certain criteria, the data within the first storage zone are moved to a second storage zone. A verification of the data to be moved is also performed, and if such verification indicates that at least a portion of the data is corrupted, routines repairing and/or restoring at least the corrupted portion are initiated.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: November 6, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Kestutis Patiejunas, Colin L. Lazier, James Christopher Sorenson, III
  • Patent number: 10096602
    Abstract: Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: October 9, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE Pte. Ltd.
    Inventors: Shyue Seng Jason Tan, Kiok Boone Elgin Quek
  • Patent number: 9947687
    Abstract: A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: April 17, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Patent number: 9947375
    Abstract: Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 17, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Jae-Kwan Park
  • Patent number: 9917211
    Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: March 13, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Wei Zheng, Chi Chang, Unsoon Kim
  • Patent number: 9881930
    Abstract: A method that allows integrating complementary metal oxide semiconductor (CMOS) transistors and a non-volatile memory (NVM) transistor on a single substrate is provided. The NVM transistor includes a gate stack containing a high-k tunneling gate dielectric, a floating gate electrode, a high-k control gate dielectric and a control gate electrode. The high-k tunneling gate dielectric is formed form a first high-k dielectric layer employed in formation of a gate dielectric for a p-type field effect transistor (FET), the floating gate electrode is formed from a capping material layer employed in annealing the first high-k dielectric layer, and the high-k control gate dielectric is formed from a second high-k dielectric layer employed in formation of a gate dielectric for an n-type FET.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung