Abstract: When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines.

Abstract: Embodiments of mechanisms of a semiconductor structure are provided. The semiconductor device structure includes a substrate and a floating gate having a first sidewall and a second sidewall formed over the substrate. The semiconductor device further includes an insulating layer formed over the substrate to cover the first sidewall and an upper portion of the second sidewall of the floating gate. The semiconductor device further includes a control gate formed over the insulating layer. In addition, the floating gate is formed in a shark's fin shape.

Abstract: According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode.

Abstract: According to an embodiment, a semiconductor memory device includes a semiconductor pillar, a first electrode film, a second electrode film, a first insulating film, a second insulating film, and a wiring film. The semiconductor member is extending in a first direction. The first electrode film is disposed at the lateral side of the semiconductor member away from the semiconductor member. The second electrode film is provided between the semiconductor member and the first electrode film. The first insulating film is provided between the semiconductor member and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode film. The wiring film is disposed in a wiring lead-out region adjacent to the memory cell region. And the first electrode film is formed of a material different from a material of the wiring film, and being electrically connected to the wiring film.

Abstract: Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification modes on the basis of an evaluated programming condition.

Abstract: Provided is a memory cell including a substrate, two doped regions of a first conductivity type, one doped region of a second conductivity type, two stacked structures, and a first isolation structure. The doped regions of the first conductivity type are respectively disposed in the substrate. The doped region of the second conductivity type is disposed in the substrate between the two doped regions of the first conductivity type. The stacked structures are disposed on the substrate and respectively cover the corresponding doped regions of the first conductivity type and a portion of the doped region of the second conductivity type. Each of the stacked structures includes one charge storage layer. The first isolation structure completely covers and is in contact with the bottom surface of each of the doped regions of the first conductivity type and the bottom surface of the doped region of the second conductivity type.

Abstract: A non-volatile semiconductor memory device according to one embodiment includes: a cell array; and a data writing unit that repeatedly executes a write loop including a programming operation of applying a program voltage to a selected word line and a passage voltage to non-selected word lines during writing of data, in which, when a difference between the passage voltage used in an n-th write loop and the passage voltage used in an n+1-th write loop is expressed as ?Vn and when a condition of L<M (L and M are integers) is satisfied, the data writing unit executes the write loop using the passage voltage where ?V (L?1)<?VL, ?VL??V (M?1), and ?V (M?1)<?VM.

Abstract: This technology provides a non-volatile memory device and a method of manufacturing the same, which may prevent an over-erase phenomenon and also increase the degree of integration, In an aspect, the non-volatile memory device includes a select gate formed over a substrate, a plurality of floating gates laterally formed with respect to the select gate and spaced apart from each other, to be independently programmable, and a plurality of junctions formed in the substrate and arranged to be controllable by the respective floating gates.

Abstract: A memory system includes a nonvolatile memory device having a first data area storing M-bit data using a buffer program operation and a second data area storing N-bit data (N being an integer larger than M) using a main program operation and a memory controller configured to control the nonvolatile memory device. When a main program operation using data stored at the first and second data areas is required, the memory controller calculates values indicating a performance of the required main program operation to be executed according to a plurality of main program manners, selects one of the plurality of main program manners based on the calculated values, and controls the nonvolatile memory device to perform the required main program operation according to the selected main program manner.

Abstract: A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Abstract: A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase program operation. For the preparation phase, the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation. Results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data.

Abstract: A method of operating an integrated circuit includes determining at least one characteristic of at least one memory cell and conducting an operation for the at least one memory cell, wherein based on the at least one characteristic determined a disturbance for at least one additional memory cell is adjusted.

Abstract: A method for programming a memory cell of a memory device includes the following steps. A plurality of cycle number ranges are set up. A specific one of the plurality of cycle number ranges, in which the memory cell having a drain terminal passes a program-verification, is determined. A bias voltage is applied to the drain terminal for programming the memory cell, wherein the bias voltage varies with the specific cycle number range.

Abstract: A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.

Abstract: A method includes storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data in a volatile buffer and then writing the buffered data to the analog memory cells while overwriting at least some of the data in the volatile buffer with success indications. Upon detecting a failure in writing the buffered data to the analog memory cells, recovered data is produced by reading both the volatile buffer and the analog memory cells, assigning reliability metrics to respective bits of the recovered data depending on whether the bits were read from the volatile buffer or from the analog memory cells, applying ECC decoding to the recovered data using the reliability metrics and reprogramming the recovered data.

Abstract: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.

Abstract: An incremental signal is defined that includes at least one of a duration and a peak voltage that is less than a respective minimum programming time or minimum programming voltage step of a resistive memory element. A characterization procedure is repeatedly performed that at least involves: applying a signal to the memory element, the signal being incremented by the incremental signal during each subsequent application; measuring a first resistance of the memory element in response to the signal; and c) measuring a second resistance of the memory element after a time period has elapsed from the measurement of the first resistance with no programming signal applied. In response to the first and second resistance measurements of the characterization procedure, a characterization parameter of the memory element is formed.

Abstract: Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND string may be lowered from one programming pulse to the next programming pulse multiple times. The select transistor may be a drain side select transistor or a source side select transistor. Progressively lowering the Vgs of the select transistor of an unselected NAND string as programming progresses may prevent the select transistor from unintentionally turning on. Therefore, program disturb is prevented or reduced. Vgs may be lowered by applying a lower voltage to a select line associated with the select transistor. Vgs may be lowered by applying a higher voltage to bit lines associated with the unselected NAND strings as programming progresses. Vgs may be lowered by applying a higher voltage to a common source line as programming progresses.

Abstract: A non-volatile memory includes a memory array, a row decoder, a source line decoder, a column decoder, and a sensing circuit. The memory array is connected with m word lines, n source lines and n bit lines. The row decoder determines a selected row of n memory cells. The n memory cells in the selected row are connected with the n source lines and the n bit lines. By the source line decoder, an x-th source line is connected with a source line voltage but the other source lines of the n source lines are in a floating state. By the column decoder, an x-th bit line of the n bit lines is connected with a data line but the other bit lines are connected with a reference voltage. The sensing circuit determines a storing state of a selected memory cell.

Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

Abstract: Methods of forming semiconductor devices are provided. A method of forming a semiconductor device may include forming a structure including insulating layers and gate layers that are alternately and repeatedly stacked on a substrate. The method may include forming through-holes in the structure. The method may include forming first patterns on sidewalls of the gate layers, by performing an oxidation process. The method may include forming second patterns on portions of the substrate, by performing the oxidation process. The method may include removing the second patterns. Moreover, the method may include forming semiconductor patterns in the through-holes.

Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.

Abstract: A non-volatile memory cell comprises a coupling device, a first and a second select transistor, and a first and a second floating gate transistor is disclosed. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to the first floating gate transistor and the second select transistor. Moreover, the first select transistor, the first floating gate transistor, and the second select transistor are formed in a second conductivity region. The second floating gate transistor is formed in a third conductivity region, wherein the first conductivity region, the second conductivity region, and the third conductivity region are formed in a fourth conductivity region. The first conductivity region, the second conductivity region, and the third conductivity region are wells, and the fourth conductivity region is a deep well. The third conductivity region surrounds the first conductivity region and the second conductivity region.

Abstract: According to one embodiment, a non-volatile semiconductor memory device which is provided with a memory cell array, bit lines, word lines, and a sense amplifier circuit is presented. The memory cell array includes memory cells. The bit lines are electrically connected to the memory cells. The word lines are electrically connected to gates of the non-volatile memory cells. The sense amplifier circuit includes sense amplifiers which are electrically connected to the bit lines. Each of the sense amplifiers includes a latch circuit which is capable of holding data, and a detection circuit. The sense amplifiers are configured to apply any one of a first voltage and a second voltage higher than the first voltage to the bit lines respectively. The sense amplifiers apply any one of the first voltage and the second voltage s a third voltage to the bit lines, and apply the third voltage to the detection circuit.

Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.

Abstract: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

Abstract: According to one embodiment, a non-volatile programmable switch according to this embodiment includes first and second non-volatile memory transistors, and a common node that is connected to the output side terminals of the first and second non-volatile memory transistors, and a logic transistor unit that is connected to the common node. A length of a gate electrode of the first and second non-volatile memory transistors in a channel longitudinal direction is shorter than a length of the charge storage film in the channel longitudinal direction.

Abstract: A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.

Abstract: Write precomensation mechanisms for non-volatile solid-state memory are disclosed. In one embodiment, programming verify voltage levels are lowered from the default levels in the early life of the solid-state memory. As memory errors increase beyond an error threshold, programming verify voltage levels are increased by one or more voltage step sizes. This programming verify voltage level increase can be performed until default levels are reached or exceeded. As a result of lowered programming verify voltage levels in the early life of the solid-state memory device, solid-state memory experiences less wear and the operational life of the memory can be extended. Disclosed write precomensation mechanisms can be used for single-level cell (SLC) and multi-level cell (MLC) memory.

Abstract: An instruction to write to a location in the Flash memory is received. It is determining if the Flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. In the event it is determined that the Flash memory exposes a level placement setting, an accurate coarse write is performed on the location, including by configuring the level placement setting to be a first value, and after the accurate coarse write is performed on the location, a fine write is performed on the location, including by configuring the level placement setting to be a second value, in response to receiving the instruction.

Abstract: A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: dividing the plurality of memory cells into M number of groups (M is an integer); successively selecting each of the M number of groups; generating M number of successive overlapping pulse signals; and programming the memory cells of the M number of groups in response to the respective M number of successive overlapping pulse signals.

Abstract: A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage.

Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.

Abstract: Disclosed herein are techniques for providing a programming voltage to a selected word line in a non-volatile memory array. This may be a 3D NAND, 2D NAND, or another type of memory array. The programming voltage may be quickly ramped up on the selected word line, without the need for adding a stronger charge pump to the memory device. The voltage on the selected word line may be ramped up to a target voltage during a channel pre-charge phase. The target voltage may be limited in magnitude so that program disturb does not occur. Next, during a channel boosting phase, the unselected word lines are increased to a boosting voltage. The voltage on the selected word line is also increased during the boosting phase to a second target level. Then, the voltage on the selected word line is charged up from the second target level to a program voltage.

Abstract: Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.

Abstract: Techniques are provided for sensing memory cells in a 3D stacked non-volatile memory device in a way which reduces read disturb, by using read pass voltages which are adjusted based on variations in a memory hole diameter. The memory cells are in NAND strings which extend in the memory holes. A larger read pass voltage is used for memory cells which are adjacent to wider portions of the memory holes, and a smaller read pass voltage is used for memory cells which are adjacent to narrower portions of the memory holes. This approach reduces the worst-case read disturb. Further, an overall resistance in the NAND string channel may be substantially unchanged so that a reference current used during sensing may be unchanged. The read pass voltage may be set based on a program voltage trim value, which is indicative of programming speed and memory hole diameter.

Abstract: A writing method of a semiconductor memory device includes applying a plurality of program voltages sequentially generated to a selected word line, and applying any one of a plurality of source selection line voltages to a source selection line when each of the plurality of program voltages is applied.

Abstract: A semiconductor memory device and a method of operating the same perform a program loop, including a program operation and a program verification operation based on a sub-verification voltage smaller than a target verification voltage and the target verification voltage, to the memory cells until a threshold voltage of the memory cells is greater than the target verification voltage. A positive voltage, supplied to the bit line of the memory cell of which the threshold voltage is higher than the sub-verification voltage, is increased whenever the program operation is performed, and thus a threshold voltage distribution of the memory cells may be improved.

Abstract: A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method.

Abstract: A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described.

Abstract: According to one embodiment, a semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The memory cells are stacked above a semiconductor substrate, and each includes a charge accumulation layer and control gate. The word lines are coupled to the control gates. The driver circuit repeats a programming operation to write data in a memory cell coupled to a selected word line. In the programming operation, a first voltage is applied to the selected word line, a second voltage to a first unselected word line, and a third voltage to a second unselected word line. The control circuit steps up the first voltage and steps down the second voltage in repeating the programming.

Abstract: When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines.

Abstract: A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory in the case of success of the first writing phase.

Abstract: Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2B, rounded up to an integer, and where B is equal to the fractional number of bits represented by the programmed state.

Abstract: The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells during a program operation, configured to supply a first negative voltage to the word line during a detrapping operation, and configured to supply a second negative voltage as a verify voltage to the word line during a program verify operation.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.

Abstract: A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.