Plural Use Of Terminal Patents (Class 365/189.03)
  • Patent number: 11074967
    Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: July 27, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Adithya Bhaskaran, Mukund Narasimhan, Shiba Narayan Mohanty
  • Patent number: 11057999
    Abstract: A motherboard is provided. The motherboard includes a memory module, a processor and a memory slot. The memory module includes a first memory rank, a second memory rank, a plurality of first pins coupled to the first memory rank and a plurality of second pins coupled to the second memory rank. The processor includes a memory channel. The memory slot is coupled between the processor and the memory module, and is configured to transmit a first control signal from the memory channel to at least one of the plurality of first pins, or transmit a second control signal from the memory channel to at least one of the plurality of second pins. The first memory rank receives the first control signal through at least one of the plurality of first pins. The second memory rank receives the second control signal through at least one of the plurality of second pins.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: July 6, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Bing-Min Lin, Ji-Kuang Tan, Chen-Wei Fan
  • Patent number: 11037608
    Abstract: A stacked memory device includes: a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises: a re-timing circuit suitable for receiving input signals and first and second clocks, performing a re-timing operation of latching the input signals based on the second clock to output re-timed signals, and reflecting a delay time of the re-timing operation into the first clock to output a replica clock; and a transfer circuit suitable for transferring the re-timed signals to the through-electrodes based on the replica clock.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Myeong-Jae Park, Chun-Seok Jeong
  • Patent number: 10978117
    Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region for coupling command-and-address (CA) input signals and a memory cell region for storing information in memory cells. A centralized CA interface region includes input circuits coupled to the CA input signals. At least two of the input circuits are configured in pairs. Each pair includes a first input circuit coupled to a first input and configured to generate a first output and a second input circuit coupled to a second input and configured to generate a second output. Each pair also includes a swap circuit disposed between the first input circuit and the second input circuit. The swap circuit selects one of the first output or the second output for a first internal signal and selects the other of the first output and the second output for a second internal signal responsive to a control signal.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiro Yoshida
  • Patent number: 10936199
    Abstract: A method of a flash controller to be coupled between a flash memory device and a host device is provided. The flash memory device has a plurality of blocks each having a plurality of pages, and the method comprises: receiving a trim/erase/unmap command from the host device; obtaining a storage space, which is to be erased, from the trim/erase/unmap command; comparing a space size of the storage space with a threshold to determine whether the space size is larger than the threshold; and resetting valid page counts of the plurality of blocks of the flash memory device when the space size is larger than the threshold.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: March 2, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Hsu-Ping Ou
  • Patent number: 10861543
    Abstract: In one embodiment, a memory device includes a first sense amplifier, a second sense amplifier, a first lower switch arranged between a first lower main bit line and a first input of the first sense amplifier, a second lower switch arranged between the first lower main bit line and a first input of the second sense amplifier, a first upper switch arranged between a first upper main bit line and the first input of the first sense amplifier, a second upper switch arranged between the first upper main bit line and the first input of the second sense amplifier, a third lower switch arranged between a second lower main bit line to a second input of the first sense amplifier, and a third upper switch arranged between a second upper main bit line to a second input of the second sense amplifier.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: December 8, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fabio Enrico Carlo Disegni, Cesare Torti, Davide Manfré
  • Patent number: 10832764
    Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: November 10, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Adithya Bhaskaran, Mukund Narasimhan, Shiba Narayan Mohanty
  • Patent number: 10785014
    Abstract: Provided is a computation device including a communication interface; a first transmission control part for sending a first communication frame at every predetermined cycle via a transmission path; a second transmission control part for sending a second communication frame in response to an arbitrary event request; and a priority management part. Upon receiving an issuance request of a second event request from a second event issuance part, the priority management part waits for completion of sending processing for a second communication frame corresponding to a first event request currently processed by the second transmission control part, and permits issuance of the second event request to the second event issuance part. The second transmission control part suspends processing for a subsequent first event request following the first event request currently processed until completion of processing for the second event request is complete.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: September 22, 2020
    Assignee: OMRON Corporation
    Inventors: Akihiro Tamura, Makoto Iwai, Shigeyuki Eguchi, Yasunori Fukuda, Kenichi Iwami, Kazunari Miyake
  • Patent number: 10719264
    Abstract: A solid state drive (SSD) device includes a plurality of nonvolatile memory devices and a SSD controller. The SSD controller is configured to allocate a resource of the SSD device based on workloads of a plurality of streams and to control operations of the nonvolatile memory devices. Accordingly, the resources of the SSD device are adjusted according to the workloads of the streams so that the SSD device may support a multi stream system with reducing performance deterioration.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min-Uk Kim
  • Patent number: 10712962
    Abstract: A memory system may include: a memory device including a plurality of dies, each including a plurality planes, each including a plurality of blocks; and a controller suitable for grouping the plurality of memory blocks into a plurality of super blocks, each of which has a designated type corresponding to a condition, the controller may form a set of first super blocks, among the plurality of super blocks, each of which has at least one bad memory block and good memory blocks, and may manage the first super blocks.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 14, 2020
    Assignee: SK hynix Inc.
    Inventors: Se-Hyun Kim, Kyung-Hoon Lee, Sung-Hun Jeon, Jung-Woo Kim
  • Patent number: 10650879
    Abstract: A device for controlling the refresh cycles of data stored in a non-volatile memory is provided. The device comprises a temperature sensor capable of measuring the temperature of at least one non-volatile memory and of delivering information representing the measured temperature, and a control module coupled to the temperature sensor capable of using the temperature information with modelling of the impact of the temperature on the retention time of the data in order to determine whether a loss of data is imminent and, if so, in order to generate an alarm.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: May 12, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Valentin Gherman, Marcelino Seif
  • Patent number: 10489312
    Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Seiji Narui, Homare Sato, Chikara Kondo
  • Patent number: 10424356
    Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Gary Howe, Eric J. Stave, Thomas H. Kinsley, Matthew A. Prather
  • Patent number: 10347324
    Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Bhushan M. Borole, Iqbal R. Rajwani, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhisek R. Appu
  • Patent number: 10309783
    Abstract: A physical quantity detection system includes first and second physical quantity sensors, first and second power supply lines to which a power supply voltage is applied, a first decoupling circuit with first band elimination frequency characteristics, and a second decoupling circuit with second band elimination frequency characteristics. A relationship of a cutoff frequency on a low frequency side of the first band elimination frequency characteristics<a first drive frequency of a first drive circuit<a cutoff frequency on a high frequency side of the first band elimination frequency characteristics is satisfied, and a relationship of a cutoff frequency on a low frequency side of the second band elimination frequency characteristics<a second drive frequency of a second drive circuit<a cutoff frequency on a high frequency side of second band elimination frequency characteristics is satisfied.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: June 4, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Yutaka Takada
  • Patent number: 9865312
    Abstract: A semiconductor device includes an output driver having a variable current driving ability, for outputting an amplified data signal to the outside through a transmission line; a nonvolatile memory having a specific area for storing output adjustment data to adjust the current driving ability of the output driver; an output adjustment data readout unit for reading out the output adjustment data from the specific area of the memory in response to powering on; and a current driving ability adjustment unit for adjusting the current driving ability of the output driver on the basis of the output adjustment data read out from the memory.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: January 9, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Shuhei Kamano
  • Patent number: 9799378
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: October 24, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 9767865
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 9761288
    Abstract: A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: September 12, 2017
    Assignee: SK hynix Inc.
    Inventors: Min Chang Kim, Chang Hyun Kim, Do Yun Lee, Jae Jin Lee, Hun Sam Jung
  • Patent number: 9728236
    Abstract: A memory channel includes a dual channel double data rate (DDR) memory device having a first bank of memory accessed by a first data bus and a first command/address (C/A) bus, and a second bank of memory accessed by a second data bus and a second C/A bus, and a memory controller configured to train the first and second C/A busses with both the first and second C/A busses active, and to train one of the first and second C/A busses with the other of the first and second C/A busses idle.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: August 8, 2017
    Assignee: Dell Products, LP
    Inventors: Vadhiraj Sankaranarayanan, Bhyrav M. Mutnury, Stuart Allen Berke
  • Patent number: 9594115
    Abstract: A device that is capable of generating a new test pattern after the design phase and has a small area of a circuit not in use during normal operation includes a first circuit and a second circuit. The second circuit includes a third circuit and fourth circuit. The fourth circuit has a function of storing data for determining the configuration of the third circuit. When a test for the operating state of the first circuit is performed, the second circuit has a function of generating a signal for the test. When the test is not performed, the second circuit has a function of storing data used for processing in the first circuit and a function of comparing a plurality of signals.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: March 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 9583182
    Abstract: A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far memory addresses mapped to the near memory addresses. The number of entries in the register array is less than the number of pages in near memory. Remapping logic determines that a far memory address of the requested data is absent from the register array and selects an available near memory address from the register array. Remapping logic also initiates writing of the requested data at the far memory address to the selected near memory address. Remapping logic further writes the far memory address to an entry of the register array corresponding to the selected near memory address.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Christopher B. Wilkerson, Alaa R. Alameldeen, Zhe Wang, Zeshan A. Chishti
  • Patent number: 9576630
    Abstract: A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: February 21, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Dinesh Maheshwari
  • Patent number: 9563734
    Abstract: In some embodiments, in a method performed by at least one processor, a cell is characterized, by the at least one processor, with respect to an input transition characteristic considering different circuit topologies of a pre-driver driving the cell resulting in the same input transition characteristic.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: February 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen, Chung-Hsing Wang
  • Patent number: 9530499
    Abstract: According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory stores data pieces and search information including entries, where each entry is associated with a search key for specifying one data piece and a real address at which the data piece is stored. Upon reception of a first command, the controller, when the first command specifies a search key, outputs one data piece corresponding to one entry which includes the search key, and when the first command specifies one real address, outputs one data piece corresponding to one entry including the real address.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: December 27, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke Bando, Atsuhiro Kinoshita, Atsushi Kunimatsu
  • Patent number: 9496047
    Abstract: In various embodiments, a memory cell and a memory are provided. The memory cell comprises a Static Random Access Memory (SRAM) cell including a reset-set (RS) flip-flop and a Read Only Memory (ROM) cell being connected (or coupled) to the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered. The size of the memory cells proposed in an embodiment of the invention is much smaller than the sum of the size of ROM cells and the size of SRAM cells with the capacity of the memory cells same as the sum of the capacity of the ROM cells and the capacity of the SRAM cells.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: November 15, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Jun Yang, Hwong-Kwo Lin, Hua Chen, Yong Li, Ju Shen
  • Patent number: 9424380
    Abstract: A system and a method are disclosed for performing static timing analysis. Information describing a distorted input waveform is received by a static timing analyzer. A transition time of the distorted input waveform is determined. Based on the determined input transition time a nominal input waveform and a corresponding nominal output waveform are received. An input waveform distortion is computed based on the nominal input waveform and the distorted input waveform. An output waveform distortion is computed based on an augmented circuit and the input waveform distortion. A distorted output waveform is computed based on the nominal output waveform and the output waveform distortion. The waveforms are represented using the distortion values which are smaller than the actual waveform values, thereby allowing for compact representation. A time-shifted version of an uncoupled input waveform is used to perform conservative timing analysis of circuits that accounts for crosstalk in the circuit.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: August 23, 2016
    Assignee: Synopsys, Inc.
    Inventors: Jiayong Le, Peivand Fallah Tehrani, Li Ding, Xin Wang, Ahmed Shebaita
  • Patent number: 9418715
    Abstract: A semiconductor device includes a buffer block configured to generate a strobe signal by buffering an external strobe signal inputted through a first pad, output the strobe signal to a first node of a first input/output line, generate data by buffering external data inputted through a second pad, and output the data to a second node of a second input/output line; a first channel configured to store the data loaded on the second input/output line in synchronization with the strobe signal loaded on the first input/output line; and a second channel configured to store the data loaded on the second input/output line in synchronization with the strobe signal loaded on the first input/output line.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: August 16, 2016
    Assignee: SK HYNIX INC.
    Inventor: Byung Deuk Jeon
  • Patent number: 9355021
    Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: May 31, 2016
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Kishore Kasamsetty
  • Patent number: 9153329
    Abstract: A method for data storage includes defining, in a memory that includes multiple analog memory cells, an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states. Data is initially stored in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states. After initially storing the data, a second group of the analog memory cells, which potentially cause interference to the first group, is programmed. After programming the second group, the first group is selectively re-programmed with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: October 6, 2015
    Assignee: Apple Inc.
    Inventors: Naftali Sommer, Uri Perlmutter, Shai Winter
  • Patent number: 9030887
    Abstract: A semiconductor memory device includes an address decoder to decode an address specifying pseudo-multiport cells in memory blocks, a first word line driver to output a word line selection signal selecting one of word lines of one of the pseudo-multiport cells based on a row address in the address, and a second word line driver having an output part to output the word line selection signal into one of a pair of the word lines of the pseudo-multiport cell, and a NOR logic part to output NOR of the word line selection signal and a read/write selection signal into the other one of the pair of the word lines, the read/write selection signal selecting writing or reading operations. The second word line driver activates the pair of the word lines for writing data, and activates one of the pair of the word lines for reading data.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: May 12, 2015
    Assignee: FUJITSU Limited
    Inventor: Hirotoshi Sasaki
  • Patent number: 9019778
    Abstract: A semiconductor apparatus includes a memory chip which includes: a memory area; a data input/output block configured to communicate with the memory area; and a data transmission/reception block configured to connect one of a plurality of channels and a pad to the data input/output block, wherein the plurality of channels are configured to input and output normal data to and from another chip, and the pad is configured to input and output test data.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Young Ju Kim, Sang Hoon Shin
  • Patent number: 9019776
    Abstract: A memory access circuit includes a write data circuit and a first write switch circuit. The write data circuit is used for receiving double data rate data or single data rate data, and outputting odd term data and even term data of adjusted double data rate data or adjusted single data rate data. The first write switch circuit is used for outputting the odd term data of the adjusted double data rate data to an odd block of a memory and outputting the even term data of the adjusted double data rate data to an even block of the memory when the write data circuit receives the double data rate data, and outputting the adjusted single data rate data to the even block or the odd block of the memory when the write data circuit receives the single data rate data.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: April 28, 2015
    Assignee: Etron Technology, Inc.
    Inventors: Chih-Huei Hu, Chia-Wei Chang, Der-Min Yuan
  • Patent number: 9019779
    Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: April 28, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Terry R. Lee, Joseph Jeddeloh
  • Patent number: 9007813
    Abstract: A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Saito, Takanori Matsuzaki, Shuhei Nagatsuka, Hiroki Inoue
  • Patent number: 9007850
    Abstract: A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hyun Joo, Il-Han Park, Ki-Hwan Song
  • Patent number: 8982606
    Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: March 17, 2015
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Se Ho Lee
  • Patent number: 8964483
    Abstract: A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power supply is supplied in the second circuit region in which the parallel data and serial data are bidirectionally converted. The first through electrode group includes through electrodes supplying the first power supply to the first circuit region, and the second through electrode group includes through electrodes supplying the second power supply to the second circuit region.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 24, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Kazuhiko Kajigaya, Kazuo Ono, Tomonori Sekiguchi
  • Patent number: 8964485
    Abstract: A memory circuit includes a memory cell, a data line coupled to the memory cell, a sense amplifier having an input terminal, a precharge circuit coupled to the input terminal of the sense amplifier, a first transistor of a first type, and a second transistor of the first type. The first transistor is coupled between the input terminal of the sense amplifier and the data line, and the second transistor is coupled between to the input terminal of the sense amplifier and the data line. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage lower than the first threshold voltage.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chou-Ying Yang, Yi-Cheng Huang, Shang-Hsuan Liu
  • Patent number: 8949504
    Abstract: A memory device is provided, including a first memory die, a second memory die and a controller. The first memory die has a first system block. The second memory die has a second system block. The controller is coupled to the first and second memory dies through a chip enable lane in order to write the same in-system programming codes (ISP codes) to the first and second system blocks, in which, when the memory device is turned on, the controller reads the ISP code from the first system block or the second system block.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: February 3, 2015
    Assignee: Silicon Motion, Inc.
    Inventors: Wei-Lun Yan, Chun-Yi Lo
  • Patent number: 8947943
    Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: February 3, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Toru Ishikawa
  • Patent number: 8942056
    Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: January 27, 2015
    Assignee: Rambus Inc.
    Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
  • Patent number: 8929153
    Abstract: Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells. A method may include asserting, during a first read operation, a first read word line connected to a first subset of a plurality of bit cells arranged in a row of bit cells, and asserting, during a second read operation, a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: January 6, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Chirag Gulati, Rakesh Kumar Sinha, Ritu Chaba, Sei Seung Yoon
  • Patent number: 8929154
    Abstract: A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jacklyn Chang, Derek C. Tao, Yukit Tang, Kuoyuan (Peter) Hsu
  • Patent number: 8929130
    Abstract: A memory cell is provided. The memory cell comprises a write port and a read port. The write port comprises a pair of cross-coupled inverters and a plurality of metal lines. The first inverter comprises a first pull-up device and a first pull-down device. The second inverter comprises a second pull-up device and a second pull-down device. The metal lines comprise a Vcc conductor line, a first Vss conductor line, and a second Vss conductor line. The first pull-down device has a source terminal coupled to the first Vss line. The second pull-down device has a source terminal coupled to the second Vss line. The read port comprises a cascaded device, a read word line, read bit line and a third Vss conductor line. The cascaded device comprises a read pull-down device and a read pass device. The read pull-down device has a source terminal coupled to the third Vss conductor line. The read pass device has a drain terminal coupled to the read bit line.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Jhon-Jhy Liaw
  • Patent number: 8923076
    Abstract: A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 8923090
    Abstract: A decoder circuit to decode an address for accessing a memory cell in a memory array includes address latch circuitry, inverter circuitry, and first address pre-decode circuitry. The address latch circuitry receives an address signal and generates address holding signals during a setup period. The address latch circuitry latches the address holding signals during an address hold period following the setup period. The inverter circuitry receives the address signal and generates a complementary address signal. The first address pre-decode circuitry decodes the address signal and the address holding signals during the setup period to generate a first pre-decode address signal at an output of the first address pre-decode circuitry. In addition, the first address pre-decode circuitry decodes the address holding signals during the address hold period to maintain the first pre-decode address signal at the output of the first address pre-decode circuitry.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: December 30, 2014
    Assignee: LSI Corporation
    Inventors: Donald A. Evans, Rasoju V. Chary, Jeffrey C. Herbert, Rahul Sahu, Rajiv K. Roy
  • Patent number: 8913422
    Abstract: Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Brian S. Doyle, Kaan Oguz, Satyarth Suri, Robert S. Chau, Charles C. Kuo, Mark L. Doczy, David L. Kencke
  • Patent number: 8891279
    Abstract: A mechanism is provided in a data processing system for enhancing wiring structure for a cache supporting an auxiliary data output. The mechanism splits the data cache into a first data portion and a second data portion. The first data portion provides a first set of data elements and the second data portion provides a second set of data elements. The mechanism connects a first data path to provide the first set of data elements to a primary output and connects a second data path to provide the second set of data elements to the primary output. The mechanism feeds the first data path back into the second data path and feeds the second data path back into the first data path. The mechanism connects a secondary output to the second data path.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christian Habermann, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast
  • Patent number: 8867287
    Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jin Youp Cha, Jae Il Kim