Including Signal Comparison Patents (Class 365/189.07)
  • Patent number: 10790266
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: September 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Mikihiko Ito, Masaru Koyanagi, Masafumi Nakatani, Masahiro Yoshihara, Shinya Okuno, Shigeki Nagasaka
  • Patent number: 10789182
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • Patent number: 10770152
    Abstract: Methods of operating a memory device include comparing input data to data stored in strings of series-connected memory cells coupled to a data line, generating a respective resistance in series with each string of series-connected memory cells while comparing the plurality of digits of input data to the stored data, comparing a representation of a level of current in the data line to a reference, deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than the reference, and deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
  • Patent number: 10748642
    Abstract: A method of setting a read voltage by a memory controller and a storage device are provided. The method includes controlling a memory device to read data from memory cells by applying a test read voltage to a selected word line; receiving, from the memory device, cell count information corresponding to a read operation of the memory device, and renewing the test read voltage by using the cell count information and a cost function to find an optimum read voltage, the cost function being determined for each read voltage level; and determining a read voltage by performing the controlling of the memory device and the renewing of the test read voltage at least once.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-hoon Kim, Jun-jin Kong, Hong-rak Son, Pil-sang Yoon
  • Patent number: 10741242
    Abstract: Memory devices are provided. A memory device includes a voltage generation circuit that includes an offset compensator configured to receive a reference voltage and an offset code and to link the offset code to the reference voltage. The voltage generation circuit includes a comparator configured to compare the reference voltage linked to the offset code with a bit line pre-charge voltage and to output driving control signals. The voltage generation circuit includes a driver configured to output the bit line pre-charge voltage at a target level of the reference voltage in response to the driving control signals. The voltage generation circuit includes a background calibration circuit configured to generate the offset code for performing control so that a target short current flows through an output node of the driver from which the bit line pre-charge voltage is output. Related methods of generating a bit line pre-charge voltage are also provided.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-hun Seo, Seung-hyun Cho, Chang-ho Shin, Yong-jae Lee
  • Patent number: 10734983
    Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 4, 2020
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Rakesh L. Notani, Kai Lun Hsiung, Yanzhe Liu
  • Patent number: 10734063
    Abstract: A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Koji Nii
  • Patent number: 10726907
    Abstract: An electronic device includes: a memory cell configured to store electric charge for representing a data value, wherein the memory cell is configured to store two or more levels of the electric charge corresponding to different data values; a preamplifier operably coupled to the memory cell, the preamplifier having a common source and configured to generate an amplified signal based on amplifying a difference in the two or more levels of the stored electric charge; and a sense amplifier operably coupled to the preamplifier, the sense amplifier configured to further process the amplified signal for determining the data value stored in the memory cell.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 10679692
    Abstract: A memory apparatus and a majority detector thereof are provided. The majority detector includes a pull-up circuit, a first switch, a second switch, a plurality of first transistors, a plurality of second transistors and a sense amplifying circuit. The pull-up circuit provides a first voltage to a first node and a second node according to a control signal before a sensing period. The first switch and the second switch provide a second voltage to the first node and the second node respectively according to the control signal during the sensing period. Control ends of the first transistors each receives one of a plurality of values of a data signal. Control ends of the second transistors each receives an inverse value of the one of the values of the data signal. The sense amplifying circuit generates a sensing result according to a voltage difference between the first node and the second node during the sensing period, and the sensing result indicates a majority value among the values.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 9, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Yuji Nakaoka
  • Patent number: 10672498
    Abstract: A repair device and a semiconductor device including the same are disclosed, which relate to a technology for a Post Package Repair (PPR) device. The repair device includes: a clock generator configured to generate a fuse clock signal based to corresponding to an available fuse; a fuse selection circuit configured to discriminate between a first clock signal and a second clock signal in the fuse clock signal; a fuse signal generator configured to output a first repair signal corresponding to the first clock signal and a second repair signal corresponding to the second clock signal during a post package repair (PPR) mode; and an output circuit configured to output a first output signal by detecting address information of the remaining unused fuses in response to the first repair signal, or configured to output a second output signal by detecting address information of the remaining unused fuses.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventor: Jong Sam Kim
  • Patent number: 10672469
    Abstract: A device comprises a first block of memory cells, a second block of memory cells to store a feature array, and a third block of memory cells to store an array of output values. Sensing circuitry is coupled to the first block of memory cells and the second block of memory cells to compare electrical differences between the memory cells in the first block and the memory cells in the second block to generate the array of output values. Writing circuitry is operatively coupled to the third block to store the array of output values in the third block of memory cells.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 2, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hsiang-Lan Lung
  • Patent number: 10664407
    Abstract: A set of data entries is transferred via a memory mapped interface from an external peripheral device to a processor device and is stored in a shared memory region. Based on a first pointer to the shared memory region, a first process executed by the processor device processes a first group of the data entries. Based on a second pointer to the shared memory region, a second process executed by the processor device processes a second group of the data entries. The second process indicates the second pointer to the first process. The first process indicates a lower one of the first pointer and the second pointer to the peripheral device.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Anant Raj Gupta, Ingo Volkening, Jun Ye Zhou
  • Patent number: 10665314
    Abstract: Methods and apparatuses are provided for self-trimming of a semiconductor device. An example self-trimming circuit includes a control circuit configured to, during a self-trimming operation, decode a test command signal to set a target voltage and set a voltage trim code to an initial value, and to adjust a value of the voltage trim code based on a stop signal. The example self-trimming circuit further includes a reference voltage regulator configured to receive the voltage trim code and to convert a band-gap reference voltage to an output voltage based on the voltage trim code, and a comparator configured to compare the target voltage with the output voltage and to provide the stop signal having a value based on the comparison.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Miguel Jimenez-Olivares, Maksim Kuzmenka
  • Patent number: 10658014
    Abstract: A memory device includes memory cell blocks, bit line sense amplifier blocks, and a control circuit connected to one or more of the bit line sense amplifier blocks arranged between the memory cell blocks. The control circuit controls levels of currents respectively supplied to a first sensing driving voltage line and a second sensing driving voltage line driving bit line sense-amplifiers, to be constant. A first sensing driving control signal and/or a second sensing driving control signal, output from the sensing-matching control circuit is provided to the bit line sense amplifiers in all of the bit line sense amplifier blocks, so that the bit line sense amplifiers are constantly driven based on the constant levels of currents supplied to the first sensing driving voltage line and the second sensing driving voltage line.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 19, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-su Lee, Jong-cheol Kim
  • Patent number: 10643673
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 10643717
    Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan S. Parry, George B. Raad, James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10622034
    Abstract: The present disclosure includes apparatuses and methods related to performing a greater vector determination in memory. An example apparatus comprises a first group of memory cells coupled to a sense line and to a number of first access lines and a second group of memory cells coupled to the sense line and to a number of second access lines. The example apparatus comprises a controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Tiwari
  • Patent number: 10600494
    Abstract: Methods and apparatuses are provided for self-trimming of a semiconductor device. An example apparatus includes a semiconductor device including a self-trimming circuit configured to receive a reference voltage and a test command signal. The self-trimming circuit is configured to convert the reference voltage to a target voltage based on the test command signal and further configured to adjust a voltage trim code until an internal voltage matches the target voltage to determine a trim level associated with the internal voltage.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Miguel Jimenez-Olivares, Maksim Kuzmenka
  • Patent number: 10585603
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 10, 2020
    Assignee: Unity Semiconductor Corporation
    Inventor: Chang Hua Siau
  • Patent number: 10580479
    Abstract: A self-time circuitry is coupled to a first power rail to receive a first voltage and a second power rail to receive a second voltage. The self-time circuitry includes a tracking control circuit which generates a first tracking signal at the first voltage and a second tracking signal at the second voltage. In response to a memory access request, a first number of dummy discharge cells (DDCs) in a first DDC group are activated according to the first tracking signal to discharge a dummy bit line (DBL), and a second number of DDCs in a second DDC group are activated according to the second tracking signal to discharge the DBL. The DBL mimics operations of a bit line in a memory cell array and the DDCs in the first DDC group and the second DDC group mimic operations of bit cells in the memory cell array.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 3, 2020
    Assignee: MEDIATEK Singapore Pte. Ltd.
    Inventors: Manish Trivedi, Dharin Nayeshbhai Shah
  • Patent number: 10579518
    Abstract: A memory management method is provided. The method includes selecting a target physical programming unit; using a first read voltage corresponding to a first type physical page of the target physical programming unit to read a plurality of target memory cells of the target physical programming unit, so as to calculate a first bit value ratio; if the first bit value ratio is not smaller than a first preset threshold, using a second read voltage corresponding to the first type physical page of the target physical programming unit to read the plurality of target memory cells of the target physical programming unit, so as to calculate a second bit value ratio; and determining whether the first type physical page of the target physical programming unit is empty by comparing the first bit value ratio and the second bit value ratio.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 3, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Yu-Hua Hsiao, Li-Hsun Liu
  • Patent number: 10553260
    Abstract: A stacked memory device includes; a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
  • Patent number: 10552087
    Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Frank F. Ross, Randall J. Rooney
  • Patent number: 10529408
    Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: January 7, 2020
    Assignee: Rambus Inc.
    Inventors: Jade M. Kizer, Sivakumar Doraiswamy, Benedict Lau
  • Patent number: 10529430
    Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
  • Patent number: 10529393
    Abstract: An exemplary embodiment includes a method of controlling a semiconductor device. The semiconductor device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, a row decoder for receiving a row address and selecting a word line corresponding to the row address, a column decoder for receiving a column address and selecting a bit line corresponding to the column address, a sense amplifier for reading data stored in a memory cell connected to the selected word line and the selected bit line, and a data output driver. The method includes setting a calibration code for a driver control code, to control an initial current strength of the data output driver, and changing the calibration code to change the driver control code during a read or write operation for the memory cell array.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungjun Shin, Tae Young Oh
  • Patent number: 10515028
    Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: December 24, 2019
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Brijesh Tripathi, Kiran Kattel, Rakesh L. Notani, Fabien S. Faure, Sukalpa Biswas, Kai Lun Hsiung, Neeraj Parik, Venkata Ramana Malladi, Shiva Kumar, Chaitanya Polapragada, Allen Kim
  • Patent number: 10496328
    Abstract: A memory control circuit of the disclosure includes a memory control unit that controls a timing of command issuance to cause (tATP+tPTA) to be constant, where, in a memory having a plurality of banks, tATP is a period from issuance of a first ACT command to issuance of a PRE command that is directed a bank same as or different from a bank to which the first ACT command is issued, and tPTA is a period from the issuance of the PRE command to issuance of a second ACT command that is directed to a bank same as or different from the bank to which the PRE command is issued.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: December 3, 2019
    Assignee: Sony Corporation
    Inventor: Takahiro Ikarashi
  • Patent number: 10497422
    Abstract: A memory device includes a memory cell array, a refresh controller, and control logic. The memory cell array includes a plurality of rows. The refresh controller performs a refresh operation on the plurality of rows. The control logic controls a care operation on a first adjacent region that is most adjacent to a first row based on a number of times the plurality of rows are accessed during a first period. The control logic also controls a care operation on a second adjacent region that is second adjacent to a second row based on a number of times the plurality of rows are accessed during a second period. The first and second periods are different periods.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-jun Lee, Seung-jun Shin, Hoon Sin, Ik-joon Choi, Ju-seong Hwang
  • Patent number: 10496569
    Abstract: A semiconductor integrated circuit according to an embodiment includes: a first memory bank that performing a read operation and outputting first data in accordance with a first clock signal; a second memory bank performing a read operation and outputting second data in accordance with the first clock signal; a configurable decoder supplying address information to the first and second memory banks; and an output module reconfigurable in one of a first and second modes, the first mode including a function of holding the first and second data in accordance with the first clock signal, and selecting and outputting the first data or the second data in accordance with a second clock signal having a frequency at least twice higher than the first clock signal, the second mode including a function of selecting and outputting the first data or the second data in accordance with the first clock signal.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: December 3, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kosuke Tatsumura
  • Patent number: 10490265
    Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: November 26, 2019
    Assignee: Apple Inc.
    Inventors: Brian J. Campbell, Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam
  • Patent number: 10482950
    Abstract: The present application relates to an improved static random access memory (SRAM) device having a plurality of storage cells and a separate read/write circuit. Each of the plurality of storage cells is connected to a read/write data node of the read/write circuit by a dedicated connection, and an access switch which permits read/write access to the storage cell. The dedicated connection exhibits a greater capacitance than the read/write data node of the read/write circuit, such that the primary read mechanism of the SRAM is charge equalization. The SRAM write data connection to the read/write node of the read/write circuit, to permit data to be written to the plurality of storage cells. Write assist techniques are disclosed which assist writing of a ‘1’ to the plurality of storage cells.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: November 19, 2019
    Assignee: PLATIPUS LIMITED
    Inventor: Robert Charles Beat
  • Patent number: 10484007
    Abstract: Disclosed may be a repair information storage circuit. The repair information storage circuit may include a fuse set. A plurality of fuses included in the fuse set may be allocated to the respective bits of preliminary repair information and defect check information. The fuse allocated to the defect check information may be ruptured to store information on whether the fuse set has a defect.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: November 19, 2019
    Assignee: SK hynix Inc.
    Inventor: Woo Hyun Paik
  • Patent number: 10475519
    Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: November 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan S. Parry, George B. Raad, James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10446246
    Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 15, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do
  • Patent number: 10438642
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. For example, a switching component connected to a digit line may also be connected to an offset capacitor selected to compensate for a threshold voltage offset. The offset capacitor may be discharged in conjunction with a read operation, resulting in a threshold voltage applied to the switching component. This may enable all or substantially all of the stored charge of the ferroelectric memory cell to be extracted and transferred to a sense capacitor through the transistor. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10438646
    Abstract: Apparatuses and methods for providing power for memory refresh operations are described. An example apparatus includes refresh circuits, a power amplifier, a power circuit, and a power control circuits. The refresh circuits are configured to refresh memory cells of a memory bank. The power amplifier is configured to provide power when activated to the refresh circuits. The power provided by the power amplifier has a first voltage. The power circuit is configured to receive a power supply voltage and to provide power when activated to the refresh circuits. The power provided by the power amplifier has a second voltage. The power control circuit is configured to compare the first voltage and the target voltage and to provide an activation signal to control activation of the power circuit having an active duration based at least in part on the comparison.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jason M. Brown, Harish N. Venkata
  • Patent number: 10424349
    Abstract: A semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to output data from the memory cell coupled to each of the bit lines through a global input/output line; a flag-generating circuit configured to generate a flag signal received with respect to the bit lines. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal based on number of data having a specific logic level among the data in the memory cell for each of the bit lines that may be provided through the global input/output line in a read operation; and an output circuit configured to output the data based on at least one of the duplicate data flag signal and the data bus is inversion flag signal.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 24, 2019
    Assignee: SK hynix Inc.
    Inventor: Yoo Jong Lee
  • Patent number: 10423667
    Abstract: A method for generating a pattern matching machine for identifying matches of a plurality of symbol patterns in a sequence of input symbols, the method comprising: providing a state machine of states and directed transitions between states corresponding to the plurality of patterns; applying an Aho-Corasick approach to identify mappings between states in the event of a failure, of the state machine in a state and for an input symbol, to transition to a subsequent state based on the directed transitions of the state machine, characterized in that one of the symbol patterns includes a wildcard symbol, and mappings for one or more states representing pattern symbols including the wildcard symbol are based on an input symbol to be received, by the pattern matching machine in use, to constitute the wildcard.
    Type: Grant
    Filed: November 27, 2014
    Date of Patent: September 24, 2019
    Assignee: British Telecommunications PLC
    Inventor: James Mistry
  • Patent number: 10410697
    Abstract: A sensing circuit includes a sensing stage. The sensing stage includes a voltage clamp, a P-type transistor and an N-type transistor. The voltage clamp receives a first power supply voltage and generates a second power supply voltage. The source terminal of the P-type transistor receives the second power supply voltage. The gate terminal of the P-type transistor receives a cell current from a selected circuit of a non-volatile memory. The drain terminal of the N-type transistor is connected with the drain terminal of the P-type transistor. The gate terminal of the N-type transistor receives a bias voltage. The source terminal of the N-type transistor receives a ground voltage. In a sensing period, the second power supply voltage from the voltage clamp is fixed and lower than the first power supply voltage.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: September 10, 2019
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Chun Chen, Chun-Hung Lin, Cheng-Da Huang
  • Patent number: 10394724
    Abstract: Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: August 27, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jungwon Suh, Dexter Chun, Haw-Jing Lo
  • Patent number: 10395719
    Abstract: A memory device includes a storage circuit, a first driving circuit, and a second driving circuit. The storage circuit stores first data and compares the first data and second data. The first driving circuit selectively drives a matching line to a first logic state, depending on a comparison result of the first data and the second data by the storage circuit. The second driving circuit drives the matching line to a second logic state regardless of the comparison result.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: August 27, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Cheol Kim, Kee-Won Kwon, Ji-Su Min, Rak-Joo Sung, Sung-gi Ahn
  • Patent number: 10397116
    Abstract: Disclosed are techniques that can be used within network devices to implement access control functionality. The techniques can include use of a content-addressable memory configured including an access control entry stored therein. Circuitry can be coupled to the content-addressable memory and configured to determine that a value is within a range of values. The circuitry can generate a compare key including a field that is set indicating that the value is within the range of values. The circuitry can provide, to the content-addressable memory, the compare key for locating a corresponding access control entry within the content-addressable memory. The circuitry can receive, from the content-addressable memory, an index of the access control entry stored within the content-addressable memory. The circuitry can select, based on the index of the access control entry, an action.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: August 27, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Thomas A. Volpe, Chin Cheah
  • Patent number: 10389838
    Abstract: Disclosed are various embodiments for client-side predictive caching of content to facilitate use of the content. If account is likely to commence use of a content item through a client, the client is configured to predictively cache the content item before the use is commenced. In doing so, the client may obtain an initial portion of the content item from another computing device. The client may then initialize various resources to facilitate use of the content item by the client. The client-side cache may be divided into multiple segments with different content selection criteria.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 20, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Lei Li, Andrew Jason Ma, Gurpreet Singh Ahluwalia, Abhishek Dubey, Sachin Shah, Vijay Sen, Gregory Scott Benjamin, Prateek Rameshchandra Shah, Cody Wayne Maxwell Powell, Meltem Celikel, Darryl Hudgin, James Marvin Freeman, II, Aaron M. Bromberg, Bryant F. Herron-Patmon, Nush Karmacharya, Joshua B. Barnard, Peter Wei-Chih Chen, Stephen A. Slotnick, Andrew J. Watts, Richard J. Winograd
  • Patent number: 10373658
    Abstract: A semiconductor module may include a host, a first semiconductor device, and a second semiconductor device. The first host line may be connected to the first and second semiconductor device or devices, according to a set mode.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventor: Sang Jin Byeon
  • Patent number: 10365318
    Abstract: A method of providing a temperature value from a dynamic random access memory (DRAM) device can include receiving a test mode command that activates a temperature value output mode of operation; providing the temperature value to an output buffer circuit; providing an enable signal to the output buffer circuit; and outputting the temperature value that indicates a temperature range, the temperature value is outputted from the output buffer circuit to at least one terminal that is electrically connected external to the DRAM device; wherein the temperature value includes at least 5 binary bits.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 30, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10339984
    Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Patent number: 10331377
    Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Naveen Vittal Prabhu, Aliasgar S. Madraswala, Simon Ramage
  • Patent number: 10332605
    Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
  • Patent number: 10319420
    Abstract: A sense circuit includes memory cell characterization circuitry, storage circuitry, switching circuitry, and bit line biasing circuitry. The sense circuit is configured to perform a sense operation to sense a characterization of a memory cell. During a pre-charge phase, the memory cell characterization circuitry and the bit line biasing circuitry set differential voltages in the storage circuitry to levels dependent on input offset voltages according to certain polarities. The storage circuitry maintains the differential voltages during the sense phase, allowing the memory cell characterization circuitry to cancel output the input offset voltages when generating output voltages used to identify a characterization of the memory cell. The memory cell characterization circuitry also generates its output voltage based on a reference current through a reference bit line.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: June 11, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Yingchang Chen, Chun-Ju Chu