Including Signal Comparison Patents (Class 365/189.07)
  • Patent number: 11417370
    Abstract: A method of operating a memory device is provide. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compare with a clock cycle period to determine that the power nap period is less that the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chen Lin, Wei Min Chan
  • Patent number: 11416549
    Abstract: A computer implemented method of storing a data object in a computer memory, wherein the data object is stored at a location in an object store as a portion of the memory, the location being determined by a hashing process based on a generated hash key, the memory further storing: a set of binary words in which each bit of each word identifies an occupancy state of a location in the object store such that an occupancy state of all locations is stored in the set of binary words; and a truncated hash key set storing, for each occupied location in the object store, a truncated hash key for a data object stored at the location, wherein the hashing process uses linear probing in which an occupancy of the location in the object store for storage of the data object is determined, wherein the occupancy is determined by reference to the set of binary words, and the linear probing further determines identity of the data object and an object stored in an occupied location, the identity being determined based on a compar
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 16, 2022
    Assignee: BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY
    Inventor: Philip Clapham
  • Patent number: 11353946
    Abstract: The invention introduces a non-transitory computer program product for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: June 7, 2022
    Assignee: SILICON MOTION, INC.
    Inventors: Chang-Wei Shen, Te-Kai Wang, Pin-Hua Chen
  • Patent number: 11355178
    Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 11295795
    Abstract: The present disclosure provides a data reading circuit and a storage unit. The data reading circuit includes a being read unit connected to a voltage stabilizing unit and configured to store data. The voltage stabilizing unit is configured to stabilize and output a current from the being read unit to a first amplifying unit. The first amplifying unit is configured to amplify and output the current from the being read unit to a comparing unit. A reference unit is connected to a second amplifying unit, to output a reference current to the second amplifying unit. The second amplifying unit is configured to amplify and output the reference current to the comparing unit. The comparing unit is configured to compare a comparing point voltage, that is based on the amplified current of the being read unit and the amplified reference current, with a reference voltage and to output comparison results.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: April 5, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Tengye Wang, Jiaxu Peng, Tao Wang, Zijian Zhao
  • Patent number: 11276463
    Abstract: Systems and methods for performing a pattern matching operation in a memory device are disclosed. The memory device may include a controller and memory arrays where the memory arrays store different patterns along bit lines. An input pattern is applied to the memory array(s) to determine whether the pattern is stored in the memory device. Word lines may be activated in series or in parallel to search for patterns within the memory array. The memory array may include memory cells that store binary digits, discrete values or analog values.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Dmitri Yudanov
  • Patent number: 11277271
    Abstract: A plurality of memory cells, in which each memory cell includes two corresponding supply terminal inputs, is powered up while applying a voltage differential between the corresponding supply terminal inputs for each of the plurality of memory cells. After powering up, the plurality of memory cells is read and a physically unclonable function (PUF) response is generated from data of the reading.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 15, 2022
    Assignee: NXP USA, Inc.
    Inventors: Glenn Charles Abeln, Nihaar N. Mahatme
  • Patent number: 11257563
    Abstract: The present application discloses an apparatus for testing defects of a memory module comprises a central buffer for generating a test write command and a test read command to indicate testing to a target address in a memory module; and a data buffer coupled to the central buffer to receive the test write command and the test read command; the data buffer is configured to, in response to the test write command, use target data as repair data corresponding to the target address, and write the target data into the memory module; and, in response to the test read command, to read target data from the target address and compare the target data with the repair data, and to send to the central buffer a comparison result of the target data and the repair data; the central buffer is further configured to record the target address as a tested address when generating the test write command, and determine whether to add the tested address to defective address information based on the comparison result associated with th
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: February 22, 2022
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Gang Shan, Yong Zhang
  • Patent number: 11250905
    Abstract: A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: February 15, 2022
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Neal Berger, Yuniarto Widjaja
  • Patent number: 11243559
    Abstract: Modern integrated circuits have an increasing need for various levels of both supply voltage (V) and operating frequency (f) available at fine spatial and temporal granularity. This work introduces a solution that provides a number and quality of locally distributed V/f domains through FOPAC. Opportunistically sharing design resources and features between multi-phase voltage regulators (MPVRs) and resonant rotary clocks (ReRoCs) enabling i) the scalability to hundreds of domains, ii) fast switching times for both voltage and frequency, leading to temporal flexibility, and iii) locally distributed designs, leading to spatial flexibility.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: February 8, 2022
    Assignee: Drexel University
    Inventors: Baris Taskin, Ragh Kuttappa, Selcuk Kose
  • Patent number: 11211111
    Abstract: A content-addressable memory (CAM) storage element includes bit storage cell bit comparison cells. The bit storage cell is arranged on a first die tier and includes at least one transistor, one or two bit lines, and a storage node. The bit comparison cell is arranged on a second die tier and has a match line, complementary search lines, and at least three transistors. The complementary search lines are decoupled from the bit line(s). A 3D connection couples the storage node to one of the transistors of the second die tier. The CAM cell performs at least one CAM search per clock cycle using at least four transistors per search, including the at least one transistor of the bit storage cell and the at least three transistors of the bit comparison cell, and to output results of the at least one CAM search on the match line.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: December 28, 2021
    Assignee: Arm Limited
    Inventors: Rahul Mathur, Mudit Bhargava, Supreet Jeloka, Andy Wangkun Chen
  • Patent number: 11205464
    Abstract: A semiconductor apparatus includes a first receiver, a second receiver, a first delay line, and a second delay line. The first receiver receives an input signal using a first supply voltage. The first delay line delays an output of the first receiver based on a first delay control signal and a first complementary delay control signal to generate a received signal. The second receiver receives a clock signal using a second supply voltage. The second delay line delays an output of the second receiver based on a second delay control signal and a second complementary delay control signal to generate a received clock signal. Delay amounts of the first and second delay lines are complementarily changed based on the first and second supply voltages.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Soon Sung An, Kwan Su Shon
  • Patent number: 11200001
    Abstract: A system to send a first command to a first memory die of a plurality of memory dies of a memory sub-system the first command to execute an initialization process. The system reads a first bit value from the first memory die, the first bit value indicating the first memory die is executing a peak current phase of the initialization process. The system reads a second bit value from the first memory die, the second bit value indicating the first memory die is executing a safe phase of the initialization process. In response to reading the second bit value, a second command is sent to a second memory die to execute the initialization process.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Liang Yu, Jonathan Parry
  • Patent number: 11200922
    Abstract: Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: December 14, 2021
    Assignee: Arm Limited
    Inventors: Sriram Thyagarajan, Andy Wangkun Chen, Yew Keong Chong, Munish Kumar
  • Patent number: 11200945
    Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: December 14, 2021
    Assignee: ZENTEL JAPAN CORPORATION
    Inventors: Takashi Kubo, Masaru Haraguchi, Takeshi Hamamoto, Kenichi Yasuda, Yasuhiko Tsukikawa, Hironori Iga
  • Patent number: 11195564
    Abstract: A semiconductor device includes a memory cell array, a first pre-charge circuit, and a data line switching control circuit. The memory cell array includes a first data line, a second data line, and a third data line. The first pre-charge circuit is configured to pre-charge the first data line according to a first voltage level of a first equalizing signal. The data line switching control circuit is configured to disconnect the second data line from the third data line according to a second voltage level of a data line switching control signal in a standby operation of the semiconductor device, to perform charge sharing of the first equalizing signal and the data line switching control signal for a first time in an active operation of the semiconductor device, and to drive the data line switching control signal to the first voltage level.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventor: Kyeong Pil Kang
  • Patent number: 11183083
    Abstract: Some embodiments are directed to a cryptographic device, including a non-volatile memory, a range of the memory storing data, a selector arranged to receive a selector signal configuring a memory read-out unit for a regular read-out mode or for a PUF read-out mode of the same memory, a control unit arranged to send the selector signal to the selector configuring the memory read-out unit in the regular read-out mode, and reading the memory range to obtain the data, and send the selector signal to the selector configuring the memory read-out unit for PUF read-out mode and obtaining a noisy bit string from the memory range.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: November 23, 2021
    Assignee: INTRINSIC ID B.V.
    Inventors: Geert Jan Schrijen, Pim Theo Tuyls
  • Patent number: 11158373
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for determining extremum numerical values. Numerical values may be stored in files of a stack, with each bit of the numerical value stored in a content addressable memory (CAM) cell of the file. Each file may be associated with an accumulator circuit, which provides an accumulator signal. An extremum search operation may be performed where a sequence of comparison bits are compared in a bit-by-bit fashion to each bit of the numerical values. The accumulator circuits each provide an accumulator signal which indicates if the numerical value in the associated file is an extremum value or not. Examples of extremum search operations include finding a maximum of the numerical values and a minimum of the numerical values.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Jason M. Brown
  • Patent number: 11150903
    Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: October 19, 2021
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Lee-Lean Shu, Chao-Hung Chang, Avidan Akerib
  • Patent number: 11132384
    Abstract: A multi-column index is generated based on an interleaving of data bits for selectivity for efficient processing of data in a relational database system. Two or more columns may be identified for inclusion in the multi-column index for a relational database table. Based, at least in part, on the interleaving of data bits for selectivity from the identified columns, a multi-column index is generated for the relational database table that provides a respective index value for each entry in the relational database table. The entries of the relational database table may then be stored according to the index values of the multi-column index.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 28, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Anurag Windlass Gupta
  • Patent number: 11133069
    Abstract: A memory controller controlling a memory device including a plurality of memory cells includes a read operation controller performing a soft read operation on the plurality of memory cells by using a plurality of soft read voltages determined based on a default read voltage when a read operation for reading the plurality of memory cells by the default read voltage fails, and reading the plurality of memory cells by using an optimal read voltage determined according to a result of performing the soft read operation, and a read voltage setting circuit determining the optimal read voltage using voltage candidates being soft read voltages corresponding to at least two voltage intervals, among a plurality of voltage intervals determined according to the plurality of soft read voltages, the voltage candidates selected in ascending order of a number of memory cells having threshold voltages belonging to each of the plurality of voltage intervals.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: September 28, 2021
    Assignee: SK hynix Inc.
    Inventor: Yu Mi Kim
  • Patent number: 11132252
    Abstract: The memory device includes a content addressable memory (CAM) block including a plurality of pages, peripheral circuits configured to perform a CAM data read operation to read a CAM data comprising a plurality of check data each indicating whether bad block information is included in a region of the CAM data from a page sequentially selected among the plurality of pages, a CAM data read controller configured to perform a CAM data load operation to receive the CAM data from the peripheral circuits and output the CAM data to an external memory controller, and stop the CAM data load operation based on at least one check data among the plurality of check data included in the CAM data.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: September 28, 2021
    Assignee: SK hynix Inc.
    Inventors: Tae Ho Lee, Byung Ryul Kim, Dae Il Choi, Yong Hwan Hong
  • Patent number: 11127454
    Abstract: A semiconductor memory device includes a plurality of memory cells connected a pair of bit lines, a column selection circuit, and a sense amplifier. When the semiconductor memory device is in a data writing operation, the column selection circuit electrically connects a pair of data input and output lines to the pair of bit lines during a first time interval and a second time interval, consecutively arranged, and the sense amplifier electrically disconnects from the pair of bit lines during the first time interval, and senses and amplifies a voltage difference between the pair of bit lines during the second time interval.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Whiyoung Bae
  • Patent number: 11114139
    Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
  • Patent number: 11107531
    Abstract: A search circuit includes a content-addressable memory (CAM) including a plurality of CAM cells configured to store a plurality of entry data, each entry data including a first bit corresponding to a least significant bit through a K-th bit corresponding to a most significant bit, the CAM configured to provide a plurality of matching signals indicating whether each of the plurality of entry data matches searching data, and a CAM controller configured to perform a partial searching operation such that the CAM controller applies comparison bits corresponding to a portion of the first through K-th bits as the searching data to the CAM and searches for target entry data among the plurality of entry data based on the plurality of matching signals indicating that the corresponding bits of the target entry data match the comparison bits.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 31, 2021
    Inventor: Hyungjin Kim
  • Patent number: 11093166
    Abstract: A method of operating a memory system, which includes a memory controller and at least one non-volatile memory, includes storing, in the memory system, temperature-dependent performance level information received from a host disposed external to the memory system, setting an operation performance level of the memory system to a first performance level, operating the memory controller and the at least one non-volatile memory device according to the first performance level, detecting an internal temperature of the memory system, and changing the operation performance level of the memory system to a second performance level that is different from the first performance level. The operation performance level is changed by the memory controller of the memory system, and changing the operation performance level is based on the temperature-dependent performance level information and the detected internal temperature.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Seok Kim, Dae-Ho Kim, Yong-Geun Oh, Sung-Jin Moon
  • Patent number: 11079829
    Abstract: Exemplary methods, apparatuses, and systems include a first die in a power network receiving, from each of a plurality of dice in the power network, a first activity state value indicating that the respective die is in a high current state, a second activity state value indicating that the respective die is a moderate current state, or a third activity state value indicating that the respective die is a low current state. The received activity state values include at least one second or third activity state value. The first die determines, using the received activity state values, a first sum of the activity state values. The first die further selects an activity state based upon the first sum and sends, to the plurality of dice, an activity state value corresponding to the selected activity state.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 3, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jonathan S. Parry, David A. Palmer
  • Patent number: 11074973
    Abstract: A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry. The responder signal circuitry performs a calculation on a row of the memory array and generates a responder signal indicating that there is at least one cell in the row having a predefined value.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: July 27, 2021
    Assignee: GSI Technology Inc.
    Inventors: Avidan Akerib, Eli Ehrman
  • Patent number: 11061578
    Abstract: The progress of an erase operation for a memory device is monitored using an erase credit mechanism. In one approach, an erase operation is performed to erase a memory. Erase pulse slices used in the erase operation are monitored. Erase credits associated with the erase operation are determined. The erase credits include an erase credit associated with each of the erase pulse slices. Based on the erase credits, an extent of erasure of the memory is determined. In response to determining that the extent of erasure has reached a predetermined threshold, the erase operation is terminated.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Cariello, Fulvio Rori, Jung Sheng Hoei
  • Patent number: 11062772
    Abstract: A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 13, 2021
    Assignee: PANASONIC CORPORATION
    Inventors: Reiji Mochida, Kazuyuki Kouno, Takashi Ono, Masayoshi Nakayama, Yuriko Hayata
  • Patent number: 11043248
    Abstract: A Memory device comprising a matrix of memory cells, the matrix being provided with at least one first column, the device also being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical ‘1’, is greater than a predetermined threshold.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 22, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Philippe Noel, Reda Boumchedda, Bastien Giraud, Emilien Bourde-Cice
  • Patent number: 11023336
    Abstract: Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: June 1, 2021
    Assignee: NeuroBlade, Ltd.
    Inventors: Elad Sity, Eliad Hillel
  • Patent number: 11017858
    Abstract: A CAM/TCAM includes a plurality of rows of CAM/TCAM lines, a plurality of search lines, and a plurality of bit lines, wherein each row comprises an array of CAM/TCAM cells. Each TCAM cell has two storage cells, representing state for data and a mask of the cell, and match logic. The two storage cells connect to a respective bit line as input and their output drives the match logic. In response to the respective search line and storage outputs, the match logic generates cell match outputs. The match logic can be implemented using static logic comprising tristate gates and masking logic that forces the cell match output to a predetermined value in response to the stored mask value. The match outputs in the row are AND-ed by a logic tree to generate a match output, thereby reducing power consumption.
    Type: Grant
    Filed: December 25, 2016
    Date of Patent: May 25, 2021
    Inventor: Sudarshan Kumar
  • Patent number: 10984883
    Abstract: A memory management method includes identifying memory segments of a memory device. The method also includes identifying, for each memory segment, a number of faulty columns and determining a total number of faulty columns for the memory device. The method also includes, in response to a determination that the total number of faulty columns is greater than a threshold, identifying a memory segment having a highest number of faulty columns. The method also includes disabling the memory segment. Another method includes identifying, for each memory segment, a number of faulty memory blocks and determining a total number of faulty memory blocks. The method also includes, in response to a determination that the total number of faulty memory blocks is greater than a threshold, identifying a memory segment having a highest number of faulty memory blocks. The method also includes disabling the memory segment.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Sowjanya Tungala, Sini Balakrishnan, Sowjanya Sunkavelli, Sridhar Yadala, Dat Tran, Loc Tu, Kirubakaran Periyannan
  • Patent number: 10969997
    Abstract: A memory controller is described. The memory controller includes a register to collectively track row active commands sent to multiple memory chip banks of a memory rank.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventor: William Nale
  • Patent number: 10964404
    Abstract: A semiconductor device capable of detecting whether test operation is normal is provided. The semiconductor device includes a plurality of memory cells arranged in a matrix, a plurality of word lines provided corresponding to each of the rows of the plurality of memory cells respectively, a decoder for generating driving signals for driving the plurality of word lines, and a detection circuit provided between the plurality of word lines and the decoder for simultaneously raising the plurality of word lines by test operation and detecting whether or not the rising state of the plurality of word lines is normal.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 30, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshisato Yokoyama, Shinji Tanaka
  • Patent number: 10950312
    Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
  • Patent number: 10942873
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
  • Patent number: 10937495
    Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: March 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: He-Hsuan Chao, Ping-Kun Wang, Seow Fong Lim, Norio Hattori, Chien-Min Wu, Chih-Hua Hung
  • Patent number: 10936198
    Abstract: In a coprocessor performing data processing by supplementing functions of a CPU of a host or independently of the CPU, a processing element corresponding to a core of the coprocessor executes a kernel transferred from the host, and a server manages a memory request generated according to an execution of the kernel by the processing element. A memory controller connected to the resistance switching memory module moves data corresponding to the memory request between the resistance switching memory module and the processing element in accordance with the memory request transferred from the server. A network integrates the processing element, the server, and the memory controller.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: March 2, 2021
    Assignees: MemRay Corporation, Yonsei University, University—Industry Foundation (UIF)
    Inventor: Myoungsoo Jung
  • Patent number: 10937475
    Abstract: A TCAM (Ternary Content Addressable Memory) according to the embodiment includes repeaters in a delay path for controlling the timing in the replica circuit that defines the timing of matching. According to the above configuration, the TCAM which consumes low power and operates at high speed can be realized.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 2, 2021
    Assignee: RENESAS ELELCTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10923165
    Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
  • Patent number: 10922240
    Abstract: According to one embodiment, a memory system includes a cache configured to cache a part of a multi-level mapping table for logical-to-physical address translation, and a controller. The multi-level mapping table includes a plurality of hierarchical tables corresponding to a plurality of hierarchical levels. The table of each hierarchical level includes a plurality of address translation data portions. The controller sets a priority for each of the hierarchical level based on a degree of bias of reference for each of the hierarchical level, and preferentially caches each of the address translation data portions of a hierarchical level with a high priority into the cache, over each of the address translation data portions of a hierarchical level with low priority.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: February 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shohei Onishi, Yoshiki Saito, Yohei Hasegawa, Konosuke Watanabe
  • Patent number: 10923183
    Abstract: A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: February 16, 2021
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Neal Berger, Yuniarto Widjaja
  • Patent number: 10916278
    Abstract: A memory controller comprising: a delay circuit, configured to use a first delay value and a second delay value to respectively delay a sampling clock signal to generate a first and a second delayed sampling clock signal; a sampling circuit, configured to use a first edge of the first delayed sampling clock signal to sample a data signal to generate a first sampling value, and configured to use a second edge of the second delayed sampling clock signal to sample the data signal to generate a second sampling value; and a calibrating circuit, configured to generate a sampling delay value according to the first delay value based on the first sampling value and the second sampling value. The delay circuit uses the sampling delay value to generate an adjusted sampling clock signal and the sampling circuit sample the data signal by the adjusted sampling clock signal.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 9, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kuo-Wei Chi, Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou, Shih-Chang Chen, Fu-Chin Tsai, Shih-Han Lin, Min-Han Tsai
  • Patent number: 10910056
    Abstract: A semiconductor device includes a plural search memory cells, a plural match lines, a plural sub-ground lines, and a plural amplifiers. The search memory cells are disposed in a matrix form. The match lines are disposed in association with respective memory cell rows and used to determine whether search data matches data stored in the search memory cells. The sub-ground lines are disposed in association with respective memory cell rows. The amplifiers are disposed in association with respective memory cell rows to amplify the potentials of the match lines. The match lines and the sub-ground lines are respectively precharged to a first potential and a second potential before a data search. When the search data is mismatched, the match lines are electrically coupled to associated sub-ground lines through the search memory cells and set to an intermediate potential that is intermediate between the first potential and the second potential.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10897248
    Abstract: A MOS transistor is allowed to recover from BTI degradation even when an operation mode signal is inactive. A semiconductor device includes a drive circuit coupled to a controlled circuit via a delay element. The drive circuit includes first and second MOS transistors coupled in series to each other. The first MOS transistor is controlled to be in an OFF state when the operation mode signal is active. When the operation mode signal is inactive, the first MOS transistor is controlled to be in the OFF state at least temporarily while the second MOS transistor is controlled to be in the OFF.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 19, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshisato Yokoyama, Toshiaki Sano
  • Patent number: 10877838
    Abstract: A method of detecting error in a data plane of a packet forwarding element that includes a plurality of physical ternary content-addressable memories (TCAMs) is provided. The method configures a first set of physical TCAMs into a first logical TCAM. The method configures a second set of physical TCAMs into a second logical TCAM. The second logical TCAM includes the same number of physical TCAMs as the first logical TCAM. The method programs the first and second logical TCAMs to store a same set of data. The method requests a search for a particular content from the first and second logical TCAMs. The method generates an error signal when the first and second logical TCAMs do not produce a same search results.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: December 29, 2020
    Assignee: Barefoot Networks, Inc.
    Inventors: Jay E. S. Peterson, Patrick Bosshart, Michael G. Ferrara
  • Patent number: 10878920
    Abstract: The memory controller includes a command generator generating first read commands respectively corresponding to each of a plurality of read voltages having different levels and transferring the first read commands to a memory device so that first read operation is performed plural times on a plurality of memory cells for each of the read voltages, and an inverted cell counter determining inverted cells showing different bit values during the first read operation performed plural times for each read voltage on the basis of read result data received from the memory device.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Jiman Hong, Tae Hoon Kim
  • Patent number: 10872076
    Abstract: Nodes of a database service may receive a read request to perform a read of a record stored by the database service and a transaction request to perform a transaction to the record. First and second indications of time may be associated with the read and transaction, respectively. A potential read anomaly (e.g., fuzzy read, read skew, etc.) may be detected based, at least in part, on a determination that the first indication of time is within a threshold value of the second indication of time. In response to detecting the potential read anomaly, the read may be performed after the transaction specified by the transaction request, regardless of whether the first indication of time is indicative of an earlier point in time than the second indication of time.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: December 22, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Laurion Darrell Burchall, Pradeep Jnana Madhavarapu, Christopher Richard Newcombe, Anurag Windlass Gupta