Abstract: Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.

Abstract: A memory device is provided. The memory device includes several sense amplifiers and at least one reference cell. Each of the sense amplifiers has a first terminal and a second terminal. The first terminals of the sense amplifiers are coupled to a memory cell block, and the second terminals of the sense amplifiers are coupled together to transmit a read current. The at least one reference cell transmits the read current to a ground terminal. The at least one reference cell has a decreased resistance value when a number N of the sense amplifiers increases.

Abstract: A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

Abstract: Apparatuses and methods can be related to preventing the activation of rows using fuses in, for example, a memory device or a computing system that includes a memory device. The preventing the activation of rows adjacent to a predefined row address range can reduce the charge leakage from the memory cells comprising the predefined row address range. Reducing the charge leakage from memory cells comprising the predefined row address range can increase stability in data retention.

Abstract: According to one embodiment, a storage device includes first wirings extending in a first direction and second wirings extending in a second direction. A memory cells are connected between the first wirings and the second wirings and include a variable resistance memory element. A first drive circuit is provided for supplying voltages to the first wirings, and a second drive circuit is provided for supplying voltages to the second wirings. The first drive circuit applies a first voltage to a selected first wiring, the second drive circuit applies a second voltage to a selected second wiring. A voltage between the second voltage and one-half of the sum of the first and second voltages is applied to a non-selected first wiring, and a voltage between the first voltage and one-half of the sum of the first and second voltages is applied to a non-selected second wiring.

Abstract: A semiconductor device includes a memory bank including a first memory block, a second memory block, and a redundancy memory block, and a column line selection circuit configured, when a fail occurs in a first column line of the first memory block, to replace the first column line of the first memory block with a first redundancy line of the redundancy memory block, and replace a second column line of the second memory block with a second redundancy line of the redundancy memory block.

Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. An example apparatus includes an array of memory cells and processing circuitry. The processing circuitry is configured to receive, from a host, a query for particular data in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that corresponds more closely to the search key than other data stored in the portions of the array of memory cells, and transfer the data that corresponds more closely to the search key than the other data to the host.

Abstract: A ternary content addressable memory (TCAM) device comprising an input interface having a first input for receiving first data and a second input for receiving second data; and a memory configured to write the first data into an address selected row of the memory at the same time that a comparison is performed between the second data and at least one other row of the memory different from the address selected row. More particularly, the input interface may further have a third input for receiving a search enable signal and a fourth input for receiving a write enable signal, wherein the memory is configured to write the first data and perform the comparison in response to assertion of the search enable signal at the same time as assertion of the write enable signal. An associated method is also provided.

Abstract: The present disclosure provides a method for automatically collecting and matching laboratory data, including: obtaining a creation time of experimental data, determining target experimental data corresponding to a target time in accordance with the creation time, segmenting the target experimental data into a plurality data blocks, generating a data block index table, including at least one data block identifier, according to the data blocks, selecting a target matching mode from a plurality of predetermined matching modes according to the data block index table, obtaining the data block identifier upon determining the target experimental data in a storage node is loaded, and extracting data content in the target experimental data corresponding to the data block identifier by the target matching mode. This method may greatly reduce the number of string matching and may reduce the complexity of the algorithm.

Abstract: A method of determining at least one property of a liquid system using a modeling system, the liquid system including at least one molecule in a solvent, the modeling system including a processor, comprises generating a quantum model of the liquid system using the processor of the modeling system, the quantum model including a device region and a lead region, the device region being spherical, paraboloid, cubic or arbitrary in shape and encompassing the at least one molecule and a portion of the solvent of the liquid system, the lead region encompassing a region of the solvent surrounding the device region, determining a first property of the device region by solving a first quantum equation for the device region using the processor of the system, determining the first property of the lead region by solving the first quantum equation under open boundary conditions for the lead region using the processor of the system, and combining the first property of the device region with the first property of the lead re

Abstract: A method of operating a memory device is provide. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compare with a clock cycle period to determine that the power nap period is less that the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

Abstract: A computer implemented method of storing a data object in a computer memory, wherein the data object is stored at a location in an object store as a portion of the memory, the location being determined by a hashing process based on a generated hash key, the memory further storing: a set of binary words in which each bit of each word identifies an occupancy state of a location in the object store such that an occupancy state of all locations is stored in the set of binary words; and a truncated hash key set storing, for each occupied location in the object store, a truncated hash key for a data object stored at the location, wherein the hashing process uses linear probing in which an occupancy of the location in the object store for storage of the data object is determined, wherein the occupancy is determined by reference to the set of binary words, and the linear probing further determines identity of the data object and an object stored in an occupied location, the identity being determined based on a compar

Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.

Abstract: The invention introduces a non-transitory computer program product for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

Abstract: The present disclosure provides a data reading circuit and a storage unit. The data reading circuit includes a being read unit connected to a voltage stabilizing unit and configured to store data. The voltage stabilizing unit is configured to stabilize and output a current from the being read unit to a first amplifying unit. The first amplifying unit is configured to amplify and output the current from the being read unit to a comparing unit. A reference unit is connected to a second amplifying unit, to output a reference current to the second amplifying unit. The second amplifying unit is configured to amplify and output the reference current to the comparing unit. The comparing unit is configured to compare a comparing point voltage, that is based on the amplified current of the being read unit and the amplified reference current, with a reference voltage and to output comparison results.

Abstract: Systems and methods for performing a pattern matching operation in a memory device are disclosed. The memory device may include a controller and memory arrays where the memory arrays store different patterns along bit lines. An input pattern is applied to the memory array(s) to determine whether the pattern is stored in the memory device. Word lines may be activated in series or in parallel to search for patterns within the memory array. The memory array may include memory cells that store binary digits, discrete values or analog values.

Abstract: A plurality of memory cells, in which each memory cell includes two corresponding supply terminal inputs, is powered up while applying a voltage differential between the corresponding supply terminal inputs for each of the plurality of memory cells. After powering up, the plurality of memory cells is read and a physically unclonable function (PUF) response is generated from data of the reading.

Abstract: The present application discloses an apparatus for testing defects of a memory module comprises a central buffer for generating a test write command and a test read command to indicate testing to a target address in a memory module; and a data buffer coupled to the central buffer to receive the test write command and the test read command; the data buffer is configured to, in response to the test write command, use target data as repair data corresponding to the target address, and write the target data into the memory module; and, in response to the test read command, to read target data from the target address and compare the target data with the repair data, and to send to the central buffer a comparison result of the target data and the repair data; the central buffer is further configured to record the target address as a tested address when generating the test write command, and determine whether to add the tested address to defective address information based on the comparison result associated with th

Abstract: A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

Abstract: Modern integrated circuits have an increasing need for various levels of both supply voltage (V) and operating frequency (f) available at fine spatial and temporal granularity. This work introduces a solution that provides a number and quality of locally distributed V/f domains through FOPAC. Opportunistically sharing design resources and features between multi-phase voltage regulators (MPVRs) and resonant rotary clocks (ReRoCs) enabling i) the scalability to hundreds of domains, ii) fast switching times for both voltage and frequency, leading to temporal flexibility, and iii) locally distributed designs, leading to spatial flexibility.

Abstract: A content-addressable memory (CAM) storage element includes bit storage cell bit comparison cells. The bit storage cell is arranged on a first die tier and includes at least one transistor, one or two bit lines, and a storage node. The bit comparison cell is arranged on a second die tier and has a match line, complementary search lines, and at least three transistors. The complementary search lines are decoupled from the bit line(s). A 3D connection couples the storage node to one of the transistors of the second die tier. The CAM cell performs at least one CAM search per clock cycle using at least four transistors per search, including the at least one transistor of the bit storage cell and the at least three transistors of the bit comparison cell, and to output results of the at least one CAM search on the match line.

Abstract: A semiconductor apparatus includes a first receiver, a second receiver, a first delay line, and a second delay line. The first receiver receives an input signal using a first supply voltage. The first delay line delays an output of the first receiver based on a first delay control signal and a first complementary delay control signal to generate a received signal. The second receiver receives a clock signal using a second supply voltage. The second delay line delays an output of the second receiver based on a second delay control signal and a second complementary delay control signal to generate a received clock signal. Delay amounts of the first and second delay lines are complementarily changed based on the first and second supply voltages.

Abstract: A system to send a first command to a first memory die of a plurality of memory dies of a memory sub-system the first command to execute an initialization process. The system reads a first bit value from the first memory die, the first bit value indicating the first memory die is executing a peak current phase of the initialization process. The system reads a second bit value from the first memory die, the second bit value indicating the first memory die is executing a safe phase of the initialization process. In response to reading the second bit value, a second command is sent to a second memory die to execute the initialization process.

Abstract: Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.

Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.

Abstract: A semiconductor device includes a memory cell array, a first pre-charge circuit, and a data line switching control circuit. The memory cell array includes a first data line, a second data line, and a third data line. The first pre-charge circuit is configured to pre-charge the first data line according to a first voltage level of a first equalizing signal. The data line switching control circuit is configured to disconnect the second data line from the third data line according to a second voltage level of a data line switching control signal in a standby operation of the semiconductor device, to perform charge sharing of the first equalizing signal and the data line switching control signal for a first time in an active operation of the semiconductor device, and to drive the data line switching control signal to the first voltage level.

Abstract: Some embodiments are directed to a cryptographic device, including a non-volatile memory, a range of the memory storing data, a selector arranged to receive a selector signal configuring a memory read-out unit for a regular read-out mode or for a PUF read-out mode of the same memory, a control unit arranged to send the selector signal to the selector configuring the memory read-out unit in the regular read-out mode, and reading the memory range to obtain the data, and send the selector signal to the selector configuring the memory read-out unit for PUF read-out mode and obtaining a noisy bit string from the memory range.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for determining extremum numerical values. Numerical values may be stored in files of a stack, with each bit of the numerical value stored in a content addressable memory (CAM) cell of the file. Each file may be associated with an accumulator circuit, which provides an accumulator signal. An extremum search operation may be performed where a sequence of comparison bits are compared in a bit-by-bit fashion to each bit of the numerical values. The accumulator circuits each provide an accumulator signal which indicates if the numerical value in the associated file is an extremum value or not. Examples of extremum search operations include finding a maximum of the numerical values and a minimum of the numerical values.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: The memory device includes a content addressable memory (CAM) block including a plurality of pages, peripheral circuits configured to perform a CAM data read operation to read a CAM data comprising a plurality of check data each indicating whether bad block information is included in a region of the CAM data from a page sequentially selected among the plurality of pages, a CAM data read controller configured to perform a CAM data load operation to receive the CAM data from the peripheral circuits and output the CAM data to an external memory controller, and stop the CAM data load operation based on at least one check data among the plurality of check data included in the CAM data.

Abstract: A memory controller controlling a memory device including a plurality of memory cells includes a read operation controller performing a soft read operation on the plurality of memory cells by using a plurality of soft read voltages determined based on a default read voltage when a read operation for reading the plurality of memory cells by the default read voltage fails, and reading the plurality of memory cells by using an optimal read voltage determined according to a result of performing the soft read operation, and a read voltage setting circuit determining the optimal read voltage using voltage candidates being soft read voltages corresponding to at least two voltage intervals, among a plurality of voltage intervals determined according to the plurality of soft read voltages, the voltage candidates selected in ascending order of a number of memory cells having threshold voltages belonging to each of the plurality of voltage intervals.

Abstract: A multi-column index is generated based on an interleaving of data bits for selectivity for efficient processing of data in a relational database system. Two or more columns may be identified for inclusion in the multi-column index for a relational database table. Based, at least in part, on the interleaving of data bits for selectivity from the identified columns, a multi-column index is generated for the relational database table that provides a respective index value for each entry in the relational database table. The entries of the relational database table may then be stored according to the index values of the multi-column index.

Abstract: A semiconductor memory device includes a plurality of memory cells connected a pair of bit lines, a column selection circuit, and a sense amplifier. When the semiconductor memory device is in a data writing operation, the column selection circuit electrically connects a pair of data input and output lines to the pair of bit lines during a first time interval and a second time interval, consecutively arranged, and the sense amplifier electrically disconnects from the pair of bit lines during the first time interval, and senses and amplifies a voltage difference between the pair of bit lines during the second time interval.

Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

Abstract: A search circuit includes a content-addressable memory (CAM) including a plurality of CAM cells configured to store a plurality of entry data, each entry data including a first bit corresponding to a least significant bit through a K-th bit corresponding to a most significant bit, the CAM configured to provide a plurality of matching signals indicating whether each of the plurality of entry data matches searching data, and a CAM controller configured to perform a partial searching operation such that the CAM controller applies comparison bits corresponding to a portion of the first through K-th bits as the searching data to the CAM and searches for target entry data among the plurality of entry data based on the plurality of matching signals indicating that the corresponding bits of the target entry data match the comparison bits.

Abstract: A method of operating a memory system, which includes a memory controller and at least one non-volatile memory, includes storing, in the memory system, temperature-dependent performance level information received from a host disposed external to the memory system, setting an operation performance level of the memory system to a first performance level, operating the memory controller and the at least one non-volatile memory device according to the first performance level, detecting an internal temperature of the memory system, and changing the operation performance level of the memory system to a second performance level that is different from the first performance level. The operation performance level is changed by the memory controller of the memory system, and changing the operation performance level is based on the temperature-dependent performance level information and the detected internal temperature.

Abstract: Exemplary methods, apparatuses, and systems include a first die in a power network receiving, from each of a plurality of dice in the power network, a first activity state value indicating that the respective die is in a high current state, a second activity state value indicating that the respective die is a moderate current state, or a third activity state value indicating that the respective die is a low current state. The received activity state values include at least one second or third activity state value. The first die determines, using the received activity state values, a first sum of the activity state values. The first die further selects an activity state based upon the first sum and sends, to the plurality of dice, an activity state value corresponding to the selected activity state.

Abstract: A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry. The responder signal circuitry performs a calculation on a row of the memory array and generates a responder signal indicating that there is at least one cell in the row having a predefined value.

Abstract: The progress of an erase operation for a memory device is monitored using an erase credit mechanism. In one approach, an erase operation is performed to erase a memory. Erase pulse slices used in the erase operation are monitored. Erase credits associated with the erase operation are determined. The erase credits include an erase credit associated with each of the erase pulse slices. Based on the erase credits, an extent of erasure of the memory is determined. In response to determining that the extent of erasure has reached a predetermined threshold, the erase operation is terminated.

Abstract: A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.

Abstract: A Memory device comprising a matrix of memory cells, the matrix being provided with at least one first column, the device also being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical ‘1’, is greater than a predetermined threshold.

Abstract: Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Abstract: A CAM/TCAM includes a plurality of rows of CAM/TCAM lines, a plurality of search lines, and a plurality of bit lines, wherein each row comprises an array of CAM/TCAM cells. Each TCAM cell has two storage cells, representing state for data and a mask of the cell, and match logic. The two storage cells connect to a respective bit line as input and their output drives the match logic. In response to the respective search line and storage outputs, the match logic generates cell match outputs. The match logic can be implemented using static logic comprising tristate gates and masking logic that forces the cell match output to a predetermined value in response to the stored mask value. The match outputs in the row are AND-ed by a logic tree to generate a match output, thereby reducing power consumption.

Abstract: A memory management method includes identifying memory segments of a memory device. The method also includes identifying, for each memory segment, a number of faulty columns and determining a total number of faulty columns for the memory device. The method also includes, in response to a determination that the total number of faulty columns is greater than a threshold, identifying a memory segment having a highest number of faulty columns. The method also includes disabling the memory segment. Another method includes identifying, for each memory segment, a number of faulty memory blocks and determining a total number of faulty memory blocks. The method also includes, in response to a determination that the total number of faulty memory blocks is greater than a threshold, identifying a memory segment having a highest number of faulty memory blocks. The method also includes disabling the memory segment.

Abstract: A memory controller is described. The memory controller includes a register to collectively track row active commands sent to multiple memory chip banks of a memory rank.

Abstract: A semiconductor device capable of detecting whether test operation is normal is provided. The semiconductor device includes a plurality of memory cells arranged in a matrix, a plurality of word lines provided corresponding to each of the rows of the plurality of memory cells respectively, a decoder for generating driving signals for driving the plurality of word lines, and a detection circuit provided between the plurality of word lines and the decoder for simultaneously raising the plurality of word lines by test operation and detecting whether or not the rising state of the plurality of word lines is normal.

Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.

Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.

Abstract: A TCAM (Ternary Content Addressable Memory) according to the embodiment includes repeaters in a delay path for controlling the timing in the replica circuit that defines the timing of matching. According to the above configuration, the TCAM which consumes low power and operates at high speed can be realized.

Abstract: In a coprocessor performing data processing by supplementing functions of a CPU of a host or independently of the CPU, a processing element corresponding to a core of the coprocessor executes a kernel transferred from the host, and a server manages a memory request generated according to an execution of the kernel by the processing element. A memory controller connected to the resistance switching memory module moves data corresponding to the memory request between the resistance switching memory module and the processing element in accordance with the memory request transferred from the server. A network integrates the processing element, the server, and the memory controller.