Including Signal Comparison Patents (Class 365/189.07)
  • Patent number: 11114139
    Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
  • Patent number: 11107531
    Abstract: A search circuit includes a content-addressable memory (CAM) including a plurality of CAM cells configured to store a plurality of entry data, each entry data including a first bit corresponding to a least significant bit through a K-th bit corresponding to a most significant bit, the CAM configured to provide a plurality of matching signals indicating whether each of the plurality of entry data matches searching data, and a CAM controller configured to perform a partial searching operation such that the CAM controller applies comparison bits corresponding to a portion of the first through K-th bits as the searching data to the CAM and searches for target entry data among the plurality of entry data based on the plurality of matching signals indicating that the corresponding bits of the target entry data match the comparison bits.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 31, 2021
    Inventor: Hyungjin Kim
  • Patent number: 11093166
    Abstract: A method of operating a memory system, which includes a memory controller and at least one non-volatile memory, includes storing, in the memory system, temperature-dependent performance level information received from a host disposed external to the memory system, setting an operation performance level of the memory system to a first performance level, operating the memory controller and the at least one non-volatile memory device according to the first performance level, detecting an internal temperature of the memory system, and changing the operation performance level of the memory system to a second performance level that is different from the first performance level. The operation performance level is changed by the memory controller of the memory system, and changing the operation performance level is based on the temperature-dependent performance level information and the detected internal temperature.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Seok Kim, Dae-Ho Kim, Yong-Geun Oh, Sung-Jin Moon
  • Patent number: 11079829
    Abstract: Exemplary methods, apparatuses, and systems include a first die in a power network receiving, from each of a plurality of dice in the power network, a first activity state value indicating that the respective die is in a high current state, a second activity state value indicating that the respective die is a moderate current state, or a third activity state value indicating that the respective die is a low current state. The received activity state values include at least one second or third activity state value. The first die determines, using the received activity state values, a first sum of the activity state values. The first die further selects an activity state based upon the first sum and sends, to the plurality of dice, an activity state value corresponding to the selected activity state.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 3, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jonathan S. Parry, David A. Palmer
  • Patent number: 11074973
    Abstract: A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry. The responder signal circuitry performs a calculation on a row of the memory array and generates a responder signal indicating that there is at least one cell in the row having a predefined value.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: July 27, 2021
    Assignee: GSI Technology Inc.
    Inventors: Avidan Akerib, Eli Ehrman
  • Patent number: 11062772
    Abstract: A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 13, 2021
    Assignee: PANASONIC CORPORATION
    Inventors: Reiji Mochida, Kazuyuki Kouno, Takashi Ono, Masayoshi Nakayama, Yuriko Hayata
  • Patent number: 11061578
    Abstract: The progress of an erase operation for a memory device is monitored using an erase credit mechanism. In one approach, an erase operation is performed to erase a memory. Erase pulse slices used in the erase operation are monitored. Erase credits associated with the erase operation are determined. The erase credits include an erase credit associated with each of the erase pulse slices. Based on the erase credits, an extent of erasure of the memory is determined. In response to determining that the extent of erasure has reached a predetermined threshold, the erase operation is terminated.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Cariello, Fulvio Rori, Jung Sheng Hoei
  • Patent number: 11043248
    Abstract: A Memory device comprising a matrix of memory cells, the matrix being provided with at least one first column, the device also being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical ‘1’, is greater than a predetermined threshold.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 22, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Philippe Noel, Reda Boumchedda, Bastien Giraud, Emilien Bourde-Cice
  • Patent number: 11023336
    Abstract: Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: June 1, 2021
    Assignee: NeuroBlade, Ltd.
    Inventors: Elad Sity, Eliad Hillel
  • Patent number: 11017858
    Abstract: A CAM/TCAM includes a plurality of rows of CAM/TCAM lines, a plurality of search lines, and a plurality of bit lines, wherein each row comprises an array of CAM/TCAM cells. Each TCAM cell has two storage cells, representing state for data and a mask of the cell, and match logic. The two storage cells connect to a respective bit line as input and their output drives the match logic. In response to the respective search line and storage outputs, the match logic generates cell match outputs. The match logic can be implemented using static logic comprising tristate gates and masking logic that forces the cell match output to a predetermined value in response to the stored mask value. The match outputs in the row are AND-ed by a logic tree to generate a match output, thereby reducing power consumption.
    Type: Grant
    Filed: December 25, 2016
    Date of Patent: May 25, 2021
    Inventor: Sudarshan Kumar
  • Patent number: 10984883
    Abstract: A memory management method includes identifying memory segments of a memory device. The method also includes identifying, for each memory segment, a number of faulty columns and determining a total number of faulty columns for the memory device. The method also includes, in response to a determination that the total number of faulty columns is greater than a threshold, identifying a memory segment having a highest number of faulty columns. The method also includes disabling the memory segment. Another method includes identifying, for each memory segment, a number of faulty memory blocks and determining a total number of faulty memory blocks. The method also includes, in response to a determination that the total number of faulty memory blocks is greater than a threshold, identifying a memory segment having a highest number of faulty memory blocks. The method also includes disabling the memory segment.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Sowjanya Tungala, Sini Balakrishnan, Sowjanya Sunkavelli, Sridhar Yadala, Dat Tran, Loc Tu, Kirubakaran Periyannan
  • Patent number: 10969997
    Abstract: A memory controller is described. The memory controller includes a register to collectively track row active commands sent to multiple memory chip banks of a memory rank.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventor: William Nale
  • Patent number: 10964404
    Abstract: A semiconductor device capable of detecting whether test operation is normal is provided. The semiconductor device includes a plurality of memory cells arranged in a matrix, a plurality of word lines provided corresponding to each of the rows of the plurality of memory cells respectively, a decoder for generating driving signals for driving the plurality of word lines, and a detection circuit provided between the plurality of word lines and the decoder for simultaneously raising the plurality of word lines by test operation and detecting whether or not the rising state of the plurality of word lines is normal.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 30, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshisato Yokoyama, Shinji Tanaka
  • Patent number: 10950312
    Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
  • Patent number: 10942873
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
  • Patent number: 10937495
    Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: March 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: He-Hsuan Chao, Ping-Kun Wang, Seow Fong Lim, Norio Hattori, Chien-Min Wu, Chih-Hua Hung
  • Patent number: 10937475
    Abstract: A TCAM (Ternary Content Addressable Memory) according to the embodiment includes repeaters in a delay path for controlling the timing in the replica circuit that defines the timing of matching. According to the above configuration, the TCAM which consumes low power and operates at high speed can be realized.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 2, 2021
    Assignee: RENESAS ELELCTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10936198
    Abstract: In a coprocessor performing data processing by supplementing functions of a CPU of a host or independently of the CPU, a processing element corresponding to a core of the coprocessor executes a kernel transferred from the host, and a server manages a memory request generated according to an execution of the kernel by the processing element. A memory controller connected to the resistance switching memory module moves data corresponding to the memory request between the resistance switching memory module and the processing element in accordance with the memory request transferred from the server. A network integrates the processing element, the server, and the memory controller.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: March 2, 2021
    Assignees: MemRay Corporation, Yonsei University, University—Industry Foundation (UIF)
    Inventor: Myoungsoo Jung
  • Patent number: 10923183
    Abstract: A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: February 16, 2021
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Neal Berger, Yuniarto Widjaja
  • Patent number: 10923165
    Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
  • Patent number: 10922240
    Abstract: According to one embodiment, a memory system includes a cache configured to cache a part of a multi-level mapping table for logical-to-physical address translation, and a controller. The multi-level mapping table includes a plurality of hierarchical tables corresponding to a plurality of hierarchical levels. The table of each hierarchical level includes a plurality of address translation data portions. The controller sets a priority for each of the hierarchical level based on a degree of bias of reference for each of the hierarchical level, and preferentially caches each of the address translation data portions of a hierarchical level with a high priority into the cache, over each of the address translation data portions of a hierarchical level with low priority.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: February 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shohei Onishi, Yoshiki Saito, Yohei Hasegawa, Konosuke Watanabe
  • Patent number: 10916278
    Abstract: A memory controller comprising: a delay circuit, configured to use a first delay value and a second delay value to respectively delay a sampling clock signal to generate a first and a second delayed sampling clock signal; a sampling circuit, configured to use a first edge of the first delayed sampling clock signal to sample a data signal to generate a first sampling value, and configured to use a second edge of the second delayed sampling clock signal to sample the data signal to generate a second sampling value; and a calibrating circuit, configured to generate a sampling delay value according to the first delay value based on the first sampling value and the second sampling value. The delay circuit uses the sampling delay value to generate an adjusted sampling clock signal and the sampling circuit sample the data signal by the adjusted sampling clock signal.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 9, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kuo-Wei Chi, Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou, Shih-Chang Chen, Fu-Chin Tsai, Shih-Han Lin, Min-Han Tsai
  • Patent number: 10910056
    Abstract: A semiconductor device includes a plural search memory cells, a plural match lines, a plural sub-ground lines, and a plural amplifiers. The search memory cells are disposed in a matrix form. The match lines are disposed in association with respective memory cell rows and used to determine whether search data matches data stored in the search memory cells. The sub-ground lines are disposed in association with respective memory cell rows. The amplifiers are disposed in association with respective memory cell rows to amplify the potentials of the match lines. The match lines and the sub-ground lines are respectively precharged to a first potential and a second potential before a data search. When the search data is mismatched, the match lines are electrically coupled to associated sub-ground lines through the search memory cells and set to an intermediate potential that is intermediate between the first potential and the second potential.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10897248
    Abstract: A MOS transistor is allowed to recover from BTI degradation even when an operation mode signal is inactive. A semiconductor device includes a drive circuit coupled to a controlled circuit via a delay element. The drive circuit includes first and second MOS transistors coupled in series to each other. The first MOS transistor is controlled to be in an OFF state when the operation mode signal is active. When the operation mode signal is inactive, the first MOS transistor is controlled to be in the OFF state at least temporarily while the second MOS transistor is controlled to be in the OFF.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 19, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshisato Yokoyama, Toshiaki Sano
  • Patent number: 10877838
    Abstract: A method of detecting error in a data plane of a packet forwarding element that includes a plurality of physical ternary content-addressable memories (TCAMs) is provided. The method configures a first set of physical TCAMs into a first logical TCAM. The method configures a second set of physical TCAMs into a second logical TCAM. The second logical TCAM includes the same number of physical TCAMs as the first logical TCAM. The method programs the first and second logical TCAMs to store a same set of data. The method requests a search for a particular content from the first and second logical TCAMs. The method generates an error signal when the first and second logical TCAMs do not produce a same search results.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: December 29, 2020
    Assignee: Barefoot Networks, Inc.
    Inventors: Jay E. S. Peterson, Patrick Bosshart, Michael G. Ferrara
  • Patent number: 10878920
    Abstract: The memory controller includes a command generator generating first read commands respectively corresponding to each of a plurality of read voltages having different levels and transferring the first read commands to a memory device so that first read operation is performed plural times on a plurality of memory cells for each of the read voltages, and an inverted cell counter determining inverted cells showing different bit values during the first read operation performed plural times for each read voltage on the basis of read result data received from the memory device.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Jiman Hong, Tae Hoon Kim
  • Patent number: 10872076
    Abstract: Nodes of a database service may receive a read request to perform a read of a record stored by the database service and a transaction request to perform a transaction to the record. First and second indications of time may be associated with the read and transaction, respectively. A potential read anomaly (e.g., fuzzy read, read skew, etc.) may be detected based, at least in part, on a determination that the first indication of time is within a threshold value of the second indication of time. In response to detecting the potential read anomaly, the read may be performed after the transaction specified by the transaction request, regardless of whether the first indication of time is indicative of an earlier point in time than the second indication of time.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: December 22, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Laurion Darrell Burchall, Pradeep Jnana Madhavarapu, Christopher Richard Newcombe, Anurag Windlass Gupta
  • Patent number: 10872657
    Abstract: An integrated circuit may include an amplifier circuit configured to receive a pull-up voltage in response to a pull-up enable signal, receive a pull-down voltage in response to a pull-down enable signal, and amplify a voltage difference between a first line and a second line through the pull-up and pull-down voltages; a first delay path configured to generate the pull-up enable signal by delaying an input signal; and a second delay path configured to generate the pull-down enable signal by delaying the input signal, wherein a change in a delay of the first delay path due to variation of a power supply voltage is smaller than a change in a delay of the second delay path due to the variation.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: December 22, 2020
    Assignee: SK hynix Inc.
    Inventor: Jeong-Jik Na
  • Patent number: 10867646
    Abstract: A circuit includes a voltage node, a plurality of memory cells, a bit line coupled with the plurality of memory cells, and a switching circuit coupled between the voltage node and the bit line. The switching circuit is configured to couple the voltage node with the bit line responsive to a voltage level on the bit line.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chi Wu, Chiting Cheng, Jonathan Tsung-Yung Chang, Yangsyu Lin, Mahmut Sinangil
  • Patent number: 10868494
    Abstract: A device includes a sensor and an oscillator. The sensor provides a temperature-sensitive voltage. The oscillator includes a digital delay cell and an adjustment device. The adjustment device, based on the temperature-sensitive voltage, adjusts a delay of the digital delay cell, wherein the digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ping-Han Tsai, Chih-Sheng Hou, Po-Yu Chen, Nan-Hsin Tseng
  • Patent number: 10859627
    Abstract: A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Sreejit Chakravarty, Oscar Mendoza, Ramasubramanian Rajamani, Bryan J. Gran, Sorin Iacobovici, Neel Shah, Michael Neve de Mevergnies, John Cruz Mejia, Amy L. Santoni
  • Patent number: 10854287
    Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hernan A. Castro
  • Patent number: 10789182
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • Patent number: 10790266
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: September 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Mikihiko Ito, Masaru Koyanagi, Masafumi Nakatani, Masahiro Yoshihara, Shinya Okuno, Shigeki Nagasaka
  • Patent number: 10770152
    Abstract: Methods of operating a memory device include comparing input data to data stored in strings of series-connected memory cells coupled to a data line, generating a respective resistance in series with each string of series-connected memory cells while comparing the plurality of digits of input data to the stored data, comparing a representation of a level of current in the data line to a reference, deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than the reference, and deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
  • Patent number: 10748642
    Abstract: A method of setting a read voltage by a memory controller and a storage device are provided. The method includes controlling a memory device to read data from memory cells by applying a test read voltage to a selected word line; receiving, from the memory device, cell count information corresponding to a read operation of the memory device, and renewing the test read voltage by using the cell count information and a cost function to find an optimum read voltage, the cost function being determined for each read voltage level; and determining a read voltage by performing the controlling of the memory device and the renewing of the test read voltage at least once.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-hoon Kim, Jun-jin Kong, Hong-rak Son, Pil-sang Yoon
  • Patent number: 10741242
    Abstract: Memory devices are provided. A memory device includes a voltage generation circuit that includes an offset compensator configured to receive a reference voltage and an offset code and to link the offset code to the reference voltage. The voltage generation circuit includes a comparator configured to compare the reference voltage linked to the offset code with a bit line pre-charge voltage and to output driving control signals. The voltage generation circuit includes a driver configured to output the bit line pre-charge voltage at a target level of the reference voltage in response to the driving control signals. The voltage generation circuit includes a background calibration circuit configured to generate the offset code for performing control so that a target short current flows through an output node of the driver from which the bit line pre-charge voltage is output. Related methods of generating a bit line pre-charge voltage are also provided.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-hun Seo, Seung-hyun Cho, Chang-ho Shin, Yong-jae Lee
  • Patent number: 10734983
    Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 4, 2020
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Rakesh L. Notani, Kai Lun Hsiung, Yanzhe Liu
  • Patent number: 10734063
    Abstract: A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Koji Nii
  • Patent number: 10726907
    Abstract: An electronic device includes: a memory cell configured to store electric charge for representing a data value, wherein the memory cell is configured to store two or more levels of the electric charge corresponding to different data values; a preamplifier operably coupled to the memory cell, the preamplifier having a common source and configured to generate an amplified signal based on amplifying a difference in the two or more levels of the stored electric charge; and a sense amplifier operably coupled to the preamplifier, the sense amplifier configured to further process the amplified signal for determining the data value stored in the memory cell.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 10679692
    Abstract: A memory apparatus and a majority detector thereof are provided. The majority detector includes a pull-up circuit, a first switch, a second switch, a plurality of first transistors, a plurality of second transistors and a sense amplifying circuit. The pull-up circuit provides a first voltage to a first node and a second node according to a control signal before a sensing period. The first switch and the second switch provide a second voltage to the first node and the second node respectively according to the control signal during the sensing period. Control ends of the first transistors each receives one of a plurality of values of a data signal. Control ends of the second transistors each receives an inverse value of the one of the values of the data signal. The sense amplifying circuit generates a sensing result according to a voltage difference between the first node and the second node during the sensing period, and the sensing result indicates a majority value among the values.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 9, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Yuji Nakaoka
  • Patent number: 10672498
    Abstract: A repair device and a semiconductor device including the same are disclosed, which relate to a technology for a Post Package Repair (PPR) device. The repair device includes: a clock generator configured to generate a fuse clock signal based to corresponding to an available fuse; a fuse selection circuit configured to discriminate between a first clock signal and a second clock signal in the fuse clock signal; a fuse signal generator configured to output a first repair signal corresponding to the first clock signal and a second repair signal corresponding to the second clock signal during a post package repair (PPR) mode; and an output circuit configured to output a first output signal by detecting address information of the remaining unused fuses in response to the first repair signal, or configured to output a second output signal by detecting address information of the remaining unused fuses.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventor: Jong Sam Kim
  • Patent number: 10672469
    Abstract: A device comprises a first block of memory cells, a second block of memory cells to store a feature array, and a third block of memory cells to store an array of output values. Sensing circuitry is coupled to the first block of memory cells and the second block of memory cells to compare electrical differences between the memory cells in the first block and the memory cells in the second block to generate the array of output values. Writing circuitry is operatively coupled to the third block to store the array of output values in the third block of memory cells.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 2, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hsiang-Lan Lung
  • Patent number: 10664407
    Abstract: A set of data entries is transferred via a memory mapped interface from an external peripheral device to a processor device and is stored in a shared memory region. Based on a first pointer to the shared memory region, a first process executed by the processor device processes a first group of the data entries. Based on a second pointer to the shared memory region, a second process executed by the processor device processes a second group of the data entries. The second process indicates the second pointer to the first process. The first process indicates a lower one of the first pointer and the second pointer to the peripheral device.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Anant Raj Gupta, Ingo Volkening, Jun Ye Zhou
  • Patent number: 10665314
    Abstract: Methods and apparatuses are provided for self-trimming of a semiconductor device. An example self-trimming circuit includes a control circuit configured to, during a self-trimming operation, decode a test command signal to set a target voltage and set a voltage trim code to an initial value, and to adjust a value of the voltage trim code based on a stop signal. The example self-trimming circuit further includes a reference voltage regulator configured to receive the voltage trim code and to convert a band-gap reference voltage to an output voltage based on the voltage trim code, and a comparator configured to compare the target voltage with the output voltage and to provide the stop signal having a value based on the comparison.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Miguel Jimenez-Olivares, Maksim Kuzmenka
  • Patent number: 10658014
    Abstract: A memory device includes memory cell blocks, bit line sense amplifier blocks, and a control circuit connected to one or more of the bit line sense amplifier blocks arranged between the memory cell blocks. The control circuit controls levels of currents respectively supplied to a first sensing driving voltage line and a second sensing driving voltage line driving bit line sense-amplifiers, to be constant. A first sensing driving control signal and/or a second sensing driving control signal, output from the sensing-matching control circuit is provided to the bit line sense amplifiers in all of the bit line sense amplifier blocks, so that the bit line sense amplifiers are constantly driven based on the constant levels of currents supplied to the first sensing driving voltage line and the second sensing driving voltage line.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 19, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-su Lee, Jong-cheol Kim
  • Patent number: 10643717
    Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan S. Parry, George B. Raad, James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10643673
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 10622034
    Abstract: The present disclosure includes apparatuses and methods related to performing a greater vector determination in memory. An example apparatus comprises a first group of memory cells coupled to a sense line and to a number of first access lines and a second group of memory cells coupled to the sense line and to a number of second access lines. The example apparatus comprises a controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Tiwari
  • Patent number: 10600494
    Abstract: Methods and apparatuses are provided for self-trimming of a semiconductor device. An example apparatus includes a semiconductor device including a self-trimming circuit configured to receive a reference voltage and a test command signal. The self-trimming circuit is configured to convert the reference voltage to a target voltage based on the test command signal and further configured to adjust a voltage trim code until an internal voltage matches the target voltage to determine a trim level associated with the internal voltage.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Miguel Jimenez-Olivares, Maksim Kuzmenka