Abstract: Apparatuses and methods for providing power for memory refresh operations are described. An example apparatus includes refresh circuits, a power amplifier, a power circuit, and a power control circuits. The refresh circuits are configured to refresh memory cells of a memory bank. The power amplifier is configured to provide power when activated to the refresh circuits. The power provided by the power amplifier has a first voltage. The power circuit is configured to receive a power supply voltage and to provide power when activated to the refresh circuits. The power provided by the power amplifier has a second voltage. The power control circuit is configured to compare the first voltage and the target voltage and to provide an activation signal to control activation of the power circuit having an active duration based at least in part on the comparison.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. For example, a switching component connected to a digit line may also be connected to an offset capacitor selected to compensate for a threshold voltage offset. The offset capacitor may be discharged in conjunction with a read operation, resulting in a threshold voltage applied to the switching component. This may enable all or substantially all of the stored charge of the ferroelectric memory cell to be extracted and transferred to a sense capacitor through the transistor. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.

Abstract: A method for generating a pattern matching machine for identifying matches of a plurality of symbol patterns in a sequence of input symbols, the method comprising: providing a state machine of states and directed transitions between states corresponding to the plurality of patterns; applying an Aho-Corasick approach to identify mappings between states in the event of a failure, of the state machine in a state and for an input symbol, to transition to a subsequent state based on the directed transitions of the state machine, characterized in that one of the symbol patterns includes a wildcard symbol, and mappings for one or more states representing pattern symbols including the wildcard symbol are based on an input symbol to be received, by the pattern matching machine in use, to constitute the wildcard.

Abstract: A semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to output data from the memory cell coupled to each of the bit lines through a global input/output line; a flag-generating circuit configured to generate a flag signal received with respect to the bit lines. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal based on number of data having a specific logic level among the data in the memory cell for each of the bit lines that may be provided through the global input/output line in a read operation; and an output circuit configured to output the data based on at least one of the duplicate data flag signal and the data bus is inversion flag signal.

Abstract: A sensing circuit includes a sensing stage. The sensing stage includes a voltage clamp, a P-type transistor and an N-type transistor. The voltage clamp receives a first power supply voltage and generates a second power supply voltage. The source terminal of the P-type transistor receives the second power supply voltage. The gate terminal of the P-type transistor receives a cell current from a selected circuit of a non-volatile memory. The drain terminal of the N-type transistor is connected with the drain terminal of the P-type transistor. The gate terminal of the N-type transistor receives a bias voltage. The source terminal of the N-type transistor receives a ground voltage. In a sensing period, the second power supply voltage from the voltage clamp is fixed and lower than the first power supply voltage.

Abstract: A memory device includes a storage circuit, a first driving circuit, and a second driving circuit. The storage circuit stores first data and compares the first data and second data. The first driving circuit selectively drives a matching line to a first logic state, depending on a comparison result of the first data and the second data by the storage circuit. The second driving circuit drives the matching line to a second logic state regardless of the comparison result.

Abstract: Disclosed are techniques that can be used within network devices to implement access control functionality. The techniques can include use of a content-addressable memory configured including an access control entry stored therein. Circuitry can be coupled to the content-addressable memory and configured to determine that a value is within a range of values. The circuitry can generate a compare key including a field that is set indicating that the value is within the range of values. The circuitry can provide, to the content-addressable memory, the compare key for locating a corresponding access control entry within the content-addressable memory. The circuitry can receive, from the content-addressable memory, an index of the access control entry stored within the content-addressable memory. The circuitry can select, based on the index of the access control entry, an action.

Abstract: Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.

Abstract: Disclosed are various embodiments for client-side predictive caching of content to facilitate use of the content. If account is likely to commence use of a content item through a client, the client is configured to predictively cache the content item before the use is commenced. In doing so, the client may obtain an initial portion of the content item from another computing device. The client may then initialize various resources to facilitate use of the content item by the client. The client-side cache may be divided into multiple segments with different content selection criteria.

Abstract: A semiconductor module may include a host, a first semiconductor device, and a second semiconductor device. The first host line may be connected to the first and second semiconductor device or devices, according to a set mode.

Abstract: A method of providing a temperature value from a dynamic random access memory (DRAM) device can include receiving a test mode command that activates a temperature value output mode of operation; providing the temperature value to an output buffer circuit; providing an enable signal to the output buffer circuit; and outputting the temperature value that indicates a temperature range, the temperature value is outputted from the output buffer circuit to at least one terminal that is electrically connected external to the DRAM device; wherein the temperature value includes at least 5 binary bits.

Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.

Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.

Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.

Abstract: A sense circuit includes memory cell characterization circuitry, storage circuitry, switching circuitry, and bit line biasing circuitry. The sense circuit is configured to perform a sense operation to sense a characterization of a memory cell. During a pre-charge phase, the memory cell characterization circuitry and the bit line biasing circuitry set differential voltages in the storage circuitry to levels dependent on input offset voltages according to certain polarities. The storage circuitry maintains the differential voltages during the sense phase, allowing the memory cell characterization circuitry to cancel output the input offset voltages when generating output voltages used to identify a characterization of the memory cell. The memory cell characterization circuitry also generates its output voltage based on a reference current through a reference bit line.

Abstract: A voltage charge pump circuit with boost capacitor segments and boost delay chain structures are provided. The voltage charge pump circuit comprising a plurality of boost capacitor segments each of which is individually controlled by a respective signal line of a boost delay chain structure.

Abstract: Decompressing a data set includes inputting data units to a decompression circuit and comparing each input data unit to a run value and to a substitute value. In response to the data unit being not equal to the run value or the substitute value, the decompression circuit outputs the value of the input data unit; in response to the input data unit having the run value and a succeeding data unit having a value N not equal to zero or one, the decompression circuit outputs multiple data units having the run value based on the value N; in response to input data unit having the substitute value, the decompression circuit outputs one data unit having the run value; and in response to one input data unit having the run value and a succeeding data unit equal to zero or one, the decompression circuit outputs one data unit of the substitute value.

Abstract: The present invention provides a semiconductor device that can reduce the power consumption. The semiconductor device includes a plurality of sub-blocks each including a memory cell array, and a plurality of sub-search units corresponding to the respective sub-blocks. Of the data stored in each row of the memory cell array, each sub-block searches for data that matches the input search data according to a search instruction, and outputs a search result indicating hit or miss for each row. Each sub-search unit includes a flag data generation part that generates flag data for presearch to compare with part of the input search data based on the data stored in the corresponding memory cell array, and a search part that compares part of the input search data with the flag data generated by the flag data generation part, and outputs the search instruction to the corresponding sub-block based on the comparison result.

Abstract: A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The configuration data may be stored in configuration memory cells on a programmable integrated circuit, thereby implementing the circuit design with the error code on the programmable integrated circuit. During execution, the programmable integrated circuit may execute error checking and detect and correct errors in the configuration data based on the embedded error code.

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory cells, wherein at least one selected memory cell that is selected from among the plurality of memory cells is programmed based on a high voltage, a high voltage generator configured to generate the high voltage by boosting an input voltage based on a pumping clock, a pumping clock generator configured to generate the pumping clock, a program current controller configured to adjust a program current flowing in the at least one selected memory cells, and a control logic configured to control a frequency of the pumping clock and an amount of the program current based on a time in a program section in which the at least one selected memory cell is programmed.

Abstract: Apparatuses and methods for providing additional drive to multilevel signals representing data are described. An example apparatus includes a first driver section, a second driver section, and a third driver section. The first driver section is configured to drive an output terminal toward a first selected one of a first voltage and a second voltage. The second driver section configured to drive the output terminal toward a second selected one of the first voltage and the second voltage. The third driver section configured to drive the output terminal toward the first voltage when each of the first selected one and the second selected one is the first voltage. The third driver circuit is further configured to be in a high impedance state when the first selected one and the second selected one are different from each other.

Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a signal processing device. The processor accesses data stored in the data storage device via the predetermined interface. The signal processing device performs signal processing on the data. The processor transmits a first power mode change request packet to the data storage device via the predetermined interface, to request to change a data transfer speed of the predetermined interface from a first speed to a second speed. The processor receives a first power mode change confirm packet via the predetermined interface from the data storage device, and in response to the first power mode change confirm packet, the processor determines to keep the data transfer speed at the first speed and does not change the data transfer speed to the second speed.

Abstract: A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.

Abstract: A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. The semiconductor device may include a code synthesis circuit configured to add the period code to a previous synthesis code to generate a synthesis code. The semiconductor device may include a buffer control circuit configured to compare the synthesis code with a selection control code to generate a buffer inactivation signal for controlling input of a data strobe signal.

Abstract: Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data is stored in an NVM array, and error correction vector (ECV) information associated with the NVM array is stored in a content addressable memory (CAM). A parallel query of the NVM array and the CAM is then performed, which includes a query of the NVM array that yields a readout of the NVM array, and a query of the CAM that yields an ECV corresponding to the readout of the NVM array.

Abstract: A semiconductor memory device includes a memory cell array and a main controller. The memory cell array includes a plurality of memory bank arrays, and each of the memory bank arrays includes a plurality of pages. The main controller counts a number of accesses to a first memory region of the memory cell array, generates at least one victim address of at least one neighbor memory region that is adjacent to the first memory region and performs a scrubbing operation sub-pages of the pages corresponding to the at least one victim address when the counted number of accesses reaches a first reference value during a reference interval.

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

Abstract: Apparatuses and methods for refreshing memory cells of a semiconductor device are described. An example apparatus includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.

Abstract: A method of operating a memory system, which includes a memory controller and at least one non-volatile memory, includes storing, in the memory system, temperature-dependent performance level information received from a host disposed external to the memory system, setting an operation performance level of the memory system to a first performance level, operating the memory controller and the at least one non-volatile memory device according to the first performance level, detecting an internal temperature of the memory system, and changing the operation performance level of the memory system to a second performance level that is different from the first performance level. The operation performance level is changed by the memory controller of the memory system, and changing the operation performance level is based on the temperature-dependent performance level information and the detected internal temperature.

Abstract: A wire order testing method for testing pin connection relationships between a memory device and an electronic device is provided. The method includes the steps of: testing the memory device with at least one test pattern to obtain at least one first data; predicting at least one second data that is to be obtained from the testing of the memory device with the test pattern according to the mapping relationships between the test pattern and the pins of the memory device; determining the pin connection relationships between the memory device and the electronic device according to the first data and second data.

Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.

Abstract: A semiconductor device includes a plurality of first pads, a plurality of data input and output units suitable for transmitting a data between a plurality of global lines and the plurality of first pads, respectively, a connection control unit suitable for coupling the plurality of first pads to each other in a test operation period, and a test operation unit suitable for controlling the plurality of data input and output units to transmit a test data in a set order through the plurality of first pads coupled to each other in the test operation period.

Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.

Abstract: An inherent information generating device adapted to an integrated circuit includes a plurality of pairs of source memory cells and a comparison circuit. One of the pairs of source memory cells includes a first source memory cell with a first electrical parameter value and a second source memory cell with a second electrical parameter value. The comparison circuit, coupled to the pairs of source memory cells and configured to generate inherent information of the integrated circuit, includes a first comparator. The first comparator is coupled to the first and second source memory cells, and is configured to compare the first electrical parameter value with the second electrical parameter value, and generate the bit value of a first bit of the inherent information according to the comparison result.

Abstract: A memory circuit includes first and second memory cells. The first memory cell has an access port having a pass gate. The second memory cell also has an access port having a pass gate. The first and second memory cells abut one another along a column direction. The circuit includes at least one conductive structure over the first and second memory cells. The conductive structure may be two interconnected conductive lines. The conductive structure extends along a row direction in a conductive layer and is electrically coupled to the gate terminals of the pass gates.

Abstract: The electronic component comprises: reference-obtaining means for obtaining a physical magnitude referred to as a reference magnitude, which magnitude is dynamically adjustable and representative of the expected activity of said component; comparator means suitable for comparing said reference magnitude with a magnitude of the same type representative of the real activity of said component; and detector means suitable for detecting an attack as a function of the result of said comparison.

Abstract: A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.

Abstract: A communication system receives a binary sequence from a sensor, identifies a power consuming characteristic of the binary sequence, and determines an error component configured to reduce the power consuming characteristic of the binary sequence. The system compares the error component to an error tolerance deviation, and if the error component is below the error tolerance deviation, combines the error component with the binary sequence to produce an output sequence and transmits the output sequence via a serial interface to a receiver configured to receive the output sequence. The error threshold is based in part on an error tolerance characteristic of the receiver.

Abstract: A storage device includes a memory device configured to store data and a memory controller connected to the memory device through a data strobe line and a plurality of data lines. The storage device adds a predetermined specific pattern in front of data and processes data input following the specific pattern as valid data during a read or write operation. The specific pattern is provided in alignment with a data strobe signal (DQS) latency cycle. The memory controller detects a specific pattern input from the memory device during a read operation and processes data input following the specific pattern as valid data when the detected specific pattern matches an internally stored specific pattern.

Abstract: A delay time is set only within the variable delay time of a clock driver and cannot be set longer than the variable delay time of the clock driver. A control circuit adjusts the delay amount of a variable delay circuit so as to synchronize a pulse phase after a first pulse outputted from a pulse generation circuit passes through the variable delay circuit N times and a second pulse outputted from the pulse generation circuit.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured for detecting a defect of a fuse set. The semiconductor device may include a pseudo initial signal generator configured to generate pseudo initial information on the basis of a test mode signal. The semiconductor device may include a fuse-set defect detector configured to compare fuse-set information of a fuse set or the pseudo initial information with a reference value on the basis of a fuse-set address, and detect a defect of the fuse set.

Abstract: Provided herein is a voltage generating circuit including: a negative voltage pump configured to generate a first negative voltage; and a negative voltage regulator configured to generate a second negative voltage using the first negative voltage and output the second negative voltage through an output terminal. The negative voltage regulator includes a first amplifier circuit configured to be controlled by a voltage of the output terminal, and a voltage booster configured to increase a voltage of the output terminal depending on an output voltage of the first amplifier circuit.

Abstract: The power control circuit of the disclosure is configured for a logic circuit performing a predetermined logic calculation on a plurality of input signals from a memory part and outputting a plurality of output signals after logic calculation. The power control circuit includes a switch part that switches between whether to supply a power voltage to the logic circuit or not; a plurality of detector circuits that respectively detect change of signal level of the input signals, wherein when the change of signal level is detected, detect signals are output respectively; and a control circuit that controls the switch part to supply power voltage to the logic circuit based on at least one detect signal from the detector circuits, wherein on the other hand, when the detect signal is not output from the detector circuits, controls the switch part not to supply power voltage to the logic circuit.

Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a content addressable memory. The content addressable memory includes a plurality of memory sections each configured to store data. Additionally, the content addressable memory includes a comparator configured to compare the stored data in each of the plurality of memory sections with search input data. The comparison may be in a time division multiplexed fashion. The comparator may be configured to compare the stored data in each of the plurality of memory sections with search input data in a corresponding one of a plurality of memory access cycles. The content addressable memory may include a state machine configured to control when the comparator compares the stored data in each of the plurality of memory sections with search input data based on a state of the state machine.

Abstract: A memory control device, which includes a signal generating circuit, a data writing circuit and a repeating circuit. The repeating circuit is coupled to the data writing circuit. The signal generating circuit is configured to generate a data strobe signal and send the data strobe signal to a memory. The data strobe signal comprises a preamble signal. The data writing circuit is configured to write a series of data to the memory according to the data strobe signal. The repeating circuit is configured to repeat a first data of the series of data in a period of the preamble signal.

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Abstract: A semiconductor device with a reduced area and capable of higher integration and larger storage capacity is provided. A multi-valued memory cell including a reading transistor which includes a back gate electrode and a writing transistor is used. Data is written by turning on the writing transistor so that a potential according to the data is supplied to a node where one of a source electrode and a drain electrode of the writing transistor and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor and holding a predetermined potential in the node. Data is read by supplying a reading control potential to a control signal line connected to one of a source electrode and a drain electrode of the reading transistor, and then detecting potential change of a reading signal line.

Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.