Abstract: Notifications of events that take place within a virtual space and/or information related the notifications may be transmitted from a server which hosts an instance of the virtual space to the user device via which users may interact with the virtual space. Based on the received notifications and/or the information related to those notifications, the user device may transmit external notifications to one or more presentation control devices that are within the vicinity of the user device. Determining a particular presentation control device to which the user device should transmit the event notification may depend on whether the presentation control device is located within the vicinity of the user device, a predefined association between a user and the presentation control device, and/or whether the user is present at the presentation control device. The presentation control device may concurrently display notifications that belong to different users.

Abstract: A receiver circuit includes: a plurality of first holding circuits respectively latching a plurality of reception data pieces on the basis of a same clock signal; a comparison circuit respectively comparing first reception data pieces and second reception data pieces after a certain time elapses since the latch of the plurality of first holding circuits, the first reception date pieces being respectively latched by the plurality of first holding circuits, the second reception data pieces being respectively input to the plurality of first holding circuits; and a plurality of second holding circuits respectively latching the first reception data pieces when a first output signal of the comparison circuit indicates that the first reception data pieces and the second reception data pieces are identical.

Abstract: An address aligner includes a command address providing unit, an alignment signal providing unit and an alignment unit. The command address providing unit outputs a sync command address signal by delaying a command address signal in synchronization with a first clock signal. The sync command address signal is synchronized with the first clock signal. The alignment signal providing unit outputs alignment clock signals by delaying a chip select signal in synchronization with a second clock signal. The alignment clock signals are synchronized with the second clock signal. The alignment unit outputs a plurality of addresses in synchronization with the alignment clock signals. The plurality of addresses is included in the sync command address signal. If the address aligner according to example embodiments is used, the operation speed of the memory device may be increased by aligning a plurality of addresses in synchronization with the alignment clock signal that is generated based on a chip select signal.

Abstract: A method of an aspect includes receiving a packed data operation mask concatenation instruction. The packed data operation mask concatenation instruction indicates a first source having a first packed data operation mask, indicates a second source having a second packed data operation mask, and indicates a destination. A result is stored in the destination in response to the packed data operation mask concatenation instruction. The result includes the first packed data operation mask concatenated with the second packed data operation mask. Other methods, apparatus, systems, and instructions are disclosed.

Abstract: A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) is disclosed. The CNVCAM cells can be constructed to form the NOR-type match line memory array and the NAND-type match line memory array. In contrast to the Random Access Memory (RAM) accessed by the address codes with the prior knowledge of memory locations, CNVCAM can be pre-configured into non-volatile memory content data and searched by an input content data to trigger the further computing process. The unique property of CNVCAM can provide a key component for neural computing.

Abstract: Pairing information is used by the target application to determine how to connect to the correct controller. A network pipe is established between the target application and the controller. The network pipe is used to pass information, such as to deliver/receive test information, between the controller and target application. A bridge may also be established between the controller and an analysis tool for the device hosting the target application. The bridge creates a communication path for the controller to send/receive information (e.g. commands, queries) to the analysis tool s to perform tests of the target application. Code may also be injected into the target application such that dynamic linked libraries may be simulated. Crash data may also be obtained by the controller (or some other device) that may not be typically available by a particular device platform.

Abstract: An integrated circuit (IC) that includes content addressable memories (CAM) is described. A CAM receives a key and searches through entries stored in the CAM for one or more entries that match the key. If a matching entry is found, the IC returns a storage address indicating a memory location at which the matching was found.

Abstract: A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.

Abstract: A semiconductor system may include a first semiconductor device configured to output a command signal, a first power supply voltage, a second power supply voltage and a third power supply voltage. The semiconductor system may include a second semiconductor device configured to drive an internal power supply voltage with the first power supply voltage in response to an internal command signal generated by decoding the command signal, generate first output data from first internal data by being supplied with the internal power supply voltage and the second power supply voltage, and generate second output data from second internal data by being supplied with the internal power supply voltage and the second power supply voltage.

Abstract: A circuit includes a tracking bit line, a tracking unit connected to the tracking bit line and a detection unit. The tracking unit is configured to receive a first control signal and configured to selectively charge or discharge a voltage on the tracking bit line in response to the first control signal. The detection unit is coupled to the tracking bit line and configured to generate a sense amplifier enable (SAE) signal in response to the voltage level on the tracking bit line.

Abstract: An address comparator circuit includes a first determination unit suitable for activating a first control signal when a first address corresponding to a previous read command is identical with a second address corresponding to a current read command; a second determination unit suitable for activating a second control signal when the previous and current read commands are consecutively inputted to the address comparator circuit with an interval of a specific number of clocks or less; and a blocking signal generation unit suitable for generating a blocking signal that blocks data transmission between a memory array and an external device based on the first and the second control signals.

Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

Abstract: A voltage regulator including a comparing circuit, a first circuit, a transistor, a voltage reference circuit, and a latching circuit. The comparing circuit compares a first and second voltage references and generates an output based on the comparison. The first circuit amplifies the output of the comparing circuit. The transistor includes: a gate configured to receive a first output of the first circuit; a first terminal connected to a voltage supply terminal; and a second terminal. A regulated output voltage of the voltage regulator is based on a voltage at the second terminal. The voltage reference circuit generates the second voltage reference based on the voltage at the second terminal. The latching circuit, based on a second output of the first circuit: adjusts the second voltage reference; and switches between forcing the second output of the first circuit to be in a first state to be in a second state.

Abstract: A storage device with a memory may include memory block health monitoring and behavior tracking. Each memory block may be analyzed based on one or more dummy wordlines within the block may not be accessible for normal data storage. The dummy wordlines may be programmed with a known data pattern that can be tracked and analyzed for potential errors, which may be used as representation of the health of the memory block. Adjustments can be made to the operating parameters (e.g. read voltages) to optimize each memory block based on its error analysis.

Abstract: A memory device includes a storage unit in which a plurality of semiconductor chips each comprising a plurality of memory blocks respectively arranged in a planar direction and a plurality of redundant blocks respectively arranged in a planar direction are stacked, a detecting unit configured to detect a defect of each of the memory blocks in the storage unit; a checking unit configured to check free capacity in each of the redundant blocks in the storage unit, and a determining unit configured to determine a substitute block to be substituted for the memory block in which the defect has been detected from the redundant blocks having the free capacity.

Abstract: Disclosed are various embodiments for client-side predictive caching of content to facilitate instantaneous use of the content. If a user is likely to commence use of a content item through a client, the client is configured to predictively cache the content item before the user commences use. In doing so, the client may obtain metadata for the content item and an initial portion of the content item from another computing device. The client may then initialize various resources to facilitate instantaneous use of the content item by the client based at least in part on the metadata and the initial portion. The client-side cache may be divided into multiple segments with different content selection criteria.

Abstract: Techniques and circuits for testing and configuring magnetic memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation. Examples include adjustment of bias voltages, sense amplifier offset values, and timing parameters to improve the efficiency of testing operations as well as improve reliability and speed of normal operation.

Abstract: A semiconductor apparatus may include an internal voltage level controller configured to output either a normal trimming code or a test voltage code as a voltage control code in response to a test mode signal, a specific operation start signal, and a specific operation end signal. The semiconductor apparatus may include an internal voltage generator configured to generate an internal voltage and control a voltage level of the internal voltage in response to the voltage control code.

Abstract: A semiconductor memory apparatus includes a first comparison block configured to compare a plurality of channel data with one another and generate a first comparison signal, or output one of the plurality of channel data as the first comparison signal, in response to a plurality of channel select signals; a second comparison block configured to compare the plurality of channel data and generate a second comparison signal when the plurality of channel select signals have a predetermined combination and a channel detection signal has a predetermined logic level; a channel selection detection block configured to enable the channel detection signal when only one channel select signal among the plurality of channel select signals is enabled; and a combined output block configured to enable a test result signal when at least one comparison signal of the first and second comparison signals is enabled.

Abstract: A method for storing database information includes storing a table having data values in a column major order. The data values are stored in a list of blocks. The method also includes assigning a tuple sequence number (TSN) to each data value in each column of the table according to a sequence order in the table. The data values that correspond to each other across a plurality of columns of the table have equivalent TSNs. The method also includes assigning each data value to a partition based on a representation of the data value. The method also includes assigning a tuple map value to each data value. The tuple map value identifies the partition in which each data value is located.

Abstract: A method for storing database information includes storing a table having data values in a column major order. The data values are stored in a list of blocks. The method also includes assigning a tuple sequence number (TSN) to each data value in each column of the table according to a sequence order in the table. The data values that correspond to each other across a plurality of columns of the table have equivalent TSNs. The method also includes assigning each data value to a partition based on a representation of the data value. The method also includes assigning a tuple map value to each data value. The tuple map value identifies the partition in which each data value is located.

Abstract: A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges in a variable state in accordance with application of different electrical signals, a control circuit that, in operation, receives a control signal, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells in accordance with the control signal, and an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information.

Abstract: A disclosed example sense programmed states of memory cells includes starting a counter at a time of activating a plurality of memory cells. Binary values are obtained based on sense amplifiers in circuit with the memory cells in response to the counter reaching a trigger count value. A programmed state of the memory cells is determined based on the binary values.

Abstract: A data alignment device includes a buffer configured to buffer a data strobe signal, output a data strobe pulse signal, and buffer inputted data, a latch configured to latch the data in correspondence to the data strobe pulse signal, a first delay configured to delay the data strobe pulse signal and output a delayed signal, a divider configured to divide the delayed signal at a time of activation of a division control signal and generate a plurality of divided signals, a control circuit configured to receive a command signal, a clock, the data strobe signal, and the plurality of divided signals, and control the division control signal for controlling an enable state of the divider, and an alignment circuit configured to align output data in correspondence to the plurality of divided signals.

Abstract: A pre-computation based TCAM configured to reduce the number of match lines being pre-charged during a search operation to save power is disclosed. The pre-computation based TCAM stores additional information in a secondary TCAM that can be used to determine which match lines in a primary TCAM storing data words to be searched need not be pre-charged because they are associated with data words guaranteed to not match. The additional information stored in secondary TCAM can include a pre-computation word that represents a range inclusive of a lower and upper bound of a number of ones or zeroes possible in a corresponding data word stored in the primary TCAM.

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

Abstract: Separate key processing units generate different search keys based off of a single master key received at a ternary memory array chip. A reference search key and selection logic are provided to reduce power dissipation in a global search key bus across the chip. The reference search key is the output of one of the key processing units and its bytes are compared with the output from each of the other key processing units. A select signal from each unit indicates which bytes match. Each matching byte at each key processing unit is blocked from changing corresponding bit line logic values across the chip, reducing the number of voltage switches occurring in the global search key bus. The select signal causes a selection module local to each superblock to select the matching byte(s) from the reference search key and non-matching byte(s) from the global search key bus to reconstitute the entire search key.

Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.

Abstract: An antifuse memory device includes an antifuse memory cell, a reference current generation unit, and a comparison unit. The antifuse memory cell includes an antifuse. The reference current generation unit provides a reference current selected from a plurality of reference currents. The comparison unit compares an intensity of a cell current flowing through the antifuse with an intensity of the reference current and provides an output signal corresponding to a result of the comparison.

Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

Abstract: An integrated circuit chip includes a test circuit suitable for performing a test operation and generating a test result signal indicating whether there is an error or not in the integrated circuit chip, a transmitting unit suitable for transmitting the test result signal through an interlayer channel. The interlayer channel is precharged to a first level before the transmitting unit transmits the test result signal, and the interlayer channel is driven to a second level when there is an error.

Abstract: A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.

Abstract: A self-refresh device is disclosed, which relates to a technology for generating a self-refresh period by reflecting refresh characteristics of an actual cell in a semiconductor device. The self-refresh device includes: a period generation unit configured to output a period control signal by comparing an output voltage of a dummy cell with a reference signal; a phase detection unit configured to detect a phase of the period control signal in response to an oscillation signal having a fixed period; and a refresh signal output unit configured to output a self-refresh period signal in response to the oscillation signal and an output signal of the phase detection unit.

Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.

Abstract: Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.

Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.

Abstract: Disclosed is an organic light emitting display device including: plurality of data lines; a charging line formed in a direction crossing the plurality of data lines; and charging switches connected between the charging line and the data lines. The charging line inputs a charging voltage and the charging switches are individually controlled in data line.

Abstract: A flash memory, a memory module, a computer-readable recording medium and an operating method are provided, which can perform a flexible setup by a flexible clock scheme. A NAND-type flash memory 100 of the invention includes: a memory array 110 having NAND-type memory cells, a controller 150 including a processor and a ROM/RAM, and a system clock generating circuit 200 configured to generate an internal system clock signal. The ROM/RAM is at least stored with setup commands for a setup of the flash memory, and the processor processes the setup commands based on the internal system clock signal during a setup period. The controller 150 further controls the system clock generating circuit 200, so that a frequency of the internal system clock signal becomes high speed during the setup period.

Abstract: In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.

Abstract: A semiconductor package includes first and second slave chips stacked vertically; and a master chip connected to the first and second slave chips, each of the slave chips including, a plurality of memory blocks, and a redundancy block, and the master chip including, a fuse block configured to repair a defective memory block detected from the first slave chip and a defective memory block detected from the second slave chip by using the redundancy block of the first slave chip and the redundancy block of the second slave chip, respectively, and a block selection circuit configured to, connect the redundancy blocks of the first and second slave chips, one or more non-defective ones of the plurality of memory blocks of the first slave chip, and one or more non-defective ones of the plurality of memory blocks of the second slave chip to an input/output circuit.

Abstract: A semiconductor memory apparatus includes a write driver configured to transfer input data to a data storage region. The semiconductor memory apparatus may also include a sense amplifier configured to sense and amplify the data stored in the data storage region and output output data. Further, the semiconductor memory apparatus may also include an enable signal generation block configured to generate a write driver enable signal and a sense amplifier enable signal according to a comparison result of the input data and the output data.

Abstract: A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have values selected from a set of at least three entry values and 2n distinct inputs can be encoded into k-entry codewords for some n>k. A vector storage element comprising k cells can store an k electrical quantities (voltage, current, etc.) corresponding to a codeword. The voltage code is such that, for at least one position of a vector, there are at least three vectors having distinct entry values at that position and, for at least a subset of the possible codewords, the sum of the entry values over the positions of each vector is constant from vector to vector in that subset. The storage device might be an integrated circuit device, a discrete memory device, or a device having embedded memory.

Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.

Abstract: A storage device has a plurality of storage cells for storing data values. Control circuitry is provided to simultaneously couple at least two cells to at least one common signal line. Sensing circuitry is provided to sense a signal on the at least one common signal line, which indicates a result of a logical operation applied to the data values stored in each of the at least two storage cells. This allows logic operations such as AND, OR, XOR, etc. to be performed within a storage device so that it is not necessary to read out each data value independently and transfer each data value to a separate processing circuit in order to find the result of the logical operation. This helps to improve performance within a data processing apparatus having the storage device.

Abstract: A memory system is provided which includes a nonvolatile memory; and a controller configured to control the nonvolatile memory, wherein the controller comprises a voltage detector configured to detect a level of a power supply voltage; and wherein when a level of the power supply voltage is lower than a first threshold value, the controller issues a reset command to the nonvolatile memory and then performs a reset operation.

Abstract: Disclosed are a semiconductor memory device, a memory system including the same, and an operating method thereof. The memory system includes: a semiconductor memory device including a plurality of memory chips; and a controller configured to measure a cell current of each of the plurality of memory chips, generate temperature compensation data corresponding to the measured cell current, and store the generated temperature compensation data in each of the plurality of memory chips.

Abstract: In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read wordline from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.

Abstract: The invention may include a semiconductor apparatus comprising: a first die configured to latch and output external input data according to a strobe signal, to detect a valid pulse from among pulses of the strobe signal, and to generate a valid signal; and a second die configured to write data transmitted from the first die in response to the valid signal.

Abstract: An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the rectangular printed circuit card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card.

Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.