Including Signal Comparison Patents (Class 365/189.07)
  • Patent number: 9001596
    Abstract: A nonvolatile memory apparatus includes a read/write control unit and a voltage generation unit and the memory cell. The read/write control circuit is configured to supply a bias voltage in response to a read control signal, a write control signal and data. The voltage generation unit is configured to compare a level of the bias voltage with a voltage level of a sensing node and drive the sensing node at voltage having a constant level based on a result of the comparison. The memory cell coupled with the sensing node and configured to receive the voltage having the constant level.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventor: Chul Hyun Park
  • Publication number: 20150092500
    Abstract: A semiconductor memory apparatus includes a first data storage region configured to be supplied with a driving voltage via a first voltage line, a second data storage region configured to be supplied with a driving voltage via a second voltage line and a switch configured to one of electrically couple the first voltage line with the second voltage line and decouple the first voltage line from the second voltage line in response to a switching control signal.
    Type: Application
    Filed: March 13, 2014
    Publication date: April 2, 2015
    Applicant: SK HYNIX INC.
    Inventor: Kyeong Pil KANG
  • Patent number: 8995213
    Abstract: A nonvolatile memory device includes a memory cell array including a main cell area and a retention flag cell area, a retention check unit configured to compare a read result for retention flag cells included in the retention flag cell area to a reference value, and determine a retention state of the retention flag cells according to a comparison result, and a control logic configured to provide a retention check result based on the retention state to the external device in response to a retention check request provided from an external device.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventor: In Hwan Song
  • Patent number: 8995206
    Abstract: A device, a computer readable medium and a method that may include performing a shortened read attempt of multiple data memory cells that store data to provide an estimate of the data; wherein the shortened read attempt has a duration that is shorter than a duration of a full read attempt; performing a shortened read attempt of redundant memory cells that store redundant information to provide an estimate of the redundant information; wherein the estimate of the redundant information is indicative of an expected number of data memory cells that store a certain logic value; determining, based on the estimate of the data, an estimated number of data memory cells that store the certain logic value; comparing the expected number to the estimated number; and providing the estimate of the data as a read result if the expected number and the estimated number equal each other.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: March 31, 2015
    Assignee: Technion Research and Development Foundation Ltd.
    Inventors: Amit Berman, Yitzhak Birk
  • Patent number: 8988919
    Abstract: A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal. The control chip includes a first control circuit outputting a synchronization signal and receiving a data signal, a delay adjustment circuit delaying the synchronization signal and outputting the same as a delayed synchronization signal, a phase comparator circuit comparing the phases of the replica signal and the synchronization signal, and a delay control circuit controlling the delay amount of the delay adjustment circuit based on a comparison result of the phase comparator circuit.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: March 24, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Yoshiro Riho
  • Patent number: 8982634
    Abstract: The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 17, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Yu-Hsiung Tsai, Yuan-Tai Lin, Ching-Yuan Lin, Chao-Wei Kuo, Shang-Wei Fang, Wein-Town Sun
  • Patent number: 8982635
    Abstract: A writing method of a semiconductor memory device includes applying a plurality of program voltages sequentially generated to a selected word line, and applying any one of a plurality of source selection line voltages to a source selection line when each of the plurality of program voltages is applied.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: March 17, 2015
    Assignee: SK Hynix Inc.
    Inventors: Tae Gyun Kim, Chi Wook An
  • Patent number: 8982255
    Abstract: An image pickup unit includes: an image pickup section including a plurality of pixels, each of the pixels including a photoelectric conversion device; and a driving section that includes an amplifier and drives each of the pixels to perform a read out operation intended to read out electric charge obtained by the photoelectric conversion device from the pixel as a signal with use of the amplifier, a pixel reset operation intended to reset electric charge in the pixel, and an amplifier reset operation intended to reset an operation of the amplifier. The driving section drives each of the pixels to allow one or both of end timing of the pixel reset operation and end timing of the amplifier reset operation not to be included in a predetermined power-source potential unstable period.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Yuichiro Minami, Michiru Senda
  • Patent number: 8982636
    Abstract: A memory comprises a memory cell, a sense amplifier, and a control unit. The memory cell stores a first bit and a second bit. The sense amplifier senses a first cell current and a second cell current corresponding to the first and the second bits respectively with a voltage applying on the memory cell. The control unit determines a digital state of the first bit by comparing a first reference current with the first cell current or by comparing a reference data with a first delta current between the first cell current and the second cell current.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 17, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Tsung-Yi Chou, Ming-Feng Zhou, Chung-Yi Li, Zong-Qi Zhou
  • Publication number: 20150071011
    Abstract: A memory device comprising a memory array comprising a plurality of memory cells, a plurality of bitlines and a plurality of wordlines for writing to the plurality of memory cells and a sense amplifier coupled to a first bitline of the plurality of bitlines, for reading the contents of a selected memory cell, the sense amplifier comprising a first cascode transistor pair coupled to a second cascode transistor pair, the first cascode transistor pair coupled to the first bitline and a second bitline, and a current comparator coupled to a drain side of the second cascode transistor pair for determining a value of the selected memory cell.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 12, 2015
    Applicant: Sony Corporation
    Inventor: Kerry Tedrow
  • Patent number: 8976605
    Abstract: A high voltage generation circuit includes a plurality of pumps configured to generate a final pump voltage, a plurality of switches configured to couple the pumps to various nodes, a voltage division circuit configured to divide the final pump voltage from the pumps interconnected by the switches, and outputting a divided voltage, a section signal generation circuit configured to generate a plurality of section signals by comparing the divided voltage with each of different reference voltages, and a section signal combination circuit configured to generate enable signals for controlling the switches by combining the section signals.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventor: Je Il Ryu
  • Patent number: 8976613
    Abstract: A circuit for a differential current sensing scheme includes first and second cell segments, first and second reference cells, and first and second current sense amplifiers. The first and second reference cells are configured to store opposite logic values. The first and second current sense amplifiers are each configured with a first node and a second node for currents therethrough to be compared with each other. A cell of the first cell segment and a cell of the second cell segment are coupled to the first nodes of the first and second current sense amplifiers, respectively, and the first and second reference cells are coupled to both the second nodes of the first and second current sense amplifiers.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventor: Sergiy Romanovskyy
  • Publication number: 20150063042
    Abstract: The present invention relates to a regulation circuit for a charge pump and to a method of regulating a charge pump. The regulation circuit comprises a detector operable to analyze a temporal activity of the charge pump, and a pump clock generator coupled to an output of the detector and having an output coupled to a clock input of the charge pump to vary a pump clock frequency of the charge pump in dependence of the analysis of the detector, or a supply or voltage generator coupled to an output of the detector and having an output coupled to the charge pump to vary an amplitude of a clock signal within the charge pump in dependence of the analysis of the detector.
    Type: Application
    Filed: August 14, 2014
    Publication date: March 5, 2015
    Applicant: EM MICROELECTRONIC MARIN S.A.
    Inventors: Lubomir PLAVEC, Filippo MARINELLI
  • Patent number: 8971136
    Abstract: A memory device automatically correcting the effect of collisions of high-energy particles, comprising at least one memory cell, and further comprising: retention means for retaining, for a determined period, a single copy of the stored value stored in said memory cell; detection means for detecting a change of state of said memory cell, by comparing the stored value stored in said memory cell with the value in retention in said retention means; and management means suitable for determining whether a detected change of state of said memory cell is due to a high-energy particle and, in which case, to automatically command a reloading of the stored value stored in said retention means into said memory cell.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: March 3, 2015
    Assignee: Thales
    Inventors: Bruno Jacquet, Raoul Rodriguez, Vincent Lavalette
  • Patent number: 8972790
    Abstract: A controller section outputs a first signal and a second signal holding a phase relationship with the first signal. The second signal is received by a memory I/F section via a FIFO memory of an error detecting section. The memory I/F section performs timing adjustment for the first and second signals, outputs the first and second signals after the timing adjustment to a memory, and loops back the second signal. A data comparator compares the looped-back second signal with the original second signal outputted from the FIFO memory and corresponding to the looped-back signal.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: March 3, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hisataka Nakabayashi, Miho Takeda, Masanori Ito
  • Publication number: 20150055423
    Abstract: A data storage unit configured to generate a data voltage; and a data comparison unit including a first input terminal for receiving the data voltage and a second input terminal for receiving a reference voltage, and being configured to compare the voltage levels of the first and second input terminals are included, wherein the data comparison unit compares the voltage levels of the first and second input terminals.
    Type: Application
    Filed: November 18, 2013
    Publication date: February 26, 2015
    Applicant: SK hynix Inc.
    Inventor: Seung Kyun LIM
  • Publication number: 20150055422
    Abstract: A semiconductor memory apparatus includes a driving current control block configured to sense a resistance value of a dummy memory element, and generates a write driver control signal; and a write driving block configured to provide a driving voltage to a memory cell array in response to a write driver enable signal and the write driver control signal.
    Type: Application
    Filed: November 18, 2013
    Publication date: February 26, 2015
    Applicant: SK hynix Inc.
    Inventor: Kyu Sung KIM
  • Patent number: 8964496
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 8964489
    Abstract: When writing into an antifuse memory element finishes, a value of resistance of the memory element rapidly decreases; accordingly, an output voltage of a boosting circuit which produces a writing voltage rapidly decreases. By detecting a change in the output voltage of the boosting circuit to control a writing command, the writing operation can be stopped immediately after the memory element is shorted. Thus, unnecessary current consumption caused by continuing a writing operation on the shorted memory element can be suppressed.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshihiko Saito
  • Publication number: 20150049559
    Abstract: Semiconductor systems are provided. The semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device generates an input calibration signal during a mode register write operation and receives an output data and an output calibration signal to control a recognition point of a logic level of the output data according to a delay time of the output calibration signal during a read operation. The second semiconductor device stores the input calibration signal therein during the mode register write operation and outputs the output calibration signal and the output data during the read operation.
    Type: Application
    Filed: December 13, 2013
    Publication date: February 19, 2015
    Applicant: SK hynix Inc.
    Inventor: Keun Soo SONG
  • Patent number: 8958231
    Abstract: A memory cell includes a first transistor controlling writing of the first date by being in an on state, and holding of the first data by being in an off state, a second transistor in which a potential of one of a source and a drain is a potential of the second data and a potential of a gate is a potential of the first data, and a third transistor which has a conductivity type opposite to that of the second transistor, which has one of a source and a drain electrically connected to the other of the source and the drain of the second transistor, and in which a potential of a gate is a potential of the first data.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Daisuke Matsubayashi
  • Patent number: 8958265
    Abstract: A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: February 17, 2015
    Inventor: Laurence H. Cooke
  • Patent number: 8958232
    Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chung-Cheng Chou, Hung-Jen Liao, Bin-Hau Lo
  • Patent number: 8958260
    Abstract: Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor device. The at least one voltage sensor is configured to generate a signal indicative of a state of the operating voltage. Methods of monitoring a voltage in a semiconductor device include determining a magnitude of an operating voltage for an operational circuit in a semiconductor device. A signal may be generated indicating a state of the operating voltage.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: February 17, 2015
    Assignee: Micron Technology, Inc.
    Inventor: David R. Resnick
  • Patent number: 8958235
    Abstract: This semiconductor memory device comprises: a memory cell array configured as an arrangement of memory cells disposed at intersections of a plurality of first lines disposed substantially in parallel and a plurality of second lines disposed to intersect the first lines, each of the memory cells including a variable resistance element; and a control circuit configured to control the memory cell array. The control circuit is configured to change a voltage value of a resetting verify voltage applied for confirming completion of the resetting operation according to a degree of change of resistance of the memory cell when performing the resetting operation to change the memory cell from a low-resistance state to a high-resistance state.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junya Matsunami
  • Patent number: 8953393
    Abstract: A semiconductor device may test a semiconductor memory device by storing a data sample that is sampled from among data requested to be written into a semiconductor memory device and by comparing the data sample with data read from the semiconductor memory device which corresponds to the data sample.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: February 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Hong-Sik Kim, Hyung-Dong Lee, Hyung-Gyun Yang
  • Patent number: 8953358
    Abstract: A memory device in which one memory cell can operate in both a single-level cell mode and a multi-level cell mode includes a signal transmission path for a multi-level cell mode in which a multi-bit digital signal representing any of three or more states input to the memory circuit is converted by a D/A converter and stored in the memory cell and the stored data is read by converting a signal output from the memory cell into a multi-bit digital signal with an A/D converter and the multi-bit digital signal is output from the memory circuit, and a signal transmission path for a single-level cell mode in which a single-bit digital signal representing any of two states input to the memory circuit is directly stored in the memory cell and the signal stored in the memory cell is directly output from the memory cell.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuji Nishijima, Hiroyuki Miyake
  • Patent number: 8953354
    Abstract: A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural number of 2 or larger) lines to each of which a first bit column of an address is assigned in advance; a comparison circuit; and a control circuit. The i×j lines to each of which a first bit column of an objective address is assigned in advance are searched more than once and less than or equal to j times with the use of the control circuit and a cache hit signal or a cache miss signal output from the selection circuit. In such a manner, the line storing the objective data is specified.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20150036441
    Abstract: A current generation circuit includes a mirroring circuit suitable for being charged by using a bias voltage, wherein a voltage level of the charged voltage varies corresponding to changes in a voltage level of a power voltage, a comparison circuit suitable for comparing the charged voltage with a feedback voltage, and a current driving circuit suitable for generating a current based on a voltage output from the comparison circuit.
    Type: Application
    Filed: January 22, 2014
    Publication date: February 5, 2015
    Applicant: SK hynix Inc.
    Inventor: Hyun Jong JIN
  • Patent number: 8947911
    Abstract: A bit line power implementing circuit is provided, the bit line power implementing circuit has a bit line discharge oscillator to convert the supply voltage to a pulse; a decoder coupled to the bit line discharge oscillator to decode the pulse, and providing a first pulse with a first frequency and a second pulse with a second frequency; a first and a second counters, coupled to the decoder, and receiving the first and the second pulses respectively, and outputting a signal proportional to an average and a minimum read currents respectively; a divider outputting a read current ratio of the average read current to the minimum read current; and a multiplier for multiplying the supply voltage the read current ratio to output a bit line power consumption corresponding to the supply voltage.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: February 3, 2015
    Assignee: United Microelectronics Corp.
    Inventor: Hsi-Wen Chen
  • Patent number: 8947972
    Abstract: A non-volatile memory system evaluates user data before writing in order to potentially group addresses for writing within a cycle. The system can determine which sense amplifier addresses of a column address will be programmed in a column address cycle. The number of bits that will be programmed is compared with an allowable number of parallel bits. The system generates groups of sense amplifier addresses based on the comparison. The system generates groups that include a total number of bits to be programmed that is within the allowable number of parallel bits. Each group is programmed in one sense amplifier address cycle. Multiple sense amplifier addresses can be grouped for programming while still remaining within an allowable number of parallel programming bits. The system performs a read before write operation and generates bitmap data for the grouping information corresponding sense amplifier addresses.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Gopinath Balakrishnan, Tz-Yi Liu
  • Patent number: 8947944
    Abstract: A non-volatile memory system is disclosed that evaluates during a read before write operation whether to skip programming of portions of group of memory cells during a subsequent write operation. By evaluating skip information during a read before write operation, the write operation can be expedited. The additional overhead for evaluating skip information is consumed during the read before write operation. By performing a skip evaluation during the read before write operation, a full analysis of the availability of skipping programming for memory cells can be performed. Skip evaluations in different embodiments may be performed for entire bay address cycles, column address cycles, and/or sense amplifier address cycles. In some embodiments, some skip evaluations are performed during read before write operations while others are deferred to the write operation. In this manner, the number of data latches for storing skip information can be decreased.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Gopinath Balakrishnan, Tz-Yi Liu, Henry Zhang
  • Patent number: 8947920
    Abstract: According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: February 3, 2015
    Inventors: Masahiro Takahashi, Tsuneo Inaba, Dong Keun Kim, Ji Wang Lee
  • Patent number: 8947946
    Abstract: Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory devices.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Publication number: 20150029798
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Application
    Filed: July 26, 2013
    Publication date: January 29, 2015
    Applicant: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 8942309
    Abstract: An intermediate voltage is maintained between a first voltage and a second voltage by conditionally or selectively performing data bus inversion (DBI) and/or data swap operations on a first and second transmit channel. The operations are performed to, in some instances, create a current imbalance between the first and second channel where the intermediate voltage drifts toward a target range or target value between the first voltage and second voltage in response to the created imbalance.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: January 27, 2015
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Wilson
  • Patent number: 8942050
    Abstract: A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: January 27, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hiroshi Tomotani, Kazuhiko Shimakawa, Ryotaro Azuma, Yoshikazu Katoh, Yuichiro Ikeda
  • Patent number: 8937838
    Abstract: An expected value associated with stored values in solid state storage, as well as a set of three or more points are obtained where the three or more points include a voltage and a value associated with stored values. Two points having ratios closest to the expected value are selected from the set. A voltage is determined based at least in part on the selected two points and the expected value.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 20, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Xiangyu Tang, Lingqi Zeng, Jason Bellorado, Frederick K. H. Lee, Arunkumar Subramanian
  • Patent number: 8934306
    Abstract: Memory devices and methods for operating a memory include filtering a histogram of sensed data of the memory, and adjusting a parameter used to sense the memory using the filtered histogram. Filtering can be accomplished by averaging or summing, and may include weighting the sums or averages.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Zhenlei Shen, William H. Radke
  • Patent number: 8934317
    Abstract: A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Jin Jeon, Yoon Joo Eom, Young Chul Cho
  • Patent number: 8934312
    Abstract: Aspects of the invention provide for a structure and method for determining a degree of process variation skew between a plurality of bit cells in a static random-access-memory (SRAM) column architecture. In one embodiment, a structure includes: a plurality of bit cells within a static random access memory (SRAM) column architecture; a digital-to-analog converter (DAC) connected to the bit cells through a pair of multiplexers; and a pre-charge circuit connected to the bit cells through the pair of multiplexers, wherein the DAC and the pre-charge circuit control and test the bit cells to determine a degree of process variation skew between each of the bit cells.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Albert M. Chu, Daryl M. Seitzer, Rohit A. Shetty
  • Patent number: 8934313
    Abstract: A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Joong Song, Gyu-Hong Kim, Jae-Seung Choi, Soung-Hoon Sim, In-Gyu Park, Chan-Ho Lee, Hyun-Su Choi, Jong-Hoon Jung
  • Patent number: 8934278
    Abstract: A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: January 13, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Rakesh Vattikonda, Nishith Desai, ChangHo Jung, Sei Seung Yoon, Esin Terzioglu
  • Patent number: 8934304
    Abstract: A nonvolatile memory device includes a plurality of memory cells and a plurality of monitor cells. The method of operating the device includes erasing the plurality of memory cells and the plurality of monitor cells, programming at least one first memory cell among the plurality of memory cells to a first program state, programming at least one first monitor cell among the plurality of monitor cells to the first program state, and refreshing data stored in the plurality of memory cells according to a result read from the at least one first monitor cell during a read operation of the at least one first monitor cell.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunsoo Cho, Kyoungil Bang
  • Publication number: 20150009766
    Abstract: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current butler configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.
    Type: Application
    Filed: September 24, 2014
    Publication date: January 8, 2015
    Inventor: JAE-KWAN PARK
  • Patent number: 8929165
    Abstract: A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-pil Son, Young-soo Sohn
  • Patent number: 8929125
    Abstract: Apparatuses and methods of forming a memory cell is described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Durai Vishak Nirmal Ramaswamy, Gurtej S. Sandhu, Adam D. Johnson, Scott E. Sills, Alessandro Calderoni
  • Patent number: 8929167
    Abstract: Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: January 6, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Jung Pill Kim, Taehyun Kim, Xia Li, Seung H. Kang
  • Patent number: 8929157
    Abstract: Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a “too high” signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a “too low” signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: January 6, 2015
    Assignee: Intel Corporation
    Inventors: Christopher P. Mozak, Navindra Navaratnam, Mahmoud Elassal
  • Patent number: 8929158
    Abstract: A method to trim a reference voltage source formed on an integrated circuit includes configuring the integrated circuit in a test mode; providing a power supply voltage and a trim code sequence to the integrated circuit where the power supply voltage is provided by a precision reference voltage source; generating a target voltage on the integrated circuit using the power supply voltage; generate a reference voltage using the reference voltage source formed on the integrated circuit; applying one or more trim codes in the trim code sequence to the reference voltage source to adjust the reference voltage; comparing the reference voltage generated based on the trim codes to the target voltage; asserting a latch signal in response to a determination that the reference voltage generated based on a first trim code is equal to the target voltage; and storing the first trim code in response to the latch signal being asserted.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: January 6, 2015
    Assignee: Integrated Silicon Solution, Inc.
    Inventors: MingShiang Wang, Kyoung Chon Jin