Abstract: One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example.

Abstract: A voltage regulator apparatus and an associated method are provided, where the voltage regulator apparatus includes: a voltage regulator module for regulating an input voltage according to a bandgap reference voltage to generate an output voltage; and a plurality of sensing modules. Ina situation where the output voltage abruptly decreases, a sensing module reduces, based on a variation amount of the output voltage, a decrement of the output voltage. In a situation where the output voltage abruptly increases, another sensing module reduces, based on another variation amount of the output voltage, an increment of the output voltage. In addition, yet another sensing module senses variation of the output voltage, converts the variation of the output voltage into a current signal, and applies the current signal to a control terminal within the voltage regulator module to indirectly control the output voltage.

Abstract: A voltage generation circuit includes a plurality of voltage generation units each configured to include an internal voltage with a reference voltage, generate a detection signal based on a comparison result between the internal voltage and the reference voltage, and adjust the level of the internal voltage in response to an oscillation signal, a control unit configured to generate an oscillation control signal in response to the detection signals, an oscillator configured to generate the oscillation signal in response to the oscillation control signal, and a selective output unit configured to selectively supply the oscillation signal to one or more of the plurality of voltage generation units in response to the detection signals.

Abstract: An integrated circuit that includes a generator unit connected to one or more pull-up units, one or more pull-up units connected to one or more source lines and an array of memory cells connected to the one or more source lines. The generator unit is configured to set a first voltage signal of each pull-up unit of the one or more pull-up units. Each pull-up unit of the one or more pull-up units is connected with the corresponding source line of the one or more source lines and is configured to set a current of the corresponding source line of the one or more source lines. The array of memory cells is electrically connected to the one or more source lines and one or more bit lines.

Abstract: A write assist circuit includes a first switch, a second switch and a bias voltage circuit. The first switch connects a cell supply voltage node of a memory cell to a power supply voltage node in response to a write control signal having a first state, and disconnects the cell supply voltage node from the power supply voltage node in response to the write control signal having a second state. The bias voltage circuit generates, at an output thereof, an adjustable bias voltage lower than the power supply voltage. The second switch connects the cell supply voltage node to the output of the bias voltage circuit in response to the write control signal having the second state, and disconnects the cell supply voltage node from the output of the bias voltage circuit in response to the write control signal having the first state.

Abstract: Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.

Abstract: A method and a memory for sensing a state of a memory cell while the memory cell capacitor is isolated from a data line are described. An activation device of the memory cell can be enabled to couple the memory cell capacitor to a parasitic capacitance of the active data line for charge sharing. The activation device can then be disabled to isolate the memory cell capacitor from the active data line. The state of the memory cell can then be sensed while the memory cell capacitor is isolated from the active data line. After the sense operation, the activation device can be re-enabled in order to restore the data to the memory cell capacitor that was destroyed during the sense operation.

Abstract: A method of writing data is performed in a data storage device with a controller and a memory. The memory includes latches and multiple storage elements and is operative to store a first number of bits in each storage element according to a first mapping of sequences of bits to states of the storage elements. The method includes loading data bits into the latches within the memory and generating manipulated data bits in the latches by manipulating designated data bits in the latches using one or more logical operations. The method also includes storing sets of the manipulated data bits to respective storage elements of the group of storage elements according to the first mapping. The designated data bits correspond to states of the respective storage elements according to a second mapping of sequences of bits to states. The second mapping is different than the first mapping.

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

Abstract: Systems and methods are provided for generating a soft information metric corresponding to a bit stored in a memory. The systems and methods include comparing a symbol value associated with the stored bit to a plurality of decision thresholds to obtain a plurality of binary values. One of the plurality of binary values is selected to obtain a reference value. Further, a frequency metric is computed, which corresponds to the number of times each of the plurality of binary values equals a predefined value. The soft information metric is then determined based on the frequency metric and the reference value.

Abstract: Path transistor malfunction is reduced. A path gate circuit includes transistors MP, MW, and MC. The transistor MP functions as a path transistor that connects a signal line INL to a signal line OUTL. The transistor MW connects a signal line BL for inputting a signal for setting the on or off state of the transistor MP and a node SN (gate of the transistor MP). When a high-level potential is written to the node SN, the potential of BL is set higher than a normal high-level potential if the potential of INL is high. Thus, even when the potential of the node SN is dropped in accordance with transition of INL from a high level to a low level, the potential drop does not influence the operation of the transistor MP because a high potential is written in advance.

Abstract: Semiconductor device capable of preventing off-leakage of the transistor may include a pulse voltage generator configured to generate a pulse voltage, and a transistor configured to have a gate provided with the pulse voltage. The transistor is in an off state in response to the pulse voltage.

Abstract: A trimming method for a voltage generator is provided. The voltage generator generates an output voltage according to a reference voltage. The trimming method includes the following steps. Firstly, in a step (a), an initial value of a trimming code is provided. Then, in a step (b), the reference voltage is generated to the voltage generator according to the trimming code, so that the output voltage is correspondingly generated by the voltage generator. Then, in a step (c), an average voltage of the output voltage is compared with a target voltage. If the average voltage does not reach the target voltage, the trimming code is gradually changed, and the step (b) is repeatedly done. If the average voltage reaches the target voltage, the trimming code is locked.

Abstract: A microcontroller system is determining to exit a power saving mode and, in response, enable a reference current source to begin providing a reference current for a memory module. The microcontroller system determines that the reference current has reached a substantial fraction of a target reference current, and, in response to determining that the reference current has reached a substantial fraction of the target reference current, enables the memory module to begin performing one or more memory operations.

Abstract: A static random access memory system includes a static random access memory, a multiplexer, an input buffer, an output buffer, and a shifter. The input buffer writes write data stored in the input buffer to addresses of the static random access memory corresponding to a write address signal according to a write command. The output buffer reads read data of addresses of the static random access memory corresponding to a read address signal according to a read command. The multiplexer transmits the write address signal and the read address signal to the static random access memory, and generates the write command and the read command. The shifter shifts the write command to an operation clock behind the read command when the write command and the read command exist simultaneously.

Abstract: An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on the integrated circuit containing the receivers, or may be placed off chip. In one embodiment, the Vref generator comprises an adjustable-resistance voltage divider in combination with a current source. The voltage divider is referenced to I/O power supplies Vddq and Vssq, with Vref being generated at a node intervening between the adjustable resistances of the voltage divider. The current source injects a current into the Vref node and into a non-varying Thevenin equivalent resistance formed of the same resistors used in the voltage divider. So constructed, the voltage generated equals the sum of two terms: a first term comprising the slope between Vref and Vddq, and a second term comprising a Vref offset.

Abstract: Semiconductor device capable of preventing off-leakage of the transistor may include a pulse voltage generator configured to generate a pulse voltage, and a transistor configured to have a gate provided with the pulse voltage. The transistor is in an off state in response to the pulse voltage.

Abstract: A circuit includes a bipolar transistor circuit including a first node, a second node, and a plurality of bipolar transistors coupled in parallel between the first node and the second node. The circuit further includes a drive circuit configured to switch on a first group of the plurality of bipolar transistors, the first group including a first subgroup and a second subgroup and each of the first subgroup and the second subgroup including one or more of the bipolar transistors. The drive circuit is further configured to switch off the first subgroup at the end of a first time period and switch off the second subgroup at a time instant before the end of the first time period.

Abstract: A write-assisted memory includes a pre-charge assist circuit that assists the pre-charge of the power supply voltage on a power supply lead for an accessed memory cell in a bit-line-multiplexed group of memory cells subsequent to a write-assist period by coupling charge from the power supply leads for the remaining non-accessed memory cells in the bit-line-multiplexed group of memory cells.

Abstract: A system includes a switched capacitor circuit and a stabilizing circuit. The switched capacitor circuit receives a reference voltage from a reference node, transitions from a first state to a second state, and draws or supplies a switched capacitor charge from or to the reference node in response to transitioning from the first state to the second state. The second state is a function of the first state, an input of the switched capacitor circuit, or a combination of both. The stabilizing circuit stabilizes the reference voltage by supplying or drawing a stabilizing charge to or from the reference node based on the first and second states of the switched capacitor circuit.

Abstract: Disclosed are a method and a system for determining threshold voltage (Vt) variations in field effect transistors (FETs), wherein multiple field effect transistors (FETs) (e.g., at least a first FET and a second FET), which are similar in design except for having different effective channel widths, can be selected for processing. Information regarding these multiple FETs (e.g., the ratio of the different effective channel widths and other information) can be acquired and used to define the relation between a standard deviation of an uncorrelated Vt variation and a difference between a first average Vt associated with the first FET and a second average Vt associated with the second FET. The relation can, depending upon the FET layouts, be used for different purposes (e.g., for characterizing the threshold voltage mismatch between a pair of adjacent essentially identical FETs on a chip or for characterizing a width scaling relation).

Abstract: A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.

Abstract: The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters are configured back to back to latch a signal. Each inverter includes a capacitor configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages are received on control terminals of differential transistors, and a differential output signal is coupled to two back to back inverters. In one embodiment, a circuit is disabled and a voltage on a control terminal of a transistor in an inverter is set below a reference, such as a power supply, to increase the speed of the circuit.

Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

Abstract: Disclosed herein is a device that includes: a memory cell array including a plurality of memory cells, the memory cell array operates on a first internal voltage; a peripheral circuit accessing selected one or ones of the memory cells, the peripheral circuit operates on a second internal voltage; a first internal voltage generation circuit that supplies the first internal voltage to the memory cell array; and a second internal voltage generation circuit that supplies the second internal voltage to the peripheral circuit. The second internal voltage generation circuit sets the second internal voltage to a first voltage value in a first mode, and to a second voltage value that is different from the first voltage value in a second mode. The first internal voltage generation circuit sets the first internal voltage to a third voltage value in both the first and second modes.

Abstract: An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit.

Abstract: A device for detecting absence of a Plain Old Telephony Service or POTS splitter on a Digital Subscriber Line, includes a device for collecting channel transfer function data or the Digital Subscriber Line, and a device for detecting a single hole in the channel transfer function data.

Abstract: A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needs to be boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.

Abstract: The invention provides a clamp voltage generating circuit capable of generating a correct clamp voltage. The clamp voltage generating circuit includes an emulate transistor, having a drain coupled to a power source VDD, a source coupled to a node, and a gate coupled to the clamp voltage; a current setting circuit, connected between the node and ground, for setting a current flowing from the node to the ground; a regulator, inputting a feedback voltage from the node and a reference voltage, and outputting a voltage VCLMP. The current setting circuit duplicates a current of a bit line, so that the emulate transistor is similar to a charge transfer transistor.

Abstract: An internal voltage control circuit according to an embodiment may include a source power supply selection unit configured to receive a first internal power supply voltage and a second internal power supply voltage and selecting the first internal power supply voltage and the second internal power supply voltage as a source voltage in response to a test mode enable signal, a first reference voltage generation unit configured to receive the source voltage from the source power supply selection unit, and configured to generate a to first low reference voltage and a first high reference voltage. The reference voltage control circuit may also include a second reference voltage generation unit configured to receive the first internal power supply voltage and configured to generate a second low reference voltage and a second high reference voltage.

Abstract: Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.

Abstract: Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate transistor in a non-conductive state is measured by periodically clocking a counter following initiation of a read cycle; a latch stores the counter contents upon the cell under test making a transition due to leakage of the floating-gate transistor. Logic for testing a group of cells in parallel is disclosed. In some embodiments, the read margin of a cell in which the floating-gate transistor is set to a conductive state is measured by repeatedly reading the cell, with the output developing a voltage corresponding to the duty cycle of the output of the read circuit.

Abstract: An SRAM macro operates in a normal operation mode in which a plurality of memory-cell array blocks are accessible and in a low power mode in which bit lines in the memory-cell array blocks are left floating. When the SRAM macro returns from the low power mode to the normal operation mode, the bit lines in only memory-cell array blocks to be accessed among the plurality of memory-cell array blocks are precharged in sequence. This allows the peak of precharging current flowing into the SRAM macro to be dispersed.

Abstract: An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry.

Abstract: Some embodiments include apparatuses and methods having first conductive lines, second conductive lines, a memory array including memory cells, each of the memory cells coupled between one of the first conductive lines and one of the second conductive lines. At least one of such apparatuses and methods can include a module configured to cause a first current from a first current source and a second current from a second current source to flow through a selected memory cell among the memory cells during an operation of storing information in the selected memory cell. Other embodiments including additional apparatuses and methods are described.

Abstract: The present invention relates to a voltage regulator and to a method of operating a voltage regulator that is operable in a reset mode and in a sampling mode. The voltage regulator comprises a capacitive voltage divider having a first capacitor and a second capacitor in series with the first capacitor, wherein the capacitive voltage divider is connectable to an output of a voltage supply to activate the sampling mode, a comparator having an output connected to an input of the voltage supply, the comparator further having a first input connected to a sampling node arranged between the first capacitor and the second capacitor and the comparator having a second input connected to a reference voltage, wherein the sampling node is connectable to the reference voltage for activating the reset mode.

Abstract: To provide a semiconductor system including a plurality of core chips and an interface chip that controls the core chips. Each of the core chips includes an internal voltage generating circuit. The interface chip includes an unused chip information holding circuit that stores therein unused chip information of the core chips. The core chips respectively receive the unused chip information from the unused chip information holding circuit. When the unused chip information indicates an unused state, the internal voltage generating circuits are inactivated, and when the unused chip information indicates a used state, the internal voltage generating circuits are activated. With this configuration, unnecessary power consumption by the unused chips is reduced.

Abstract: A fuse circuit includes a data line, a plurality of fuse cells selectively programmed and electrically connected with the data line in response to respective selection signals, a dummy fuse cell electrically connected with the data line in response to a test signal, and a sense amplifier configured to sense a data of the data line. The fuse circuit includes a plurality of fuses, reduces the area thereof, and easily detects whether a sense amplifier operates properly or not in the fuse circuit.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.

Abstract: Devices, methods, and circuits for row driver architectures that can improve an existing row driver circuit including a boosting capacitor and a level shifter circuit. For example, the improvement can include a decoupling inverter that decouples the level shifter from the boosting capacitor, which can reduce the time for the row driver to turn on and drive appropriate voltages to the matrix array.

Abstract: A nonvolatile memory device including a memory cell arranged at a region where a word line and a bit line cross each other; a control signal generator configured to be enabled while the nonvolatile memory device operates in a test mode, and generate control signals which are not provided from an external device, based on a reference signal provided from the external device; and a control logic configured to control an operation for the memory cell according to the generated control signals.

Abstract: An electronic system, a reduced-noise reference voltage platform for a voltage converter device, and a method of manufacture of a reduced-noise reference voltage platform for a voltage converter device are disclosed. For example, the reduced-noise reference voltage (e.g., ground) platform includes a first conductor unit, a second conductor unit, and an insulator unit interposed between a first surface of the first conductor unit and a first surface of the second conductor unit. The reduced-noise reference voltage platform also includes a phase terminal connected to the first conductor unit, and a reference voltage (e.g., ground) terminal connected to the second conductor unit, wherein a second surface of the second conductor unit forms a platform coupled to the reference voltage (e.g., ground).

Abstract: A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element.

Abstract: A semiconductor memory apparatus includes a sense amplifier driving control unit configured to be applied with first and second driving voltages, and generate first to third sense amplifier driving signals in response to a mat enable signal, a sense amplifier enable signal and a power-up signal; a sense amplifier driving unit configured to, in response to the first to third sense amplifier driving signals, connect first and second sense amplifier driving nodes to cause the first and second sense amplifier driving nodes to have substantially the same voltage level, or disconnect the first and second sense amplifier driving nodes to apply first and second sense amplifier driving voltages to the first and second sense amplifier driving nodes; and a sense amplifier configured to be applied with the first and second sense amplifier driving voltages, and sense and amplify a voltage difference of a bit line and a bit line bar.

Abstract: An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.

Abstract: A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal voltage line with a voltage of the power line of the bit line sense amplification unit in a discharge driving period.

Abstract: A semiconductor memory device includes a bulk voltage generation circuit configured to interrupt driving of a bulk voltage in response to an exit signal which is generated in synchronization with a time at which a power-down mode is ended, and discharge charges of a first node from which the bulk voltage is outputted, in response to the exit signal; and an internal circuit including a MOS transistor which is supplied with the bulk voltage.

Abstract: A data transmission circuit includes: a driving voltage generation unit configured to generate a driving voltage having a lower level than an external driving voltage; a switch unit configured to transmit the driving voltage when any one of a write enable signal and a read enable signal is enabled; and a data transmission unit configured to be driven by receiving the driving voltage, transmit a signal of a DQ pad as data in response to the write enable signal, and transmit the data to the DQ pad in response to the read enable signal.