Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.

Abstract: A memory device is provided and includes multiple memory cells, multiple reference cells, and multiple sense amplifiers. The memory cells are coupled to first inputs of the sense amplifiers, respectively. The reference cells are coupled to second inputs of the sense amplifiers, respectively. The reference cells are coupled to each other.

Abstract: In a method of writing data in a memory device, a plurality of duplicated bit rows is generated by performing a first duplication operation in which a plurality of bits included in write data are copied by units of bits. A plurality of duplicated bit groups is generated by performing a second duplication operation in which the plurality of duplicated bit rows is copied by units of rows. The plurality of duplicated bit groups is stored into a plurality of memory regions included in the memory device, respectively. Each of the plurality of memory regions is a region that is simultaneously sensed during a data read operation.

Abstract: A technique relates probing a pass gate transistor in a static random access memory (SRAM) circuit. A gate probe is connected to a gate metal layer of the SRAM circuit, the gate metal layer being coupled to a gate of the pass gate transistor. A source probe is connected to a source metal layer of the SRAM circuit, the source metal layer being coupled to a source of the pass gate transistor. A drain probe is connected to a drain metal layer of the SRAM circuit, the drain metal layer being coupled to a drain of the pass gate transistor, the SRAM circuit comprising other transistors along with the pass gate transistor. The other transistors are free from connections for the probing so as not to cause the other transistors to have an unwanted effect on the pass gate transistor being probed.

Abstract: A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.

Abstract: A semiconductor device includes a forcing line extending in a first direction over a through-electrode, and electrically coupled to the through-electrode; a first monitoring line formed separate from the forcing line by a first interval in a second direction, and extended in the first direction; a second monitoring line formed separate from the forcing line by a second interval in an opposite direction to the second direction, and extended in the first direction; and a selection circuit suitable for outputting a detection signal by selecting any one of a plurality of voltage levels of the first and second monitoring lines according to a monitoring signal.

Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as isolation transistors and at least one precharge transistor, that are used to provide threshold voltage compensation.

Abstract: Provided herein may be a memory controller and a method of operating the memory controller. The memory controller may control a memory device that stores data, and may include a bit counter configured to generate a count value by counting any one of bits in a programmed state and an erased state contained in the data, a flash translation layer configured to generate page information indicating an address of the data stored in the memory device, an additional data generator configured to generate judgment data for determining whether the data has changed, based on the count value and the page information, a comparator configured to generate comparison information by comparing the judgment data with detection data generated based on data read from the memory device, and a read data controller configured to perform an operation of correcting an error in the read data based on the comparison information.

Abstract: A memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line, and a second bias circuit inputting a second bias voltage to a selected bit line, a first switch element connected to the selected word line, and a second switch element connected between the first switch element and the first bias circuit; and a control logic configured to control the first and second switch elements, when a predetermined delay time elapses after the second bias voltage is input to the selected bit line. The control logic turns off the first switch element while the second switch element is turned on.

Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.

Abstract: A fingerprint and image sensor includes a plurality of data lines, a plurality of scan lines, to which a plurality of scan signals is transferred, a plurality of reset scan lines, to which a plurality of reset scan signals is transferred, and a sensor panel, which is reset by a reset voltage, which is synchronized to a corresponding reset scan signal and is transferred, generates a pixel voltage according to light supplied during an exposure period, and includes a plurality of sensor pixels, which is synchronized to a corresponding scan signal and transfers the pixel voltage to a corresponding data line, and the exposure period may be a period from a time point, at which the corresponding reset scan signal is changed to an off-level, to a time point, at which the corresponding scan signal is changed to an on-level.

Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.

Abstract: A dynamic random access memory including a memory cell array and a memory controller is provided. The memory cell array includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. The memory controller is coupled to the memory cells via the bit lines and the word lines. The memory controller is configured to perform a self-refresh operation on the memory cell array during a self-refresh period. Each of the bit lines includes a switch element. The memory controller controls a part of the switch elements to be conducted and a part of the switch elements not to be conducted during the self-refresh period.

Abstract: A semiconductor device is disclosed, which is configured to perform a test using various conditions during a test mode. The semiconductor device includes a voltage generation circuit configured to output 2n (n is an integer of n?2) bit-line precharge voltages through different power-supply lines, based on a mode control signal, and a sense amplifier configured to receive the bit-line precharge voltages from the voltage generation circuit, and supply the 2n bit-line precharge voltages to corresponding bit lines in units of 2n successive bit-lines within the same cell array.

Abstract: A semiconductor device includes a sensing circuit. The sensing circuit includes a sense amplifier configured to sense and amplify data applied to each of a sensing line and a reference line. The sensing circuit further includes a first isolation circuit configured to selectively control a connection between a matching line and the sensing line in response to an isolation signal. The sensing circuit also includes a second isolation circuit configured to selectively control a connection between the reference line and a bit line in response to the isolation signal. The sensing circuit additionally includes an inverter coupled between the sensing line and the bit line.

Abstract: A physical unclonable function (PUF) array includes a plurality of PUF transistor cells each of which includes at least one inverter. An input and an output of the at least one inverter are shorted to a first reference node. There is adjustment circuitry for adjusting a reference voltage of the first reference node, and measurement circuitry for measuring a trip point of the at least one inverter. If the trip point is close to the reference voltage then bits of the at least one inverter are defined as unstable.

Abstract: There is provided a memory unit (100). The memory unit comprises a plurality of memory cells (110), each memory cell of the plurality of memory cells being operatively connected to data input and output circuitry by a pair of bit lines (130a, 130b), a pre-charge circuit (150) configured to provide a voltage for charging the bit lines, and a multiplexer circuit. The multiplayer circuit (140) comprises, for each bit line, an associated NMOS (142a, 142b) device that is configured to selectively connect the bit line (130a, 130b) to the data input and output circuitry and to the pre-charge circuit (150) when activated by a corresponding bit line selection signal, and a multiplex controller (144) that is configured to be able to select each pair of bit lines by activating the associated NMOS devices (142a, 142b) using the corresponding bit lines selection signals.

Abstract: A memory circuit including: memory cells, each including a storage cell transistor; a first tracking bit line; and a tracking circuit, electrically coupled between a first tracking word line and a reference voltage node, including a first set of first tracking cells, each first tracking cell including a first cell transistor having a same transistor configuration as each storage cell transistor; and wherein: a driving capacity of the storage cell transistors of the memory cells has a storage cell statistical distribution that exhibits a weak bit current value; a driving capacity of the first cell transistors of the first set of tracking cells has a first tracking cell statistical distribution that exhibits a first strong bit current value; and a first quantity of the first tracking cells is sufficient to cause the first strong bit current value to be equal to or less than the weak bit current value.

Abstract: Integrated circuits with volatile random-access memory cells are provided. A memory cell may be coupled to write bit lines and a read bit line. The write bit line may not be coupled to any precharge circuitry. The read bit line may only be precharged during memory access operations. In one suitable arrangement, the read bit line may be precharge immediately after an address decoding operation and before an evaluation phase. In another suitable arrangement, the read bit line may be precharged after an addressing decoding operation and in parallel with the evaluation phase. In either arrangement, a substantial amount of leakage and active power can be reduced.

Abstract: A bit line power supply apparatus including a bit line high voltage generator is provided. The bit line high voltage generator includes a first voltage generation circuit and a second voltage generation circuit. The first voltage generation circuit includes a first sensor and a first linear voltage regulator. The first sensor compares a first reference voltage with a bit line high voltage to generate a first sensing voltage according to a first control signal. The first linear regulator generates the bit line high voltage according the first sensing voltage. The second voltage generation circuit includes a second sensor and a switching voltage regulator. The second sensor compares the first reference voltage with the bit line high voltage to generate a second sensing voltage according to a second control signal. The switching regulator generates the bit line high voltage according the second sensing voltage.

Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.

Abstract: An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. The page table walk can include using a controller coupled to the array. The controller can be configured to operate the sensing circuitry to determine a physical address of a portion of data by accessing the page table in the array of memory cells. The controller can be configured to operate the sensing circuitry to cause storing of the portion of data in a buffer.

Abstract: The present application provides a NAND flash memory and a method for indicating program status of wordline in a NAND flash memory, the NAND flash memory comprises: a wordline including a plurality of columns, the columns include NOP columns, which are used to store NOP bytes, one of the NOP bytes is programmed after the wordline is programmed for one time. The method includes: performing program operation to a wordline; and after the wordline is programmed for one time, programming one of NOP bytes; if all the NOP bytes are programmed, outputting a NOP status. The present application could effectively prevent the error occurs due to over-time programming the same wordline.

Abstract: Various embodiments of the invention allow to dynamically transition between clock-driven and even-driven circuit elements to enable automatic multi-mode operation to enable low-power and high-throughput applications. In certain embodiments, dynamic transitioning is accomplished through a mode control unit that evaluates input data from a number of sources to determine whether to initiate a transition. Certain embodiments take advantage of dynamic transitioning to allow for energy harvesting in a data gathering phase by switching to high power communication phase as needed. The energy harvesting scheme is particularly suited for battery-operated applications that benefit from a reduction in overall power consumption.

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.

Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might include an array of memory cells. An example apparatus might also include a plurality of sensing components coupled to the array and comprising a first group of sensing components coupled to a controller via a first number of control lines and a second group of sensing components coupled to the controller via a second number of control lines wherein the controller is configured to activate at least one of the first number of control lines and the second number of control lines.

Abstract: Systems, apparatuses and methods may provide for detecting a read-write condition in which a read operation from a location in magnetoresistive memory such as spin transfer torque (STT) memory is to be followed by a write operation to the location. Additionally, a current level associated with the read operation may be increased, wherein the read operation is conducted from the location at the increased current level. In one example, the increased current level causes a reset of all bits in the location.

Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.

Abstract: A write assist circuit includes a write detection circuit, a write detection-aware write driver and a write condition recovery circuit. The write detection circuit receives a detected result signal and a write data, and generates a write detect control signal and generating a selecting signal according to the detection result signal and the write data. The write detection-aware write driver receives the write detect control signal and operates a write detection operation on a selected memory cell according to the write detect control signal, and decides whether to provide a negative voltage to one of a bit line and an inverted bit line of the selected memory cell or not according to the selecting signal.

Abstract: To notify a residual life of a replaceable part at appropriate time on image quality required by the user. An image forming apparatus including: a replaceable part used for image formation; an output unit configured to output information indicating that a usage amount has reached a threshold; an input unit configured to input information; and a control unit configured to change the threshold in accordance with information about image quality input by the input unit.

Abstract: A semiconductor device includes a memory array having a plurality of complementary cells, each including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, and a control circuit for initializing the complementary cells.

Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Abstract: Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.

Abstract: Apparatuses and methods are described herein for limiting current in threshold switching memories. In an example, an apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits.

Abstract: Systems, apparatuses and methods may provide for detecting a read-write condition in which a read operation from a location in magnetoresistive memory such as spin transfer torque (STT) memory is to be followed by a write operation to the location. Additionally, a current level associated with the read operation may be increased, wherein the read operation is conducted from the location at the increased current level. In one example, the increased current level causes a reset of all bits in the location.

Abstract: A memory device may include: first to Nth cell blocks; first to (N?1)th bit line sense amplifiers, of which a Kth bit line sense amplifier amplifies a potential difference between a bit line of a Kth cell block and a bit line of a (K+1)th cell block; one or more first outermost bit line sense amplifiers suitable for amplifying a potential difference between a first node and a bit line of the first cell block, wherein drivability for driving the first node is different from drivability for driving the bit line of the first cell block; and one or more second outermost bit line sense amplifiers suitable for amplifying a potential difference between a second node and a bit line of the Nth cell block, wherein drivability for driving the second node is different from drivability for driving the bit line of the Nth cell block.

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit comprising one or more columns and a date line and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns includes a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and second variable resistance elements; a bit line and a source line connected to the first variable resistance element; connected to the other end of the first variable resistance element; a bit line bar and a source line bar connected to the second variable resistance element; and a driving block configured to latch data of the data line and the data line bar.

Abstract: Among other things, techniques and systems are provided for activating a memory cell of a memory arrangement in preparation for at least one of a read operation or write operation. The memory arrangement comprises a word-line driver comprising at least a first input terminal and a second input terminal. The first input terminal is operably coupled to a first decoder and the second input terminal is operably coupled to a second decoder. When the word-line driver senses a first voltage at the first input terminal and a second voltage at the second input terminal, the word-line driver outputs a gate voltage signal which activates the memory cell.

Abstract: A memory device may include a cell array including a plurality of memory cells and a bit line coupled to the plurality of memory cells; a sense amplifier suitable for amplifying a voltage difference between a first line and a second line; and a separation unit suitable for electrically coupling the bit line and the first line, and electrically separating the bit line and the first line during an initial period of an operation of the sense amplifier.

Abstract: A multi-state static RAM cell includes N NOR gates. Each NOR gate has N?1 inputs and one output. The output of each NOR gate is coupled to a different bit line. Each NOR gate has its inputs connected to the outputs of each of the other NOR gates.

Abstract: Embodiments include a method comprising: receiving a first voltage; and while testing a memory cell: modifying the first voltage to generate a second voltage that is different from the first voltage; and performing a first read operation on the memory cell, based on applying (i) the second voltage to an array of transistors of the memory cell and (ii) the first voltage to the memory cell.

Abstract: There are provided: a first buffer circuit which includes buffers being circuits to be measured connected in series, whose output and input are connected to a first input terminal and a second output terminal of a control circuit, respectively; a second buffer circuit which includes buffers being circuits to be measured connected in series whose number is the same as a number of the buffers included in the first buffer circuit, whose output and input are connected to a second input terminal and a first output terminal of the control circuit, respectively; and the control circuit which makes the entire circuit is a negative logic when a first operation is set, and simultaneously outputs signals with different logics from the output terminals at a time of a start of an oscillation operation and makes the entire circuit is a positive logic when a second operation is set.

Abstract: In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. First, memory cells are read to obtain verification bits. A first hard bit mode decoding procedure is performed according to the verification bits and whether the first hard bit mode decoding procedure generates a first valid codeword is determined by a first correcting circuit. If the first valid codeword is generated, the first valid codeword is outputted. If the first valid codeword is not generated, a second hard bit mode decoding procedure is performed, and whether the second hard bit mode decoding procedure generates a second valid codeword is determined by a second correcting circuit. A precision of the first correcting circuit is less than a precision of the second correcting circuit. Accordingly, the speed of decoding is increased.