For Complementary Information Patents (Class 365/190)
  • Patent number: 10902905
    Abstract: A memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line, and a second bias circuit inputting a second bias voltage to a selected bit line, a first switch element connected to the selected word line, and a second switch element connected between the first switch element and the first bias circuit; and a control logic configured to control the first and second switch elements, when a predetermined delay time elapses after the second bias voltage is input to the selected bit line. The control logic turns off the first switch element while the second switch element is turned on.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: January 26, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Sung Cho, Venkataramana Gangasani, Hee Won Kim, Tae Hui Na
  • Patent number: 10847217
    Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
  • Patent number: 10755070
    Abstract: A fingerprint and image sensor includes a plurality of data lines, a plurality of scan lines, to which a plurality of scan signals is transferred, a plurality of reset scan lines, to which a plurality of reset scan signals is transferred, and a sensor panel, which is reset by a reset voltage, which is synchronized to a corresponding reset scan signal and is transferred, generates a pixel voltage according to light supplied during an exposure period, and includes a plurality of sensor pixels, which is synchronized to a corresponding scan signal and transfers the pixel voltage to a corresponding data line, and the exposure period may be a period from a time point, at which the corresponding reset scan signal is changed to an off-level, to a time point, at which the corresponding scan signal is changed to an on-level.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: August 25, 2020
    Assignee: SILICON DISPLAY TECHNOLOGY
    Inventors: Kijoong Kim, Taehan Go, Jin Hyeong Yu, Ji Ho Hur, Jong Woo Jin, Young Man Park, Youn Duck Nam
  • Patent number: 10748583
    Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 18, 2020
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Fakhruddin Ali Bohra, Shri Sagar Dwivedi
  • Patent number: 10714164
    Abstract: A dynamic random access memory including a memory cell array and a memory controller is provided. The memory cell array includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. The memory controller is coupled to the memory cells via the bit lines and the word lines. The memory controller is configured to perform a self-refresh operation on the memory cell array during a self-refresh period. Each of the bit lines includes a switch element. The memory controller controls a part of the switch elements to be conducted and a part of the switch elements not to be conducted during the self-refresh period.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: July 14, 2020
    Assignee: Windbond Electronics Corp.
    Inventor: Che-Min Lin
  • Patent number: 10692586
    Abstract: A semiconductor device is disclosed, which is configured to perform a test using various conditions during a test mode. The semiconductor device includes a voltage generation circuit configured to output 2n (n is an integer of n?2) bit-line precharge voltages through different power-supply lines, based on a mode control signal, and a sense amplifier configured to receive the bit-line precharge voltages from the voltage generation circuit, and supply the 2n bit-line precharge voltages to corresponding bit lines in units of 2n successive bit-lines within the same cell array.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 23, 2020
    Assignee: SK hynix Inc.
    Inventors: Jae Hwan Seo, Sung Soo Chi
  • Patent number: 10643687
    Abstract: A semiconductor device includes a sensing circuit. The sensing circuit includes a sense amplifier configured to sense and amplify data applied to each of a sensing line and a reference line. The sensing circuit further includes a first isolation circuit configured to selectively control a connection between a matching line and the sensing line in response to an isolation signal. The sensing circuit also includes a second isolation circuit configured to selectively control a connection between the reference line and a bit line in response to the isolation signal. The sensing circuit additionally includes an inverter coupled between the sensing line and the bit line.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventor: One Gyun Na
  • Patent number: 10630493
    Abstract: A physical unclonable function (PUF) array includes a plurality of PUF transistor cells each of which includes at least one inverter. An input and an output of the at least one inverter are shorted to a first reference node. There is adjustment circuitry for adjusting a reference voltage of the first reference node, and measurement circuitry for measuring a trip point of the at least one inverter. If the trip point is close to the reference voltage then bits of the at least one inverter are defined as unstable.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 21, 2020
    Assignee: Birad—Research & Development Company Ltd.
    Inventors: Joseph Shor, Roi Levi, Yoav Weizman
  • Patent number: 10586589
    Abstract: There is provided a memory unit (100). The memory unit comprises a plurality of memory cells (110), each memory cell of the plurality of memory cells being operatively connected to data input and output circuitry by a pair of bit lines (130a, 130b), a pre-charge circuit (150) configured to provide a voltage for charging the bit lines, and a multiplexer circuit. The multiplayer circuit (140) comprises, for each bit line, an associated NMOS (142a, 142b) device that is configured to selectively connect the bit line (130a, 130b) to the data input and output circuitry and to the pre-charge circuit (150) when activated by a corresponding bit line selection signal, and a multiplex controller (144) that is configured to be able to select each pair of bit lines by activating the associated NMOS devices (142a, 142b) using the corresponding bit lines selection signals.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: March 10, 2020
    Assignee: SURECORE LIMITED
    Inventor: Andrew Pickering
  • Patent number: 10553265
    Abstract: A memory circuit including: memory cells, each including a storage cell transistor; a first tracking bit line; and a tracking circuit, electrically coupled between a first tracking word line and a reference voltage node, including a first set of first tracking cells, each first tracking cell including a first cell transistor having a same transistor configuration as each storage cell transistor; and wherein: a driving capacity of the storage cell transistors of the memory cells has a storage cell statistical distribution that exhibits a weak bit current value; a driving capacity of the first cell transistors of the first set of tracking cells has a first tracking cell statistical distribution that exhibits a first strong bit current value; and a first quantity of the first tracking cells is sufficient to cause the first strong bit current value to be equal to or less than the weak bit current value.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuoyuan (Peter) Hsu, Jacklyn Chang
  • Patent number: 10431269
    Abstract: Integrated circuits with volatile random-access memory cells are provided. A memory cell may be coupled to write bit lines and a read bit line. The write bit line may not be coupled to any precharge circuitry. The read bit line may only be precharged during memory access operations. In one suitable arrangement, the read bit line may be precharge immediately after an address decoding operation and before an evaluation phase. In another suitable arrangement, the read bit line may be precharged after an addressing decoding operation and in parallel with the evaluation phase. In either arrangement, a substantial amount of leakage and active power can be reduced.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: October 1, 2019
    Assignee: Altera Corporation
    Inventors: Rajiv Kumar, Wei Yee Koay, Kuan Cheng Tang
  • Patent number: 10418075
    Abstract: A bit line power supply apparatus including a bit line high voltage generator is provided. The bit line high voltage generator includes a first voltage generation circuit and a second voltage generation circuit. The first voltage generation circuit includes a first sensor and a first linear voltage regulator. The first sensor compares a first reference voltage with a bit line high voltage to generate a first sensing voltage according to a first control signal. The first linear regulator generates the bit line high voltage according the first sensing voltage. The second voltage generation circuit includes a second sensor and a switching voltage regulator. The second sensor compares the first reference voltage with the bit line high voltage to generate a second sensing voltage according to a second control signal. The switching regulator generates the bit line high voltage according the second sensing voltage.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 17, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Kaoru Mori
  • Patent number: 10410715
    Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: September 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
  • Patent number: 10402340
    Abstract: An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. The page table walk can include using a controller coupled to the array. The controller can be configured to operate the sensing circuitry to determine a physical address of a portion of data by accessing the page table in the array of memory cells. The controller can be configured to operate the sensing circuitry to cause storing of the portion of data in a buffer.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Perry V. Lea
  • Patent number: 10304537
    Abstract: The present application provides a NAND flash memory and a method for indicating program status of wordline in a NAND flash memory, the NAND flash memory comprises: a wordline including a plurality of columns, the columns include NOP columns, which are used to store NOP bytes, one of the NOP bytes is programmed after the wordline is programmed for one time. The method includes: performing program operation to a wordline; and after the wordline is programmed for one time, programming one of NOP bytes; if all the NOP bytes are programmed, outputting a NOP status. The present application could effectively prevent the error occurs due to over-time programming the same wordline.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 28, 2019
    Assignee: GIGADEVICE SEMICONDUCTOR (BEIJING) INC.
    Inventor: Minyi Chen
  • Patent number: 10289186
    Abstract: Various embodiments of the invention allow to dynamically transition between clock-driven and even-driven circuit elements to enable automatic multi-mode operation to enable low-power and high-throughput applications. In certain embodiments, dynamic transitioning is accomplished through a mode control unit that evaluates input data from a number of sources to determine whether to initiate a transition. Certain embodiments take advantage of dynamic transitioning to allow for energy harvesting in a data gathering phase by switching to high power communication phase as needed. The energy harvesting scheme is particularly suited for battery-operated applications that benefit from a reduction in overall power consumption.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: May 14, 2019
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Hung Thanh Nguyen, Nancy Kow Iida, Edward Tangkwai Ma, Robert Michael Muchsel, Gary Vernon Zanders
  • Patent number: 10199122
    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: February 5, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Jon Slaughter, Dimitri Houssameddine, Syed M. Alam
  • Patent number: 10049722
    Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 14, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Atsuo Koshizuka
  • Patent number: 10037794
    Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: July 31, 2018
    Assignee: STMicroelectronics International N.V.
    Inventors: Dhori Kedar Janardan, Abhishek Pathak, Shishir Kumar
  • Patent number: 9928901
    Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: March 27, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuichiro Ishii
  • Patent number: 9922701
    Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
  • Patent number: 9905276
    Abstract: Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might include an array of memory cells. An example apparatus might also include a plurality of sensing components coupled to the array and comprising a first group of sensing components coupled to a controller via a first number of control lines and a second group of sensing components coupled to the controller via a second number of control lines wherein the controller is configured to activate at least one of the first number of control lines and the second number of control lines.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: February 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jeremiah J. Willcock, Glen E. Hush
  • Patent number: 9892775
    Abstract: Systems, apparatuses and methods may provide for detecting a read-write condition in which a read operation from a location in magnetoresistive memory such as spin transfer torque (STT) memory is to be followed by a write operation to the location. Additionally, a current level associated with the read operation may be increased, wherein the read operation is conducted from the location at the increased current level. In one example, the increased current level causes a reset of all bits in the location.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventor: Helia A. Naeimi
  • Patent number: 9842631
    Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: December 12, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Ge Yang, Hwong-Kwo Lin, Xi Zhang, Jiani Yu, Haiyan Gong
  • Patent number: 9779802
    Abstract: A write assist circuit includes a write detection circuit, a write detection-aware write driver and a write condition recovery circuit. The write detection circuit receives a detected result signal and a write data, and generates a write detect control signal and generating a selecting signal according to the detection result signal and the write data. The write detection-aware write driver receives the write detect control signal and operates a write detection operation on a selected memory cell according to the write detect control signal, and decides whether to provide a negative voltage to one of a bit line and an inverted bit line of the selected memory cell or not according to the selecting signal.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 3, 2017
    Assignee: National Tsing Hua University
    Inventors: Meng-Fan Chang, Yi-Ju Chen
  • Patent number: 9772591
    Abstract: To notify a residual life of a replaceable part at appropriate time on image quality required by the user. An image forming apparatus including: a replaceable part used for image formation; an output unit configured to output information indicating that a usage amount has reached a threshold; an input unit configured to input information; and a control unit configured to change the threshold in accordance with information about image quality input by the input unit.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: September 26, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoru Taniguchi, Wataru Uchida, Hiroyuki Yamazaki, Toshifumi Kitamura
  • Patent number: 9747990
    Abstract: A semiconductor device includes a memory array having a plurality of complementary cells, each including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, and a control circuit for initializing the complementary cells.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 29, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Masamichi Fujito, Hiroshi Yoshida, Takanori Takahashi, Yasuhiko Taito
  • Patent number: 9711223
    Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: July 18, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Roberto Gastaldi
  • Patent number: 9647476
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: May 9, 2017
    Assignee: NAVITAS SEMICONDUCTOR INC.
    Inventors: Daniel M. Kinzer, Santosh Sharma, Ju Jason Zhang
  • Patent number: 9627052
    Abstract: Apparatuses and methods are described herein for limiting current in threshold switching memories. In an example, an apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: April 18, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Hari Giduturi, Mingdong Cui
  • Patent number: 9627016
    Abstract: Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 18, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Vineet Agrawal, Roger Bettman, Samuel Leshner
  • Patent number: 9589620
    Abstract: Systems, apparatuses and methods may provide for detecting a read-write condition in which a read operation from a location in magnetoresistive memory such as spin transfer torque (STT) memory is to be followed by a write operation to the location. Additionally, a current level associated with the read operation may be increased, wherein the read operation is conducted from the location at the increased current level. In one example, the increased current level causes a reset of all bits in the location.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: March 7, 2017
    Assignee: Intel Corporation
    Inventor: Helia Naeimi
  • Patent number: 9570150
    Abstract: A memory device may include: first to Nth cell blocks; first to (N?1)th bit line sense amplifiers, of which a Kth bit line sense amplifier amplifies a potential difference between a bit line of a Kth cell block and a bit line of a (K+1)th cell block; one or more first outermost bit line sense amplifiers suitable for amplifying a potential difference between a first node and a bit line of the first cell block, wherein drivability for driving the first node is different from drivability for driving the bit line of the first cell block; and one or more second outermost bit line sense amplifiers suitable for amplifying a potential difference between a second node and a bit line of the Nth cell block, wherein drivability for driving the second node is different from drivability for driving the bit line of the Nth cell block.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: February 14, 2017
    Assignee: SK Hynix Inc.
    Inventor: Dong-Keun Kim
  • Patent number: 9564198
    Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: February 7, 2017
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier
  • Patent number: 9543008
    Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit comprising one or more columns and a date line and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns includes a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and second variable resistance elements; a bit line and a source line connected to the first variable resistance element; connected to the other end of the first variable resistance element; a bit line bar and a source line bar connected to the second variable resistance element; and a driving block configured to latch data of the data line and the data line bar.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 10, 2017
    Assignee: SK hynix Inc.
    Inventor: Dong-Keun Kim
  • Patent number: 9536598
    Abstract: Among other things, techniques and systems are provided for activating a memory cell of a memory arrangement in preparation for at least one of a read operation or write operation. The memory arrangement comprises a word-line driver comprising at least a first input terminal and a second input terminal. The first input terminal is operably coupled to a first decoder and the second input terminal is operably coupled to a second decoder. When the word-line driver senses a first voltage at the first input terminal and a second voltage at the second input terminal, the word-line driver outputs a gate voltage signal which activates the memory cell.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limi
    Inventors: Wei-Cheng Wu, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 9524758
    Abstract: A memory device may include a cell array including a plurality of memory cells and a bit line coupled to the plurality of memory cells; a sense amplifier suitable for amplifying a voltage difference between a first line and a second line; and a separation unit suitable for electrically coupling the bit line and the first line, and electrically separating the bit line and the first line during an initial period of an operation of the sense amplifier.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: December 20, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hyung-Sik Won
  • Patent number: 9514804
    Abstract: A multi-state static RAM cell includes N NOR gates. Each NOR gate has N?1 inputs and one output. The output of each NOR gate is coupled to a different bit line. Each NOR gate has its inputs connected to the outputs of each of the other NOR gates.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: December 6, 2016
    Assignee: Microsemi SoC Corporation
    Inventor: Jonathan W. Greene
  • Patent number: 9424911
    Abstract: Embodiments include a method comprising: receiving a first voltage; and while testing a memory cell: modifying the first voltage to generate a second voltage that is different from the first voltage; and performing a first read operation on the memory cell, based on applying (i) the second voltage to an array of transistors of the memory cell and (ii) the first voltage to the memory cell.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: August 23, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Winston Lee, Moon-Hae Son, Peter Lee
  • Patent number: 9404964
    Abstract: There are provided: a first buffer circuit which includes buffers being circuits to be measured connected in series, whose output and input are connected to a first input terminal and a second output terminal of a control circuit, respectively; a second buffer circuit which includes buffers being circuits to be measured connected in series whose number is the same as a number of the buffers included in the first buffer circuit, whose output and input are connected to a second input terminal and a first output terminal of the control circuit, respectively; and the control circuit which makes the entire circuit is a negative logic when a first operation is set, and simultaneously outputs signals with different logics from the output terminals at a time of a start of an oscillation operation and makes the entire circuit is a positive logic when a second operation is set.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: August 2, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Tsuyoshi Sakata
  • Patent number: 9384826
    Abstract: In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: July 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Per Torstein Roine, Vinod Menezes, Mahesh Mehendale, Vamsi Gullapalli, Premkumar Seetharaman
  • Patent number: 9342404
    Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. First, memory cells are read to obtain verification bits. A first hard bit mode decoding procedure is performed according to the verification bits and whether the first hard bit mode decoding procedure generates a first valid codeword is determined by a first correcting circuit. If the first valid codeword is generated, the first valid codeword is outputted. If the first valid codeword is not generated, a second hard bit mode decoding procedure is performed, and whether the second hard bit mode decoding procedure generates a second valid codeword is determined by a second correcting circuit. A precision of the first correcting circuit is less than a precision of the second correcting circuit. Accordingly, the speed of decoding is increased.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: May 17, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chien-Fu Tseng
  • Patent number: 9336860
    Abstract: A complementary lateral bipolar SRAM device. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: May 10, 2016
    Assignee: International Business Machines Corporation
    Inventor: Tak H. Ning
  • Patent number: 9275721
    Abstract: Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tzu Chen, Bin-Hau Lo, Tsai-Hsin Lai, Pey-Huey Chen, Hau-Tai Shieh
  • Patent number: 9177619
    Abstract: A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: November 3, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 9111589
    Abstract: Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: August 18, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Rakesh Kumar Sinha, Chirag Gulati, Ritu Chaba, Sei Seung Yoon
  • Patent number: 9111594
    Abstract: A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: August 18, 2015
    Assignee: SK Hynix Inc.
    Inventor: Duk Su Chun
  • Patent number: 9094277
    Abstract: An integrated circuit device can include a radio-frequency device and a hard-wired lookup table. The radio-frequency device can have an analog input, a digital control input, and an analog output. An unadjusted transfer response of the analog output relative to the analog input and the digital control input can differ from an ideal transfer response. The hard-wired lookup table can be connected to the digital control input of the radio-frequency device to generate a modified digital control input based on a predetermined function. This can have the effect that the adjusted transfer response of the analog output relative to the analog input and the modified digital control input is closer to the ideal transfer response than the unadjusted transfer response of the analog output relative to the analog input and the digital control input. The predetermined function can be defined by metallization connections within the integrated circuit device.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 28, 2015
    Assignee: ViaSat, Inc.
    Inventor: David Self
  • Patent number: 9053776
    Abstract: A setting information storage circuit includes first decoders configured to generate first input enable signals, respectively, in response to selection codes and a first set signal, first register sets configured to correspond to the first decoders, respectively, and to receive setting data when first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and store the received setting data, a second decoders configured to generate a second input enable signals, respectively, in response to the selection codes and a second set signal, and a second register sets configured to correspond to the second decoders, respectively, and to receive the setting data when second input enable signals generated from the second decoders corresponding to the second register sets, respectively, are enabled, and store the received setting data.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: June 9, 2015
    Assignee: SK Hynix Inc.
    Inventors: Kwanweon Kim, Hyunsu Yoon, Jeongtae Hwang
  • Patent number: 9042162
    Abstract: A static random access memory (SRAM) cell includes first and second n-channel transistors, first and second p-channel transistors, first and second enable transistors, and first and second pass gates. The first n-channel transistor, the first p-channel transistor, and the first enable transistor are connected in series between first and second reference potentials. The second n-channel transistor, the second p-channel transistor, and the second enable transistor are connected in series between the first and second reference potentials. The first pass gate is configured to selectively connect a first bitline to a first node. The first node is connected to a gate of the first n-channel transistor and a gate of the first p-channel transistor. The second pass gate is configured to selectively connect a second bitline to a second node. The second node is connected to a gate of the second n-channel transistor and a gate of the second p-channel transistor.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: May 26, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Peter Lee, Winston Lee