Abstract: A memory device may be provided. The memory device may include a test data output circuit configured to compare lower data output from a lower data storage region with upper data output from an upper data storage region and make a decision. The memory device may include a data transmitter configured to output the lower data by inverting or noninverting the lower data according to the decision. The memory device may include a test control circuit generates a test control signal according to a test read signal and an address signal.

Abstract: A deferred error correction code (ECC) scheme for memory devices is disclosed. In one embodiment, a method is disclosed comprising starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.

Abstract: A method and apparatus for acquiring chirp data in a frequency modulated continuous wave (FMCW) radar system of a road vehicle. The method includes transmitting a FMCW signal comprising a plurality of ramping regions in which a frequency of the FMCW signal ramps up to a first frequency or ramps down to a second frequency. The method also includes receiving a reflected signal corresponding to the reflection of the FMCW signal from one or more physical objects. The reflected signal includes a plurality of ramping regions corresponding to the ramping regions of the transmitted FMCW signal. The method further includes sampling the reflected signal by: taking a plurality of samples in a ramping region in which the frequency of the reflected signal ramps up; and taking a plurality of samples in a ramping region in which the frequency of the reflected signal ramps down.

Abstract: The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.

Abstract: An exemplary memory includes a memory cell array configured to store a plurality of data bits each associated with a respective column plane, and an input/output circuit including a compression circuit configured to provide error data based on a comparison between a bit of the plurality of data bits received from the memory cell array and an expected value and based on a respective column plane of the memory cell array with which the bit is associated. The compression circuit is further configured to encode a column plane error code based on the error data for provision to a data terminal.

Abstract: The present technology relates to an electronic device. A method of operating a memory device having improved test performance according to the present technology includes setting a plurality of program biases corresponding to a plurality of memory dies, respectively, based on an operation speed of each of the plurality of memory dies, setting a plurality of offsets corresponding to a plurality of word line groups, respectively, based on an operation speed of each of the plurality of word line groups included in a selected block of a selected memory die among the plurality of memory dies, and detecting a defect of a target block of the selected memory die using a plurality of high voltages and a set low voltage determined based on a program bias corresponding to the selected memory die and the plurality of offsets.

Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

Abstract: According to one embodiment, a storage device includes a first memory cell; a second memory cell; and a controller configured to, in response to receiving a first command set, execute a first erase operation which is included in an erase operation of data of the first memory cell, and suspend the first erase operation, and in response to receiving a second command set, execute a read operation or a write operation of the second memory cell and subsequently resume the suspended first erase operation.

Abstract: A test mode set circuit includes: a first test mode set block suitable for setting entry into a first test mode based on a clock signal and first data outputted from a non-volatile memory during a first period of a boot-up operation; and a second test mode set block suitable for setting entry into a second test mode based on the first data and second data outputted from the non-volatile memory during a second period of the boot-up operation, or setting entry into the second test mode based on a set signal generated by a combination of a command and an address during a normal operation.

Abstract: A circuit device includes a first physical layer circuit to which a first bus with a USB standard is coupled, a second physical layer circuit to which a second bus with the USB standard is coupled, and a bus monitor circuit monitoring the first bus and the second bus, in which the first physical layer circuit includes a first disconnect detection circuit which detects device disconnect in the first bus, the bus monitor circuit includes a first test signal detection circuit which detects whether or not a test signal is output to the first bus, and when detection of the device disconnect by the first disconnect detection circuit is disabled, detection of the test signal by the first test signal detection circuit is disabled.

Abstract: A memory device includes a bank that includes first memory cells connected to a first column selection line and second memory cells connected to a second column selection line, a first column decoder that selects the first memory cells by transmitting a first column selection signal in a first direction through the first column selection line, and a second column decoder that selects the second memory cells by transmitting a second column selection signal in a second direction opposite to the first direction through the second column selection line. The first column decoder includes a first register that stores a first fail column address of the first memory cells, and a second register that stores a second fail column address of the second memory cells.

Abstract: A storage device includes a memory device configured to perform a read operation on a selected word line among a plurality of word lines, and a memory controller configured to control the memory device to: perform the read operation, perform a read retry operation on the selected word line, by changing a read voltage level, when the read operation fails, and perform an additional read retry operation on the selected word line, by changing the read voltage level and an application time of voltages related to the read operation, depending on whether the selected word line is a set word line, when the read retry operation fails.

Abstract: According to one embodiment, a semiconductor memory device includes a memory, a controller, and a sense amplifier. The memory includes a plurality of memory cells, wherein each of the memory cells can store a multi level indicating one data. The controller writes the multi level to one cell of the memory. The sense amplifier performs unary read of data from the multi level written in the one cell. The data is data in which an error of a predetermined lower significant bit is allowed. The controller reads data indicated by the multi level stored in the one cell of the memory from the sense amplifier.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.

Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

Abstract: A memory device includes: a memory cell array having a plurality of memory cells, wherein each of the plurality of memory cells includes a first port; a first control circuit disposed on a first side of the memory cell array and arranged to electrically connect to the plurality of first ports; and a second control circuit disposed on a second side of the memory cell array and arranged to electrically connect to the plurality of first ports; wherein the second side is opposite to the first side of the memory cell array.

Abstract: Apparatuses and methods for latching redundancy repair addresses at a memory are disclosed. An example apparatus includes block of memory including primary memory and a plurality of redundant memory units and repair logic. The repair logic including a plurality of repair blocks. A repair block of the plurality of repair blocks is configured to receive a set of repair address bits associated with a memory address for defective memory of the block of memory and to latch the set of repair address bits at a respective set of latches. The repair block is further configured to, in response to receipt of a memory access request corresponding to the set of repair address bits latched at the repair block, redirecting the memory access request to a redundant memory unit associated with the repair block.

Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

Abstract: A memory device includes a memory cell array, a peripheral circuit, a test mode register set, and a test circuit. The peripheral circuit stores data in the memory cell array or reads data from the memory cell array. The test mode register set stores a delay value. In response to detecting a clock select signal received from outside the memory device, the test circuit generates an asynchronous signal from a clock received from the outside based on the delay value, and controls the peripheral circuit based on the asynchronous signal.

Abstract: A semiconductor device includes a pattern data generation circuit generating pattern data, a data comparison circuit receiving read data which are outputted from cell arrays included in a core area by a read operation and comparing the read data with the pattern data to generate a fail code, and a fail flag generation circuit comparing the fail code with a set code to generate a fail flag.

Abstract: Apparatus having first and second sets of memory devices commonly connected to receive a first enable signal and a second enable signal, respectively, and a multiplexer connected to receive the first and second enable signals. The multiplexer is configured to connect the first set of memory devices to an output of the apparatus in response to the first enable signal having a first logic level, and to isolate the first set of memory devices from the output in response to the first enable signal having a second logic level different than the first logic level. The multiplexer is further configured to connect the second set of memory devices to the output in response to the second enable signal having the first logic level, and to isolate the second set of memory devices from the output in response to the second enable signal having the second logic level.

Abstract: A semiconductor device includes: a non-volatile memory including a normal region, a self-repair region and a redundancy region, each having a plurality of cells; a first boot-up control block suitable for controlling a first boot-up operation to detect defective cells of the normal region and store a defective address in a first latch unit; a self-program control block suitable for controlling a self-program operation to program the defective address stored in the first latch unit into the self-repair region; and a second boot-up control block suitable for controlling a second boot-up operation to read out data of the normal region based on an input address while reading out data of the redundancy region instead of the data of the normal region when data of the self-repair region coincides with the input address.

Abstract: The present disclosure includes apparatuses and methods for in-memory data switching networks. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array of memory cells. An input/output (I/O) line is shared as a data path for in-memory data switching associated with the array. An in-memory data switching network is selectably coupled to the respective shared I/O line. A controller is configured to couple to the in-memory data switching network and direct enablement of a switch protocol.

Abstract: A memory device and a memory peripheral circuit are provided. The memory peripheral circuit includes a redundancy column data circuit and a column selection control circuit. The redundancy column data circuit is configured to provide a redundancy test mode data signal and a column address signal. The column address signal includes a redundancy column address signal. The column selection control circuit includes a column decoder and a redundancy column decoder. The column decoder disables a bad column address of a main memory block according to the redundancy test mode data signal and the redundancy column address signal. The redundancy column decoder latches the redundancy column address signal, compares the column address signal with the latched redundancy column address to obtain a comparison result, and enables a redundancy column address of a redundancy memory block according to the comparison result.

Abstract: The present invention provides a security system, and methods useful for vehicle CAN bus communication mapping and attack originator identification, comprising: a CAN Bus Monitor, (CBM), configured to monitor the CAN bus communication comprising one or more frames, to and/or from at least one Electronic Control Unit, (ECU); a characterization module in communication with the CBM, configured to generate at least one characteristic for the monitored communication from each the ECU and at least one characteristic for each communication frame; (c) a comparator unit in communication with the characterization module, configured to compare one or more the characteristics of at least one frame against characteristics of each the ECU communication in order to detect at least one anomaly; and, (d) one or more Identification module in communication with the comparator, configured to identify at least one ECU originating an attack on the CAN bus.

Abstract: A testing method for a semiconductor memory includes determining which memory blocks are defective based on the number of defective cells in the block. The method includes determining whether the number of defective blocks exceeds a first threshold value and judging the semiconductor memory to be defective if the number of defective blocks is equal to or greater than the first threshold value. The method also includes comparing the number of defective blocks with a second threshold value equal to or less than the first threshold value and repeating the process of measuring and judging of the memory cells and memory blocks until the number of defective blocks is at least equal to the second threshold value, and then managing access to the defective blocks in a different manner from accesses to other blocks.

Abstract: A memory device includes a plurality of memory cell arrays, a plurality of data transmitters corresponding to the plurality of memory cell arrays, respectively, and suitable for transmitting data read in parallel from the corresponding memory cell arrays, and a test circuit suitable for selecting one data transmitter among the plurality of data transmitters, and sequentially outputting data transmitted in parallel from the selected data transmitter to one data input/output pad among a plurality of data input/output pads, during a test mode.

Abstract: Embodiments include a system, method, and a computer program product for notifying a technician when a repair task the technician is addressing may be negatively impacted by a nearby fault and/or if the technician is qualified to repair a nearby fault. The technician is qualified if the technician has the necessary skills, parts (e.g., materials), and/or equipment (test equipment) required to repair the nearby fault. In addition, embodiments include receiving and responding to queries from a technician to: determine whether any of the repair tasks associated with the technician's assigned tickets are futile tasks based on newly received faults or pending tickets; and determine whether the querying technician is qualified to address (e.g., repair) any newly received faults or pending tickets.

Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.

Abstract: A method includes receiving, by a host server on a public cloud including one or more physical data centers associated with one or more logical zones, a pairing request by a client device associated with a private cloud, allocating, by the host server, access to resources on the one or more physical data centers to the client device, and pairing, by the host server, the private cloud to the public cloud based on receiving an identity provider token from an identity provider.

Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.

Abstract: Provided herein is a memory device and a method of operating the memory device. The memory device may include a one or more memory blocks, one or more peripheral circuits configured to perform an erase operation and a threshold voltage distribution scan operation on a selected memory block, and a control logic configured to control the one or more peripheral circuits, and determine the selected memory block to be a normal memory block or a defective memory block based on a result of the threshold voltage distribution scan operation.

Abstract: A semiconductor switch according to an embodiment includes: a first sub-switch and a second sub-switch. A first input signal is inputted into the first sub-switch and a second input signal is inputted into the second sub-switch. The first input signal is either a first voltage or a third voltage, the second input signal is either a second voltage or a fourth voltage, the second voltage is lower than the first voltage, the third voltage is lower than the first voltage and the fourth voltage is lower than the third voltage. The second voltage is inputted into the second sub-switch when an output from the first sub-switch is outputted from the semiconductor switch, and the third voltage is inputted into the first sub-switch when an output from the second sub-switch is outputted from the semiconductor switch.

Abstract: Provided is a semiconductor device including a regulator that generates a first voltage and applying the first voltage to a first line; an external terminal that is connected to the first line and externally connects an external component; and a test circuit that inspects a connection state of the external component. The test circuit includes a test discharge execution unit that is configured, upon receiving a test start signal, to stop the operation of the regulator and discharge the external component by connecting the first line to a predetermined potential; and a discharge duration measurement unit that measures a time required from the reception of the test start signal to a drop of the voltage of the first line below a predetermined second voltage, as a discharge duration of the component, and generate discharge duration information about the discharge duration.

Abstract: A method and apparatus for memory built-in self-test (MBIST) may be configured to load a testing program from an MBIST controller, execute the testing program, and determine and write pass/fail results to a read-out register. For example, in various embodiments, the testing program may comprise one or more write operations that are configured to change data stored in a plurality of memory bitcells from a first value to a second value while a byte enable signal is asserted in order to test stability associated with a memory bitcell, create DC and AC noise due to byte enable mode stress, check at-speed byte enable mode timing, and execute a self-checking algorithm that may be designed to verify whether data is received at a data input (Din) pin. Any memory bitcells storing a value different from an expected value after performing the write operation(s) may be identified as having failed the MBIST.

Abstract: Techniques change a type of a storage system. The techniques involve: determining, from a resource pool associated with the storage system, a set of used disks utilized by one stripe of the storage system and a set of spare disks unutilized by the stripe; determining a neighboring relationship between spare disks in the set of spare disks and used disks in the set of used disks, the neighboring relationship indicating a number of adjacencies between the spare disks and the used disks in a period of history time; selecting, based on the neighboring relationship, one spare disk from the set of spare disks as an expanded disk of the stripe; and updating the stripe of the storage system using extents of the expanded disk. Accordingly, the type of the storage system may be changed based on the existing resources to improve reliability and operating efficiency.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reclaiming one or more portions of storage resources in a computer system serving one or more virtual computing instances, where the storage resources in the computer system are organized in clusters of storage blocks. In one aspect, a method includes maintaining a respective block tracking value for each storage block that indicates whether a call to reclaim the storage block is outstanding; determining, from the block tracking values, a respective cluster priority value for each of the clusters based on a count of storage blocks in the respective cluster for which a call to reclaim is outstanding; and reclaiming a first portion of storage resources in the computer system in accordance with the cluster priority values.

Abstract: The present disclosure relates to a memory device including a BIST circuit and an operating method thereof. The memory device includes a comparison circuit comparing test pattern data with sensing data to generate a comparison signal, a status information generating circuit generating a fail mask signal by marking data in which a failure occurs in the sensing data in response to the comparison signal, a column address generating circuit generating column addresses sequentially increasing in response to an input/output strobe signal, a latch enable signal generating circuit generating a latch enable signal in response to the fail mask signal, and an input/output circuit receiving the column addresses and selectively latching a column address in which a failure occurs among the column addresses in response to the latch enable signal.

Abstract: A semiconductor device includes: a non-volatile memory including a normal region, a self-repair region and a redundancy region, each having a plurality of cells; a first boot-up control block suitable for controlling a first boot-up operation to detect defective cells of the normal region and store a defective address in a first latch unit; a self-program control block suitable for controlling a self-program operation to program the defective address stored in the first latch unit into the self-repair region; and a second boot-up control block suitable for controlling a second boot-up operation to read out data of the normal region based on an input address while reading out data of the redundancy region instead of the data of the normal region when data of the self-repair region coincides with the input address.

Abstract: There are provided, a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

Abstract: Provided is a phase difference film formed of a resin containing a polymer having crystallizability, and having an NZ factor of less than 1. A production method of the phase different film includes: bonding a second film to one or both surfaces of a first film formed of a resin containing the polymer having crystallizability and having a glass transition temperature Tg (° C.) and a melting point Tm (° C.), to obtain a third film, the second film having a shrinkage percentage in at least one direction at (Tg+30)° C. of 5% or more and 50% or less; heating the third film to Tg° C. or higher and (Tg+3)° C. or lower to obtain a fourth film; and heating the fourth film to (Tg+50)° C. or higher and (Tm?40)° C. or lower.

Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

Abstract: An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.

Abstract: For controlling device performance based on temperature differential, an apparatus includes a plurality of sensors positioned at different locations of the apparatus, a controller, and a memory that stores code executable by the controller. The controller determines a plurality of temperatures using the plurality of sensors. Here, each temperature corresponds to a different location of the apparatus. The controller calculates a temperature differential for the apparatus using the plurality of temperatures. The controller maintains device performance in response to the temperature differential being within a threshold amount and throttles device performance in response to the temperature differential exceeding the threshold amount.

Abstract: A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.

Abstract: In various example embodiments, a system and method for enhancing a user's on-line experience by utilizing a computer-implemented on-line session trace system is provided. The on-line session trace system is provided in connection with an on-line trading platform. The on-line session trace system records and stores a state of an on-line session associated with a user identification and permits a user associated with the user identification to commence a further on-line session from a state corresponding to the saved state of a previous on-line session.

Abstract: A memory device may include a command controller and a memory array with multiple memory cells. The command controller may receive commands to write a data pattern to the memory cells of the memory array. The data pattern may be repeated across multiple cells of the memory array without further input from input/output data lines. Additionally, the memory device may include one or more counters to assist in accessing the memory cells of the memory array.

Abstract: An indication that a test resource of a test platform has failed can be received. The test resource can be associated with performing a portion of a test of memory components. A characteristic of the test resource that failed can be determined. Another test resource of the test platform can be identified based on the characteristic of the test resource that failed. The portion of the test of memory components can be performed based on the another test resource of the test platform.

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.