Testing Patents (Class 365/201)
  • Patent number: 11320488
    Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sundarrajan Rangachari, Saket Jalan
  • Patent number: 11315628
    Abstract: Various implementations described herein are directed to a device having memory with a first array and a second array. The device may have power rails formed in frontside metal layers that supply core voltage to the memory. The power rails may include a first path routed through a first frontside metal layer to the first array of the memory, and the power rails may include a second path routed through the first frontside metal layer and a second frontside metal layer to the second array of the memory.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: April 26, 2022
    Assignee: Arm Limited
    Inventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Ayush Kulshrestha, Sony
  • Patent number: 11315634
    Abstract: A device includes at least one tunable resistive element. Each tunable resistive element comprises a first terminal, a second terminal, and a dielectric layer arranged between the first and second terminals. The device is configured to apply at least one electrical set pulse to the resistive elements to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer. The device is configured to apply at least one electrical reset pulse to displace a subset of the oxygen vacancies of the conductive filament. The at least one electrical reset pulse comprises a first part, which is adapted to increase the temperature of the conductive filament and increase the mobility of the oxygen vacancies of the conductive filament, and a second part, which is configured to displace the subset of the oxygen vacancies of the conductive filament.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: Siegfried Friedrich Karg, Gerhard Ingmar Meijer
  • Patent number: 11315652
    Abstract: The disclosure performs a pre-test that checks electrical connections between each electrical contact of the socket and the corresponding pin of the semiconductor chip during a pre-test stage before a burn-in test. The electrical connection between each of the electrical contacts and each of the pins may be checked through multiple signal channels. Even when one of the signal channels failed, the pre-test and the burn-in test may still be performed as long as another one of the signal channels passes the pre-test. In addition, the pre-test stage through multiple signal channels also provides information for determining whether the failure of semiconductor chip is caused by the electrical connection between the socket of the burn-in board or the semiconductor chip itself.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: April 26, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Chih-Chiang Lai
  • Patent number: 11309055
    Abstract: Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Claudio Giaccio, Ferdinando Pascale, Raffaele Mastrangelo, Erminio Di Martino, Ferdinando D'Alessandro, Cristiano Castellano, Andrea Castaldo
  • Patent number: 11309013
    Abstract: A memory device includes: first power pins in a first power area and configured to receive a first power voltage; data pins configured to transmit or receive data signals, the data pins being arranged in a first region and in a second region each including the first power area; control pins configured to transmit or receive control signals in the first region and in the second region; second power pins in a second power area between the first region and the second region and configured to receive a second power voltage different from the first power voltage; and ground pins in the second power area and configured to receive a ground voltage.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 19, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byongmo Moon, Beomyong Kil, Jihye Kim
  • Patent number: 11309048
    Abstract: A method of testing using a memory test apparatus connected to a memory device includes receiving a test command. When the test command is a finite state machine (FSM) operation command, the memory device is tested in accordance with the FSM operation command, and an operation is performed to output a result depending on a pass/fail result. But, when the test command is a direct access command, an auto-operation test of input data is performed in a test region according to received address information, and a test result is output, which may include output data with fail information or the auto-operation.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: April 19, 2022
    Inventors: Hong-Mook Choi, Hye Soo Lee, Ji-Su Kang, Hyun Il Kim
  • Patent number: 11302371
    Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: April 12, 2022
    Assignee: Rambus Inc.
    Inventor: Ian Shaeffer
  • Patent number: 11293982
    Abstract: The present invention provides an improved testing of a complex device under test, in particular a parallel analysis of signals of a device under test. Multiple signals of the device under test may be acquired and characteristic parameters of the acquired signals may be determined. The determined characteristic parameters of the multiple signals may be stored. In particular, the characteristic parameters may be stored in form of an array, table or spread sheet.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 5, 2022
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventor: Philip Diegmann
  • Patent number: 11290014
    Abstract: A boost direct current-to-direct current (DC-DC) converter using a delta-sigma modulator (DSM), the boost DC-DC converter may comprise a boost driving circuit outputting an output voltage to output terminals by boosting an input voltage, a resistance distribution circuit outputting a feedback voltage by distributing the output voltage of the boost driving circuit, a compensator outputting a compensated feedback voltage by compensating for the feedback voltage outputted by the resistance distribution circuit based on a reference voltage, a delta-sigma modulator outputting a digital signal by modulating the compensated feedback voltage and a duty controller outputting a duty control signal for controlling a switching duty of the boost driving circuit by receiving the output of the delta-sigma modulator.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 29, 2022
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Kyun Cho, Tae Joong Kim, Kwang Chun Lee, Jung Nam Lee, Jae Ho Jung
  • Patent number: 11280831
    Abstract: According to one embodiment, a semiconductor integrated circuit includes: a first core that includes a first logic circuit that has a plurality of first scan chains, and a first generator that generates a first test pattern; a second core that includes a second logic circuit that has a plurality of second scan chains, and a second generator that generates a second test pattern; a controller that controls a test operation of the first and second cores. The controller is configured to: obtain a seed for a test pattern from the first generator; supply the obtained seed to the second generator; perform a test on the first and second cores for a same number of cycles; obtain first and second test results respectively from the first and second cores; and compare the first and second test results.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: March 22, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yuki Watanabe, Masato Nakazato, Shohei Morishima
  • Patent number: 11275116
    Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: March 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11264113
    Abstract: A memory system and an operating method thereof are provided. The memory system includes a storage device including a mode register suitable for activating or inactivating an auto mode and a memory suitable for storing data, and a storage device controller controlling the mode register to enter a test mode, after inactivating the auto mode, during a test operation of the storage device, and controlling the mode register to activate the auto mode again when the test operation of the storage device is completed.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Se Kyoung Hur, Kwang Seok Im
  • Patent number: 11257559
    Abstract: Provided herein may be a test circuit, a memory device, a storage device, and a method of operating the same. The word line test circuit may include an operation signal generator configured to generate a plurality of operation signals in response to a test command, a comparison result generator configured to, in response to the plurality of operation signals, generate a target voltage based on a test current, in which a current of a target word line varying with a test voltage is reflected, and to generate a comparison signal based on a result of a comparison between the target voltage and a reference voltage, and a word line defect detector configured to detect a defect in the target word line based on at least one reference count and a count of a reference clock, cycles of which are counted until a level of the comparison signal changes from a first level to a second level.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventor: Sung Won Choi
  • Patent number: 11250925
    Abstract: A ground bounce generator includes a resistor and at least one switch coupled in parallel with the resistor. The ground bounce generator is in a device under test circuit including a source, at least one ground bounce generator, at least one device under test, and a ground. The device under test is coupled in series between the source and the ground bounce generator. The device under test and the ground bounce generator are coupled in series between the source and the ground.
    Type: Grant
    Filed: July 26, 2020
    Date of Patent: February 15, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11250927
    Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: February 15, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Ashish Darbari, Iain Singleton
  • Patent number: 11222895
    Abstract: Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Yih Wang, Abhishek Sharma, Van Le
  • Patent number: 11204829
    Abstract: Systems, apparatus and methods are provided for an error correction code (ECC) architecture with reduced decoding latency in error control. An apparatus may comprise control circuitry configured to receive a status report that a decoding task has failed, determine that a higher priority is needed for a re-decoding task, generate a NAND read task having a second priority level higher than a first priority level of the failed decoding task, and generate an ECC re-decoding task having the second priority level.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: December 21, 2021
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Bo Fu, Jie Chen, Xiaoming Zhu, Zining Wu
  • Patent number: 11200959
    Abstract: A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Patent number: 11200941
    Abstract: An electronic device includes a memory device receiving a power supply voltage, a data strobe signal, and a data signal, and a system-on-chip that exchanges data with the memory device using the data strobe signal and the data signal. The system-on-chip performs write training that measures a magnitude of a delay of the data strobe signal due to variation in the level of the power supply voltage and adjusts a delay of the data signal using a result of the write training.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: December 14, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyumin Park
  • Patent number: 11194488
    Abstract: A memory system includes: a plurality of nonvolatile memories; a controller connected to the plurality of nonvolatile memories via a plurality of channels that includes a plurality of memory physical layer circuits arranged corresponding to the plurality of channels, respectively, one or more pads for calibration corresponding to the plurality of memory physical layer circuits, and a processor that controls the plurality of memory physical layer circuits. A single reference resistor is connected to the plurality of memory physical layer circuits via the pad. An output based on a ZQ calibration of the plurality of memory physical layer circuits is wired-OR connected to the single reference resistor via the one or more pads. The processor performs a calibration for each of the plurality of memory physical layer circuits in a time division manner using the single reference resistor.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: December 7, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Shinya Koizumi
  • Patent number: 11183226
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Patent number: 11152347
    Abstract: Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections. In exemplary aspects disclosed herein, to allow cross-connections to be made across different gates between PMOS and NMOS transistors formed in the circuit cell, cut areas in the circuit cell are located in different horizontal routing tracks and offset from each other in the direction of longitudinal axes of gates. Gate cross-connections can be routed around offset gate cut areas and coupled to active gates to form gate cross-connections. In this manner, fewer metal layers may be required to provide such cross-connections in the circuit cell, thus reducing area. Further, gate contacts of cross-connected gates can be formed as gate contacts over active areas (GCOAs) in diffusion areas of the circuit cell, thus facilitating easier routing of interconnections in non-diffusion area of the circuit cell for further ease of routing.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: October 19, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Kern Rim, John Jianhong Zhu, Da Yang
  • Patent number: 11151008
    Abstract: A diagnostic system may utilize telemetry from a monitored system to infer information about the operation of various components systems within the monitored system. In embodiments, inferences may be drawn from a comparison of various component systems using a system of implication and exoneration. Exoneration is utilized to isolate faulty components from functioning components by comparing information between the systems, which may run in parallel. A dynamic grouping algorithm may eventually isolate faulty components and suggest the root cause as well as multiple distinct faults.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 19, 2021
    Assignee: Oceaneering International, Inc.
    Inventors: Joshua Warren Mercer, Jeff Newberry, Govind Shil Dayal Srivastava
  • Patent number: 11145381
    Abstract: A memory with a test function and a method thereof. The memory includes a memory array having cells, input buffers divided into even- and odd-numbered groups and output buffers divided into even- and odd-numbered groups; at least two data input pads, respectively providing test data to the cells through the even-numbered and the odd-numbered input buffers; a first and a second logic gates, respectively performing a first logic operation on outputs of the even-numbered and odd-numbered output buffers; a third logic gate, performing a second logic operation on outputs of the first and the second logic gates; and at least one data output pad, coupled to an output of the third logic gate for providing a test result of the cells.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: October 12, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yasuhiro Konishi
  • Patent number: 11143694
    Abstract: A system, method and apparatus for measuring carrier lifetime of a device comprises subjecting a test device to a voltage via a voltage source associated with the test system, disconnecting the test device from the voltage source, measuring the voltage as a function of time, measuring the current as a function of time, and determining a carrier lifetime of the test piece according to the slope of the measured voltage and the measured current.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 12, 2021
    Assignee: TEXAS TECH UNIVERSITY SYSTEM
    Inventors: Shelby Lacouture, Stephen Bayne
  • Patent number: 11144387
    Abstract: Embodiments include a serial bus controller that may be coupled to an in band serial peripheral interface (SPI) link, to request a write of data and a subsequent read of the data from a memory device and in response to the request to read the data, receive a bit error report and optionally correct the bit error over the in band SPI link. Embodiments include a memory device, e.g., a flash memory device, to detect and report the bit error over the in band SPI link, where the flash memory device, in response to a request to write and/or erase data, calculates or determines an error correction code (ECC) and stores corresponding parity data. In embodiments, after receiving a subsequent request to read the data, the flash memory device accesses the stored parity data to check the ECC for a bit error and if a bit error is detected, reports the detected bit error over the in band SPI link. Other embodiments may be described and claimed.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: October 12, 2021
    Assignee: INTEL CORPORATION
    Inventors: Zhenyu Zhu, William A. Stevens, Jr., Michael T. Klinglesmith, Mikal Hunsaker
  • Patent number: 11144235
    Abstract: Disclosed approaches for measuring memory performance include inputting respective sets of parameter values for master circuits. Each set specifies control over a transaction issuance rate, a transaction size, or an address pattern. Configuration data is generated for implementing master circuits in programmable logic circuitry based on the sets of parameter values. Each master circuit is configured to issue memory transactions according to the respective set of parameter values. The programmable logic circuitry is configured with the configuration data, and the master circuits are activated. Each master circuit issues memory transactions based on the respective set of parameter values. Each master circuit measures performance metrics of memory circuitry in processing the memory transactions and stores data indicative of the performance metrics.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: October 12, 2021
    Assignee: XLNX, INC.
    Inventors: Rowan Lyons, Noel Brady
  • Patent number: 11144214
    Abstract: Apparatuses and methods related to memory authentication. Memory devices can be authenticated utilizing authentication codes. An authentication code can be generated based on information stored in a fuse array of the memory device. The authentication code can be stored in the memory device. The stored authentication code can be compared to a captured authentication code based on fuse array information broadcast to memory components of the memory device. The authenticity of the memory device can be determined based on the comparison and can result in placing the memory device in an unlocked state.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Rachael R. Carlson, Aparna U. Limaye, Diana C. Majerus, Debra M. Bell, Shea M. Morrison
  • Patent number: 11139044
    Abstract: A memory testing method and a memory testing system. The memory testing system includes a host system and a testing device. The host system includes a processor. The testing device is coupled to the host system and a rewritable non-volatile memory module. A first memory controlling circuit unit corresponding to a first type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain first test information. A second memory controlling circuit unit corresponding to a second type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain second test information according to the first test information. The processor determines that whether the rewritable non-volatile memory module is applicable to the second type memory storage device or not according to the first test information and the second test information.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: October 5, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Siu-Tung Lam, Chih-Hung Chiu, Kun-Tsung Lo, Chao-Kai Zhang
  • Patent number: 11127477
    Abstract: An E-fuse circuit comprising: an E-fuse group, comprising a plurality of E-fuse sections, wherein each one of the E-fuse sections comprises a plurality of E-fuses; a multi-mode latch circuit, configured to receive an input signal to generate a first output signal in a burn in mode, and configured to receive an address to be compared to generate a second output signal in a normal mode; a first logic circuit group, configured to receive a first part of bits of the first output signal to generate a control signal in the burn in mode; and a second logic circuit group, configured to receive the control signal and a second part of bits of the first output signal to generate a selection signal in the burn in mode, to select which one of the E-fuse sections is activated.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 21, 2021
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Tse-Hua Yao, Yi-Fan Chen
  • Patent number: 11113129
    Abstract: Several embodiments of memory devices and systems for real time block failure analysis are disclosed herein. In one embodiment, a system includes a memory array including a plurality of memory cells and a processing device coupled to the memory array. The processing device is configured to sense, in response to detection of an error associated with a subset of a plurality of memory cells of the memory device, a state associated with each memory cell of the subset of the plurality of memory cells. The processing device is further configured to store state distribution information in a persistent memory, the state distribution information comprising the sensed state associated with each memory cell of the subset.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Francis Chew, Gerald L. Cadloni, Bruce A. Liikanen
  • Patent number: 11107543
    Abstract: A current demarcation voltage is determined, where the current demarcation voltage is to be applied to a memory cell for reading a state of the memory cell. Based on the current demarcation voltage and a space between a first threshold voltage distribution corresponding to a first state of the memory cell and a second threshold voltage distribution corresponding to a second state of the memory cell, a test demarcation voltage having a low error rate of reading the state of the memory cell is selected. The current demarcation voltage is set to correspond to the selected test demarcation voltage.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zhenming Zhou, Murong Lang
  • Patent number: 11094391
    Abstract: A processor memory is stress tested with a variable list insertion depth using list insertion test segments with non-naturally aligned data boundaries. List insertion test segments are interspersed into test code of a processor memory tests to change the list insertion depth without changing results of the test code. The list insertion test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The list insertion test segments include list insertion segments and load/store segments. The list insertion segments locate a current memory location using a fixed segment at a known location. The load/store segments load and store list elements in memory.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
  • Patent number: 11094392
    Abstract: A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: August 17, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Charles Lance Fuoco, Brian Karguth, Jay Bryan Reimer, Samuel Paul Visalli
  • Patent number: 11087823
    Abstract: Technologies for a multi-bit non-volatile dynamic random access memory (nvDRAM) device, which may include a DRAM array having a plurality of DRAM cells with single or dual transistor implementation and a non-volatile memory (NVM) array having a plurality of NVM cells with single or dual transistor implementations, where the DRAM array and the NVM array are arranged by rows of word lines and columns of bit lines. The nvDRAM device may also include one or more of isolation devices coupled between the DRAM array and the NVM array and configured to control connection between the dynamic random access bit lines (BLs) and the non-volatile BLs. The word lines run horizontally and may enable to select one word of memory data, whereas bit lines run vertically and may be connected to storage cells of different memory address.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 10, 2021
    Assignee: Aspiring Sky Co. Limited
    Inventors: Zhijiong Luo, Xuntong Zhao
  • Patent number: 11087857
    Abstract: A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: August 10, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Devanathan Varadarajan, Lei Wu
  • Patent number: 11081200
    Abstract: A memory device to generate intelligent, proactive responses to a read command. For example, signal and noise characteristics of a group of memory cells in a memory device are measured to determine a read voltage. An action is identified based on evaluation of the quality of data retrievable using the read voltage from the group of memory cells. While a response indicating the action is provided responsive to the command, the memory device can initiate the action proactively before a subsequent command, following the response, is received.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Patent number: 11081202
    Abstract: A computer-implemented method includes receiving a memory address of a memory location in a memory that has been identified to be failing. The method further includes determining that the memory location is from a particular portion of the memory. The method further includes, in response to a number of memory locations that are identified to be failing from the particular portion of the memory being below a predetermined threshold, logging the memory address in a set of failing address registers associated with the memory, otherwise, skipping the logging of the memory address in the failing address registers.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Uma Srinivasan, Thomas J. Knips, Gregory J. Fredeman, Matthew Steven Hyde, Thomas E. Miller
  • Patent number: 11074977
    Abstract: A semiconductor device includes a memory block including a plurality of memory strings, each of the plurality of memory strings including one or more dummy transistors, wherein each of the dummy transistors, included in the plurality of memory strings, is programmed to different degrees according to a junction overlap of each of the memory strings.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Eun Young Park
  • Patent number: 11056179
    Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Chong J. Zhao, James A. McCall, Shigeki Tomishima, George Vergis, Kuljit S. Bains
  • Patent number: 11049503
    Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: June 29, 2021
    Assignee: Apple Inc.
    Inventors: Timothy J. Millet, Manu Gulati, Michael F. Culbert
  • Patent number: 11043269
    Abstract: Test resources of a test platform that are performing a test of memory components are determined. An indication that a particular test resource of the test resources of the test platform has failed can be received. The particular test resource is failed while performing a portion of the test of memory components. A remaining portion of the test of memory components can be performed based on the indication that the particular test resource of the test platform has failed.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Sivagnanam Parthasarathy, Daniel Scobee
  • Patent number: 11041906
    Abstract: A system and method for performing scan chain testing is disclosed. Scan cells, in the form of scan chains, are inserted into circuit designs for testing those circuit designs. The integrity of the scan chains is checked for defects before testing the circuit under test. In order to do so, various scan chain patterns, including one or both of U-turn and Z-turn patterns, are used in order to generate scan chain test data. The scan chain test data is analyzed in order to identify one or both of a type of defect (e.g., a timing fault, stuck-at fault, etc.) or a location of the defect. Further, the scan chain testing is performed using chain patterns with adaptive length.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 22, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Yu Huang, Szczepan Urban, Wu-Tung Cheng, Manish Sharma
  • Patent number: 11043261
    Abstract: A circuit includes a first cell in a first row of a memory array, a second cell in a second row of the memory array, and a data line perpendicular to the first row and the second row, intersecting each of the first cell and the second cell, and electrically coupled with each of the first cell and the second cell. The circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a read operation on the first row.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11036632
    Abstract: The present disclosure relates to an electronic device. A memory controller having improved read interleaving and write interleaving performance may include a buffer memory temporarily storing data chunks read from a sacrificial area, a target die information manager generating target die information on a plurality of memory dies in which the data chunks are respectively stored according to logical address counts of the data chunks corresponding to the plurality of memory dies, respectively, determined based on correspondence information between the plurality of memory dies and logical addresses provided from a host, and a write operation controller controlling the plurality of memory dies so that the data chunks temporarily stored in the buffer memory are stored in the plurality of memory dies on the basis of the target die information.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventor: Seok Jun Lee
  • Patent number: 11037653
    Abstract: A memory device includes: a memory cell array including a plurality of memory regions, the plurality of memory regions including first and second edge memory regions each respectively including an edge word line, and the plurality of memory regions including a center memory region including a center word line; a segment selection circuit configured to select a target segment from among a plurality of segments based on an input row address and output segment information identifying the target segment, where the first and second edge memory regions and the center memory region are grouped into a first segment of the plurality of segments; and a column decoder configured to control a column repair operation performed on a segment basis based on at least one fuse set that is selected based on the segment information.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: June 15, 2021
    Inventor: Kyungryun Kim
  • Patent number: 11023027
    Abstract: Streaming content using a data streaming device having limited power is described. A data streaming device receives streaming content from a network and provides the streaming content for display on a content display device. Data streaming device includes power supplies that receive power from the content display device. The power supplies use the power to operate components of data streaming device that process the streaming content. A measuring module measures the power provided to the data streaming device. When the power is insufficient, a controller generates an indication that there is insufficient power to operate the components of the data streaming device. The controller may also modify functionality of the components to operate using available power or disable a component of the data streaming device.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: June 1, 2021
    Assignee: Roku, Inc.
    Inventors: Gregory Garner, Anthony Wood, Simon Martin, David Stern
  • Patent number: 11003369
    Abstract: Performing a tune-up procedure on a storage device including determining, during a boot process, that a first storage device is available for a tune-up procedure, wherein the tune-up procedure prepares the first storage device for use after being offline; reserving the first storage device to perform the tune-up procedure, wherein reserving the first storage device prevents another system from performing the tune-up procedure on the first storage device; and executing the tune-up procedure on the first storage device.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: May 11, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Andrew Bernat, Wei Tang
  • Patent number: RE48938
    Abstract: A component subsystem and a method for authenticating the component subsystem. The component subsystem may be installed in a host device. The method can include an authentication protocol, wherein the host device sends a test voltage value to the component subsystem which, in turn, generates a test voltage based on the test voltage value. The test voltage is applied to a test cell that includes a wordline, a bitline, and a memory film. A response voltage is read from the bitline and compared to an expected value. If the response voltage matches the expected value, host device and/or component subsystem functionality is enabled. If the response voltage does not match the expected value, the host device and/or component subsystem functionality is disabled.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 22, 2022
    Assignee: XEROX CORPORATION
    Inventors: Christopher P. Caporale, Alberto Rodriguez, Scott Jonathan Bell, John M. Scharr