Testing Patents (Class 365/201)
  • Patent number: 10614903
    Abstract: A computer-implemented method includes receiving probability distribution function (PDF) data corresponding to bit-error-rate (BER) data for each of a plurality of data blocks within a qualified set of NVRAMS, collecting non-exhaustive bit-error-rate data for each of the data blocks on a tested NVRAM to produce non-exhaustive test data for each of the data blocks, determining a plurality of stable data blocks on the tested NVRAM based on the non-exhaustive test data and the probability distribution function data for each of the data blocks, determining, from the non-exhaustive test data, an inferior data block for the stable data blocks on the tested NVRAM, collecting exhaustive bit-error-rate data on the inferior data block to produce exhaustive test data for the tested NVRAM, and routing the tested NVRAM according to the exhaustive test data. A corresponding computer program product and computer system are also disclosed herein.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey W. Christensen, Phillip E. Christensen, Robert S. Miller, Matthew S. Reuter, Antoine G. Sater
  • Patent number: 10614904
    Abstract: Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a data receiver, a read buffer coupled between the data terminal and the memory core, and a write buffer coupled between the data receiver and the memory core. The write buffer may include at least a first input coupled to the data receiver, and a second input. While in a test mode, the write buffer may be loaded with data from the second input instead of the first input.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Stefan Dietrich, Wolfgang Spirkl
  • Patent number: 10613128
    Abstract: A testing device includes a transfer interface, a tester, a first socket group and a second socket group. The first socket group includes a plurality of tested devices coupled in series and the second socket group includes a plurality of tested devices coupled in series. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal. The double-frequency testing signal and a plurality of control signals are provided to the tested devices in the first socket group and the second socket group to perform the testing procedure on the tested devices of a same tested device pair simultaneously, and performing the testing procedure on the tested device pairs sequentially.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: April 7, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Chih-Hui Yeh, Ming-Jyun Yu
  • Patent number: 10598728
    Abstract: A scan chain for testing a combinatorial logic circuit includes a first scan chain path of flip-flops connected to the combinatorial logic circuit for functional mode operation during runtime of the combinatorial logic circuit. A second scan chain path of flip-flops is also connected to the combinatorial logic circuit and supports both a shift mode and a capture mode. The second scan chain path operates in shift mode while the first scan chain path is connected to the combinatorial logic circuit for functional mode operation. The second scan chain is then connected to the combinatorial logic circuit when run time is interrupted and operates in capture mode to apply the test data to the combinatorial logic circuit.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: March 24, 2020
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Bruno Fel
  • Patent number: 10593420
    Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Harry Barowski, Sheldon Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter
  • Patent number: 10587248
    Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
  • Patent number: 10580511
    Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: March 3, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Ashish Darbari, Iain Singleton
  • Patent number: 10573319
    Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: February 25, 2020
    Assignee: Apple Inc.
    Inventors: Timothy J. Millet, Manu Gulati, Michael F. Culbert
  • Patent number: 10564864
    Abstract: A system for controlling a solid state drive is disclosed that includes a plurality of NAND memory devices, each NAND memory device further comprising at least one die, a plurality of blocks associated with each of the dies, and a plurality of pages associated with each of the blocks. A pseudo clock system configured to determine a pseudo clock value for each of the NAND memory devices. An effective retention time system coupled to the plurality of NAND memory devices and configured to determine a maximum effective retention time for each of the NAND memory devices as a function of the pseudo clock value for the NAND memory device.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: February 18, 2020
    Assignee: DELL PRODUCTS L.P.
    Inventors: Justin L. Ha, Frederick K. H. Lee, Seungjune Jeon
  • Patent number: 10566072
    Abstract: A method for detecting a flash memory array includes a plurality of word lines, a plurality of bit lines, and a source line, includes executing a first detection process. The first detection process includes: applying a first positive voltage to a P-type well of the flash memory array; applying a ground to all the word lines; floating the bit lines and the source line; determining whether a leakage current flowing through the P-type well exceeds a leakage threshold; and when the leakage current exceeds the leakage threshold, determining that at least one of the word lines is short-circuited with at least one of the bit lines or the source line.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: February 18, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Koying Huang
  • Patent number: 10566034
    Abstract: A memory device and a method for test reading and writing thereof are provided. A precharge voltage control circuit is based on the precharge reference voltage to provide a first precharge voltage and a second precharge voltage. A sense amplifier circuit is coupled between a bit line and a complementary bit line and configured to sense data of a memory cell coupled to the bit line, and also coupled to the precharge voltage control circuit to make the bit line and the complementary bit line receive the first precharge voltage and the second precharge voltage respectively, the first precharge voltage and the second precharge voltage are on the same voltage level during the precharge operation, but during a test write sensing period and a test read sensing period after the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are different.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: February 18, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Yuji Nakaoka
  • Patent number: 10564875
    Abstract: An optical decoding system is applied to mode conversion of a memory. The optical decoding system includes an optical sensor and a processor. The optical sensor is utilized to sense an intensity of a pattern, and variation of the intensity containing an activation code. The processor is electrically connected with the optical sensor. The processor is adapted to analyze the variation of the intensity and to switch the memory from a normal mode to a configuration mode in accordance with the activation code. Normal operation of the memory is paused while the memory is set in the configuration mode.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: February 18, 2020
    Assignee: PixArt Imaging Inc.
    Inventor: Jr-Yi Li
  • Patent number: 10558258
    Abstract: An input/output (I/O) interface-based signal output method and apparatus. The method includes determining whether a voltage output by a core power supply domain of a first chip is lower than a preset threshold voltage of the first chip, and when the voltage output by the core power supply domain is lower than the threshold voltage, generating a first level signal according to a control function of the first chip over a second chip, where the first level signal is used to enable the second chip to be in an ignoring state after the second chip receives the first level signal, and sending the first level signal to the second chip through an I/O interface, where the ignoring state indicates that the second chip ignores a control signal and a data signal that are sent by the first chip where the method improves stable performance of a chip product.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 11, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Lijuan Tan
  • Patent number: 10560293
    Abstract: In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: February 11, 2020
    Assignee: KANDOU LABS, S.A.
    Inventors: Roger Ulrich, Peter Hunt
  • Patent number: 10558556
    Abstract: Systems, methods, and computer program products to perform an operation comprising determining, based on actual coverage point data for a first time interval and expected coverage point data, that a first set of lines of source code associated with the actual and expected coverage point data have not been executed by a system, instantiating, in the system, an action code associated with the first set of lines of source code and an effect code associated with the action code, and determining, based on a final state of the effect code, whether the action code executed correctly in the system.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: February 11, 2020
    Assignee: Cisco Technology, Inc.
    Inventor: John M. Lake
  • Patent number: 10559375
    Abstract: A semiconductor device includes: a non-volatile memory including a normal region, a self-repair region and a redundancy region, each having a plurality of cells; a first boot-up control block suitable for controlling a first boot-up operation to detect defective cells of the normal region and store a defective address in a first latch unit; a self-program control block suitable for controlling a self-program operation to program the defective address stored in the first latch unit into the self-repair region; and a second boot-up control block suitable for controlling a second boot-up operation to read out data of the normal region based on an input address while reading out data of the redundancy region instead of the data of the normal region when data of the self-repair region coincides with the input address.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Young-Bo Shim
  • Patent number: 10559341
    Abstract: A method for performing a refresh operation on a memory cell efficiently is provided. A semiconductor device including a normal memory cell and a trigger memory cell that determines whether the refresh operation is performed or not is used. Specific data is written to the trigger memory cell, and the data is read from the trigger memory cell at predetermined timing. When the read data agrees with the written specific data, no special operation is performed. When the read data does not agree with the written specific data, a refresh operation is performed automatically.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: February 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Hikaru Tamura
  • Patent number: 10551437
    Abstract: An apparatus for performing an electrical test at a device is described. In one general implementation, an apparatus may include a memory, a receiver, and a processor. The receiver is configured to receive a test signal, convert the test signal into a digital test signal (bit stream) and store the digital test signal in the memory. The receiver identifies when a pre-defined number of bits of the bit stream are available in the memory. The processor is configured to perform a logic operation on the bit stream and a reference signal, generate a test result based on the logic operation, and determine whether the test result satisfies a condition. In some implementations, the processor may be configured to synchronize the digital test signal with the reference signal prior to performing of the logic operation.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: February 4, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Gregoire Waelchli
  • Patent number: 10552307
    Abstract: In a data processing system that comprises a memory 8 comprising N memory banks 11, a memory controller is configured to store one or more N data unit×N data unit arrays of data in the memory 8 such that each data unit in each row of each N×N data unit array is stored in a different memory bank of the N memory banks 11, and such that each data unit in each column of each N×N data unit array is stored in a different memory bank of the N memory banks 11.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 4, 2020
    Assignee: Arm Limited
    Inventors: Tomas Fredrik Edsö, Fredrik Peter Stolt
  • Patent number: 10535416
    Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics International N.V.
    Inventor: Nishu Kohli
  • Patent number: 10522216
    Abstract: Disclosed is a static random access memory including an assist circuit. More particularly, a static random access memory according to an embodiment of the present disclosure may include a bit cell part including at least one bit cell connected between a first ground voltage node and a second ground voltage node; and a controller including a first transistor configured to control connection between the first ground voltage node and the second ground voltage node, a second transistor configured to float a first ground voltage of the first ground voltage node, and a third transistor configured to float a second ground voltage of the second ground voltage node, wherein the controller controls the first and second ground voltages supplied to the bit cell part using the first, second, and third transistors.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: December 31, 2019
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong Ook Jung, Se Hyuk Oh, Han Wool Jeong, Ju Hyun Park
  • Patent number: 10515673
    Abstract: A semiconductor device includes a memory circuit and a data output circuit. The memory circuit outputs first internal data having a first burst length in a first mode and outputs the first internal data and second internal data in a second mode. A sum of the first and second internal data has a second burst length. The data output circuit outputs the first internal data as first output data through a first input/output line in the first mode. The data output circuit outputs the first internal data as the first output data through the first I/O line and outputs the second internal data as second output data through a second I/O line in the second mode. The data output circuit controls an internal current according to a logic level combination of the first and second internal data to generate the first and second output data in the second mode.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 24, 2019
    Assignee: SK hynix Inc.
    Inventor: Kwandong Kim
  • Patent number: 10515689
    Abstract: A circuit includes a data line, a first cell in a first row of a memory array, and a second cell in a second row of the memory array. The first cell is electrically coupled with the data line and the second cell is electrically coupled with the data line. The circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a first read operation on the first row.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10510431
    Abstract: A method of detecting random telegraph noise defects in a memory includes initializing a first bit cell of the memory to a first value and reading the first value from the first bit cell. The method also includes writing a second value to the first bit cell and performing back to back read operations on a second bit cell adjacent to the first bit cell, after writing the second value. The method further includes attempting to read the second value from the first bit cell and determining whether the first bit cell is defective based on whether the second value was read from the first bit cell.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: December 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Sneha Revankar, Karthikeyan Subramanian
  • Patent number: 10509072
    Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Sylwester Milewski, Nilanjan Mukherjee, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
  • Patent number: 10490277
    Abstract: A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: David Resnick
  • Patent number: 10475491
    Abstract: A random code generator includes a memory cell array and a sensing circuit. The memory cell array includes plural antifuse differential cells. The sensing circuit has an input terminal and an inverted input terminal. When a first antifuse differential cell of the memory cell array is a selected cell, a bit line of the selected cell is connected with the input terminal of the sensing circuit and an inverted bit line of the selected cell is connected with the inverted input terminal of the sensing circuit. During a read cycle, the sensing circuit judges a storage state of the selected cell according to a first charging current of the bit line and a second charging current of the inverted bit line, and determines a bit of a random code according to the storage state of the selected cell.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: November 12, 2019
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Yung-Jui Chen, Chih-Hao Huang
  • Patent number: 10475486
    Abstract: An electronic device includes a pulse generator, a signal synthesizer, and a first storage circuit. The pulse generator generates a mode active pulse and a mode pre-charge pulse in response to an operation mode signal. The signal synthesizer synthesizes an active signal and the mode active pulse to generate a synthesized active signal. The signal synthesizer synthesizes a pre-charge signal and the mode pre-charge pulse to generate a synthesized pre-charge signal. The first storage circuit performs an active operation, a read operation, or a pre-charge operation in response to the synthesized active signal, a read signal, and the synthesized pre-charge signal in each of a first read mode and a second read mode.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 12, 2019
    Assignee: SK hynix Inc.
    Inventor: Yo Sep Lee
  • Patent number: 10462311
    Abstract: There is provided a communication apparatus. A communication control controls a communication unit so as to connect to one of a plurality of external apparatuses. A transfer unit transfers a data item to an external apparatus to which the communication unit has connected. In a case that a transfer of the data item is failed, a storage control unit stores transfer failure information in which the data item is associated with a transfer-destination external apparatus. In a case that the communication unit has connected to a first external apparatus, a transfer control unit controls a transfer of a data item. If a data item included in the transfer failure information is associated with the first external apparatus, the transfer control unit performs control so as to automatically transfer the data item to the first external apparatus.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: October 29, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuji Kawai
  • Patent number: 10446241
    Abstract: Several embodiments of memory devices and systems with walking read level calibration are disclosed herein. In one embodiment, a system includes a memory component having at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to perform iterative calibrations of the memory region by determining a first read level offset value during a first calibration. A new base read level test signal is determined based on the first read level offset value. During a second calibration using the new base read level test signal, a second read level offset value is determined.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni
  • Patent number: 10431224
    Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: October 1, 2019
    Assignee: Apple Inc.
    Inventors: Timothy J. Millet, Manu Gulati, Michael F. Culbert
  • Patent number: 10412052
    Abstract: System and method for managing devices comprising a memory store having memory locations, wherein each memory location stores one or more attributes associated with one or more devices. Device manager arranged to execute commands to take an action on the one or more attributes stored in the memory locations, and to receive from the one or more devices values of the corresponding one or more attributes. Synchronizer configured to maintain synchronization between the attributes stored in the memory store and the attributes associated with the devices.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: September 10, 2019
    Assignee: Vodafone IP Licensing Limited
    Inventors: Nick Bone, Tim Snape, Yakeen Prabdial, Jorge Bento, Michael Prince
  • Patent number: 10388401
    Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device configured for outputting a command and an address, and inputting/outputting data. The semiconductor system may include a second semiconductor device including first and second registers, wherein first corrected data, which is generated by correcting an error of internal data outputted in a first error correction operation, may be stored in the first register, and second corrected data, which is generated by correcting an error of the internal data outputted in a second error correction operation, may be stored in the second register, based on the command and the address.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventors: Min Seok Choi, Dae Yong Shim
  • Patent number: 10381099
    Abstract: Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including a plurality of memory cells; and a control circuit that receives read data from the plurality of memory cells, compares the read data with reference data, and further provides an error signal. The control circuit further provides the error signal when a number of bit errors detected is greater than or equal to a predetermined number, and suppresses providing the error signal when the number of bit errors detected is less than the predetermined number.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Toru Ishikawa
  • Patent number: 10380043
    Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Tonia G. Morris, John V. Lovelace, John R. Goles
  • Patent number: 10325648
    Abstract: The apparatus provided may be a memory circuit. The memory circuit includes a memory cell. The memory cell has a bitline. The memory circuit also includes a write driver. The write driver is configured to drive the bitline to write a bit to the memory cell during a write operation. The write driver is also configured to float the bitline to mask the bit during a read operation. The write driver may use NMOS pullup transistors.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Darshit Mehta, Chulmin Jung, Po-Hung Chen
  • Patent number: 10318464
    Abstract: A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a non-target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, one or more non-target access CS signals disabling target access to one or more non-target memory ranks of the first plurality of memory ranks coupled to the non-target local controller; and the memory controller being further configured to provide to a target local controller of the second plurality of local controllers, out of the first plurality of CS signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers a command and address (CA) sign
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 11, 2019
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Yibo Jiang, Gang Yan, Robert Xi Jin, Lizhi Jin, Leechung Yiu
  • Patent number: 10312928
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 4, 2019
    Assignee: MAXLINEAR, INC.
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Patent number: 10311966
    Abstract: A system and integrated circuits are provided for determining performance metrics over a plurality of cycles of an input signal using on-chip diagnostic circuitry. The system comprises a trigger generation module configured to generate a trigger signal, and diagnostic circuitry coupled with the trigger generation module. The diagnostic circuitry comprises a memory comprising a plurality of data lines, and a plurality of delay elements, each delay element of the plurality of delay elements connected between consecutive data lines of the plurality of data lines. The diagnostic circuitry is configured to receive at least one input signal, and write, upon receiving the trigger signal, values on the plurality of data lines to the memory, thereby acquiring samples of a plurality of cycles of the input signal.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, Jeffrey M. Scherer
  • Patent number: 10303998
    Abstract: A floating gate setup method, system, and computer program product include, in an initial setup of weights for a floating gate including rows, columns, and a separate input line: comparing a current weight to a desired weight, performing a feedback to the input line to set a voltage to change the floating gate FET VT and the current weight, and checking that the current weight is within a predetermined tolerance of the desired weight.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10302695
    Abstract: Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 28, 2019
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Tejinder Kumar, Akshat Jain
  • Patent number: 10304522
    Abstract: Big data analysis using low power circuit design including storing a plurality of data bits in a plurality of cells on a bitline of a dynamic random access memory (DRAM), wherein each data bit corresponds to a test result, and wherein each of the plurality of cells on the bitline is associated with a different wordline; precharging the bitline to a midpoint voltage between a low voltage corresponding to a low data bit and a high voltage corresponding to a high data bit; activating, at the same time, each wordline associated with each of the plurality of cells on the bitline, wherein activating each wordline causes a voltage to be applied to the bitline from each of the plurality of cells; and measuring a resulting voltage on the bitline to obtain a value corresponding to a percentage of the test results that indicate a passing test result.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Patent number: 10304527
    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: May 28, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Yabuuchi, Hidehiro Fujiwara
  • Patent number: 10276165
    Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: April 30, 2019
    Assignee: Apple Inc.
    Inventors: Timothy J. Millet, Manu Gulati, Michael F. Culbert
  • Patent number: 10268257
    Abstract: A memory control device that is capable of making a nonvolatile memory of an information device exhibit the performance thereof certainly. A detection unit detects whether a data writable semiconductor memory is a nonvolatile memory or a volatile memory. A setting unit performs a setting to a volatile memory and performs a different setting to a nonvolatile memory that is detected with the detection unit.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: April 23, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yoshihisa Nomura
  • Patent number: 10268578
    Abstract: In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Shankar Natarajan, Aliasgar S. Madraswala, Wayne D. Tran
  • Patent number: 10268548
    Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: April 23, 2019
    Assignee: Pure Storage, Inc.
    Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
  • Patent number: 10254339
    Abstract: To improve test efficiency of addressable test chips, an addressable test chip test system includes a test equipment, a probe card and an addressable test chip, the test equipment connects to the addressable test chip through the probe card to constitute a test path, the test system includes a new type of address register, which can provide two test modes for users according to user's needs. A new type of high density addressable test chip can accommodate DUTs of more than 1000/mm2.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 9, 2019
    Assignee: Semitronix Corporation
    Inventors: Fan Lan, Shenzhi Yang, Yongjun Zheng, Weiwei Pan
  • Patent number: 10248530
    Abstract: Methods and system are provided for determining a maximum number of users of a system or network. A system capacity can be determined by performing a plurality of capacity tests. Each capacity test of the plurality of capacity tests can produce capacity test results that can be used to define a region of the system capacity from which the system capacity can be selected based on network conditions. The system capacity can be used to determine a user capacity of the system which can indicate the maximum number of users that can be active at any given time on the system. The system capacity can be used with a percentage weight of a plurality of user events performed on the system by active users to determine the maximum number of users.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: April 2, 2019
    Assignee: Comcast Cable Communications, LLC
    Inventors: Lichia Lu, Qi Wang, Ningxiang Yuan
  • Patent number: 10248498
    Abstract: The disclosure relates to technology performing a cyclic redundancy check (CRC). Data is divided into a plurality of blocks, each of the plurality of blocks having a fixed size equal to a degree of a generator polynomial. A CRC computation is independently performed on each of the plurality of blocks, and the CRC computation for each of the plurality of blocks is combined by application of an exclusive or (XOR) operation.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 2, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Yan Sun, YunSong Lu, Wenzhe Zhou