Abstract: A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.

Abstract: An in-memory computing circuit includes an initial computing circuit and a target computing circuit. Herein, the initial computing circuit is configured to perform first operation processing on first data and second data to output a first operation result, and perform second operation processing on the first data and the second data to output a second operation result. The target computing circuit is configured to perform the first operation processing on the second operation result and the first operation result to output a first target result, and perform the second operation processing on the first data and the second operation result to output a second target result.

Abstract: A dual-line cascade application system for simultaneously supplying electrical power and transmitting data, including a controller, cascade chips connected to the controller, and LED lights connected to the cascade chips. Each cascade chip is provided with a voltage clamp module, an electrical power supply module, a data storage module, a PWM constant current output driving circuit, an R end (Red LED output end), a G end (Green LED output end), a B end (Blue LED output end), a W end (White LED output end), a VCC/DATA end and a GND/DATA end, as well as a data sampling and calibration module, a power line data sampling and transmission module, a chip initial address setting by command module, a module which determines if E-fuse address of the chip is identical to an address of received data, and an E-fuse module which are sequentially connected. A method using the system is also provided.

Abstract: A control method includes: decoding a third Operand (OP) in a third Mode Register (MR) and a fourth OP in a first MR; and in response to the semiconductor memory being in a preset test mode, controlling, in a case where the third OP meets a first decoding condition, the impedance of a Data Mask (DM) pin to be a first value; or controlling, in a case where the third OP meets a second decoding condition, the impedance of the DM pin to be a second value according to the fourth OP; wherein the third OP is configured to indicate whether the DM pin is a test object in the preset test mode, and the fourth OP is configured to indicate whether the DM pin is enabled.

Abstract: Device testing techniques including allocating a log memory, testing a device, and storing test result during testing of the device in the allocated log memory. The allocated log memory can be accessed through an application programming interface (API) during testing of the device, wherein the allocated log memory remains unlocked during testing of the device.

Abstract: A system and method are provided for driving a dual-rail memory circuit that operates with sensing of a memory bit cell, inversion of the sense signal and level shifting in four stage delays. The system includes inversion circuitry configured to (i) receive power from a first power rail (VDDA) of the dual-rail memory, (ii) receive an output of a sense amplifier that senses a state of a bit cell of the dual-rail memory, and (iii) provide two outputs (QB, QT) limited to the first power rail VDDA. The system further includes level-shifting circuitry configured to (i) receive the two outputs of the inversion circuitry (QB, QT). (ii) receive power from a second power rail of the dual-rail memory (VDDP) and (iii) drive an output (Q) in dependence on the two outputs of the inversion circuitry (QB, QT) and limited to the second power rail VDDP which is less than the first power rail VDDA.

Abstract: Methods to test functional memory interface logic of a core under test utilize a built-in-self-test (BIST) controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at BIST mode, an at-speed functional mode is utilized to capture a desired memory output.

Abstract: Embodiments of the present disclosure provide a control method, a semiconductor memory, and an electronic device. When the semiconductor memory is in a preset test mode, a first Model Register (MR) and a second MR related to a Data Pin (DQ) are allowed to directly define the impedance of a Data Mask Pin (DM). The DM does not need to add definition of an output driver state and a related control circuit for the preset test mode to ensure that the preset test mode is adapted to the DM. The impedance of the DM may be tested in the preset test mode to avoid circuit processing errors.

Abstract: According to one embodiment, a controller configured to manage second test information including status information indicating that a test related to a write operation and a read operation on a second storage area has not been executed. In response to receiving a command for acquiring information related to the second storage area from a host, the controller transmits the second test information to the host. When execution of the test on the second storage area is requested by the host, the controller executes the test related to the write operation and the read operation on the second storage area, and updates the status information of the second test information.

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

Abstract: A processing system employs techniques for enhancing dynamic random access memory (DRAM) page retirement to facilitate identification and retirement of pages affected by multi-page DRAM faults. In response to detecting an uncorrectable error at a first page of DRAM, the processing system identifies a second page of the DRAM for potential retirement based on one or more of physical proximity to the first page, inclusion in a range of addresses stored at a fault map that tracks addresses of DRAM pages having detected faults, and predicting a set of pages to check for faults based on misses at a translation lookaside buffer (TLB).

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

Abstract: An electronic device may include: a control pulse generation circuit configured to selectively generate one of a first control pulse and a second control pulse on the basis of a reference code during a test period; and a voltage control code generation circuit configured to perform an addition operation or subtraction operation on a logic bit set of a voltage control code to set the voltage level of an operation voltage on the basis of the first and second control pulses.

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

Abstract: A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.

Abstract: A method, device for checking data, an electronic device and a storage medium are provided. The method includes operations as follows. A memory array is read to obtain read data, and the read data is compressed to obtain first compressed data. The first compressed data is compared with second compressed data, the second compressed data being obtained by compressing written data corresponding to the read data. In responsive to that the first compressed data is consistent with the second compressed data, whether data of a predetermined bit in the read data is consistent with pre-stored original bit data is detected, to determine whether the read data is correct. It is determined that the read data is correct if the data of the predetermined bit is consistent with the pre-stored original bit data, otherwise it is determined that the read data is incorrect.

Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.

Abstract: A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.

Abstract: A selection device includes: a storage unit storing a plurality of types of amplifiers in advance; an acquisition unit for acquiring a plurality of selected amplifiers selected for driving a plurality of designated motors designated in advance; an alignment order selection unit for selecting a predetermined arrangement order in which the plurality of selected amplifiers are arranged adjacent to each other in the width direction on the basis of the types of the plurality of selected amplifiers; and a display control unit for causing a display unit to display the predetermined arrangement order.

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.

Abstract: An electronic device includes: a wiring board; an electric connection wiring connected to a power supply; motor connection wirings arranged on a peripheral side of the wiring board and connected to the electric motor; and semiconductor modules having semiconductor elements and a resin mold. The semiconductor modules are arranged at a position on the electric connection wiring or on the peripheral side of the electric connection wiring and on a center side of the motor connection wiring. At least a part of electrodes of the plurality of semiconductor modules is mounted on the electric connection wiring.

Abstract: A data writing method includes: receiving a first writing command, and selecting a target bank and a target column address according to the first writing command, data corresponding to the first writing command being first test data; writing the first test data into the target column address of the bank selected according to the first writing command, and latching the first test data on an address bus during the writing at least until a second writing command is executed; receiving the second writing command, and reselecting the target bank and the target column address according to the second writing command; and writing the first test data latched on the address bus into a reselected target column address of a reselected target bank.

Abstract: A memory system for storage access monitoring is provided. The memory system includes a media controller of a memory. An analog persistent circuit is coupled to the media controller and configured to monitor access to the memory. The analog persistent circuit stores persistent data related to memory access counts access signals from the command/address bus. A command/address bus is coupled to the analog persistent circuit. A memory array is communicatively coupled to the command address and the media controller.

Abstract: A test device method includes: setting a core voltage of a memory device to a first voltage value and a peripheral voltage of the memory device to a second voltage value; testing the memory device by accessing the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a third voltage value and the at least one peripheral voltage of the memory device to a fourth voltage value; testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a fifth voltage value and the at least one peripheral voltage of the memory device to a sixth voltage value; and testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage.

Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Abstract: A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

Abstract: A TPM with programmable fuses in an SOC includes an on-die RAM storing a blown-fuse count and a TPM state read from off-die NV memory. During initialization, if the blown-fuse count is greater than a TPM state fuse count, a TPM state PIN-attempt-failure count is incremented, thereby thwarting a replay attack. If a PIN satisfies a PIN failure policy, and if a TPM state previously-passed-PIN indicator is set to true, a fuse is blown and the blown-fuse count incremented depending on the PIN being incorrect, but if the TPM state previously-passed-PIN indicator is set to false, a fuse is blown and the blown-fuse count incremented independent of whether the PIN is correct or incorrect. The TPM state fuse count is set equal to the blown-fuse count. If a counter cleared before processing the PIN remains cleared during the next initialization, a fuse voltage cut is detected and a penalty imposed.

Abstract: A memory component has a block of memory cells that has been designated as a bad block. A processing device included in the memory component identifies a functional page of memory cells in the bad block, and programs system data to the identified functional page of memory cells in the bad block.

Abstract: This application relates to a data transmission circuit, a method making it, and a storage device. The circuit includes a mode register data storage unit and an array area data storage unit. The mode register data storage unit outputs mode register data in response to a first clock signal; the output terminal of the array area data storage unit and the output terminal of the mode register data storage unit are both connected to the first node, the array area data storage unit receives array area data in response to the first pointer signal, and outputs the array area data in response to the second pointer signal. This technic can accurately control the mode register data and the array area data to output through the respective output channels in turn.

Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.

Abstract: Embodiments of the present disclosure provide intrinsic program suppression of a non-programmed two-terminal resistive switching memory cell of a plurality of memory cells defining an identifier bit, such as a physical unclonable feature (PUF) bit. Differential programming applies a program signal to a plurality of resistive switching memory cells and derives a value for the identifier bit from which cell(s) becomes programmed. However, where more than an expected number of cells become programmed, an invalid value can occur. Disclosed intrinsic program suppression mitigates or avoids the invalid result by very rapidly reducing the program signal to a non-programmed cell(s) in response to another cell(s) becoming programmed. In an embodiment, intrinsic program suppression can be implemented by programming the plurality of memory cells electrically in parallel and shorting second terminals of the plurality of memory cells at a common node.

Abstract: A memory testing device uses a master control unit to concurrently operate multiple, intelligent, slave control units (SCUs). SCUs have one or more processing unit(s) (i.e. Finite State Machines, micro controllers, processors) capable of processing one or more firmware with or without operating system (i.e. bare-metal, embedded OS, RTOS (real time operating system)) to perform a series of task defined by firmware(s) for testing volatile and/or non-volatile memory devices connected into one or more DUT devices plus SCU has capability of having operating system and install and run host applications locally within each SCU units to mimic host applications environments along with performing regular memory testing.

Abstract: A memory device coupled to a memory controller and including a memory array and an access circuit is provided. The memory array includes a plurality of cells. Each of the cells is coupled to a word-line. The access circuit is coupled between the memory controller and the memory array. In a normal mode, the access circuit executes a refresh action for the cells which are coupled to at least one word-line in response to the memory controller outputting an auto-refresh command. In a standby mode, the access circuit selects one of the word-lines and determines whether to execute the refresh action for the cells coupled to the selected word-line according to the retention capability of the selected word-line at regular time intervals.

Abstract: A chip and a chip test system are provided by the present invention. The chip includes a decoding module and a test mode control module, and decodes an input signal to determine whether the input signal is a pre-activation signal or not. If the input signal is decoded into a pre-activation signal, then the chip will respond to a subsequent test signal; otherwise, the chip will not respond to any subsequent test signal. According to the present invention, by configuring a pre-activation signal, the number of chips to be simultaneously connected to and individually tested by the test equipment can be increased, without the need to occupy more input/output (I/O) interfaces.

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.

Abstract: Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction.

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

Abstract: This application provides a memory, a chip, and a method for storing repair information of the memory. The memory includes a repair circuit that is configured to receive a first signal from a processor and determine to be powered by a first power supply or a second power supply based on a status of the first signal, to store repair information. The repair information is information of the failed bit cells in the memory. The first power supply is zero or in a high impedance state when a system is powered off, and the second power supply is not zero when the system is powered off. The memory further comprises a processing circuit configured to perform communication between the memory and the processor based on the repair information. Therefore, the repair information of the memory can be stored even during power loss.

Abstract: An operation method of a memory including normal word lines and redundancy word lines may include receiving a row redundancy information and a flag signal along with an active command and a row address; and activating one of the redundancy word lines by decoding the row redundancy information according to a logic level of the flag signal.

Abstract: A semiconductor device includes memory cells, word lines, a row address decoder, word line drivers, a first switch transistor, and second switch transistors. The switch transistor is provided between the word line drivers and a power supply potential terminal. Each second switch transistor is provided between each word line and a reference potential terminal. The row address decoder activates all of decode signals corresponding to the memory cells to which a burn-in test is performed collectively. The first switch transistor has a lower driving capability than a total driving capability of two P-channel MOS transistors included in inverters of two word line drivers. Each second switch transistor has a lower driving capability than a driving capability of an N-channel MOS transistor included in the inverter of each word line driver.

Abstract: The present disclosure relates to an apparatus comprising a host device and a memory component coupled to the host device. The memory component can comprise an array of memory cells, and an interface comprising a boundary scan architecture, wherein the boundary scan architecture includes an instruction register configured to store data indicative of a presence of a test data input (TDI) signal.

Abstract: A memory device includes at least one die and a heater device. The heater device includes a first switch element electrically connected to a power supply connection and the at least one die, a second switch element electrically connected to the first switch element, and a resistive element electrically connected to the second switch element and a ground connection. A method includes configuring the first switching element of the heater device to electrically connect the second switching element of the heater device to a power supply connection, configuring the second switching element to electrically connect one of a first resistor or a second resistor of the resistive element to the first switching element, and applying a voltage across the first resistor or the second resistor that is electrically connected to the first switching element.

Abstract: Implementations described herein relate to indicating a status of the memory built-in self-test for multiple memory device ranks. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify a first data mask inversion (DMI) bit of the memory device that is associated with a first rank of the memory device and a second DMI bit of the memory device that is associated with a second rank of the memory device. The memory device may set the first DMI bit to a first value based on determining to perform the memory built-in self-test for the first rank of the memory device. The memory device may perform the memory built-in self-test for the first rank of the memory device based on setting the first DMI bit to the first value.

Abstract: A system for testing control units via simulation includes: a simulator; a host computer; and at least one connection for a communication system. At least one communication tool is stored on the system. Real control units are connectable to the system via the communication system. At least one controller is provided on the system for the connection to the communication system. Driver software for the at least one controller is stored on the system. The at least one communication tool is configured to generate communication code for communication between simulated control units and/or the real control units, wherein the communication code is configured to interact with the driver software and to relay signals and/or messages from the real and simulated control units to the driver software and to receive the signals and/or messages from the driver software. A loop mode is provided for the driver software.

Abstract: An electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder. An electroforming device performing electroforming through write operations to such a resistive memory and to a method for checking a write operation.

Abstract: A security device includes a physical unclonable function (PUF) cell array including PUF cells connected with word lines and bit lines; first decoder circuitry connecting a first bit line connected to a target PUF cell with a first data line and a second bit line connected with a reference PUF cell to a second data line; a digital-to-analog converter (DAC) control circuit outputting first and second digital codes; a first DAC between a power supply voltage and the first data line, the first DAC generating a first analog output in response to the first digital code; a second DAC between the power supply voltage and the second data line, the second DAC generating a second analog output in response to the second digital code; and a sense amplifier comparing the first analog output and the second analog output and outputting a comparison result.

Abstract: Implementations described herein relate to interrupting a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is to be interrupted while the memory built-in self-test is being performed using a test mode. The memory device may be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode but may not be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using a repair mode. The memory device may interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode.

Abstract: Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.