Abstract: Disclosed are a method and system for detecting a memory error, and a device. The method includes: taking an application platform as a test engine of a memory test device, the application platform being provided with a system memory; capturing, by the memory test device, a data flow of an actual application program of the application platform on a memory transmission line in a manner including a logic analyzer; and taking, by the memory test device, a processed data flow as a memory test vector to test a tested memory device, thereby reproducing a memory error of the application platform or the application program on the memory test device. The present disclosure can reproduce all tested memory devices with an error in the application platform, and improves a reproduction rate for the memory error.

Abstract: Disclosed is a device for correcting an erasure including a defect symbol location generating unit and an erasure decoding unit. The defect symbol location generating unit generates third information on a location of an erasure. The erasure decoding unit performs an erasure correcting operation on a read codeword read from a memory unit based on the third information.

Abstract: A method for updating stored information and an apparatus. A controller performs error correction code (ECC) decoding on stored data information based on the stored data information and stored ECC check information to generate an error-corrected codeword, where the error-corrected codeword includes error-corrected data information. The controller generates candidate to-be-written data information based on the error-corrected data information and a data update indication. The controller performs a mask operation on the candidate to-be-written data information based on the stored data information, and writes unmasked content in the candidate to-be-written data information into a memory.

Abstract: A method, a system, and computer program product for degradation-aware training of neural networks are provided. A degradation of degraded memory cells of a memory array is detected, during a training of a neural network. A first set of writing parameter values to be applied to the one or more degraded memory cells and a second set of writing parameter values to be applied to the undegraded memory cells is determined using a model of the memory array tuned to account for the degradation of one or more memory cells. A writing operation is executed, by applying the first set of writing parameter values to the one or more degraded memory cells to compensate for the degradation of the one or more degraded memory cells and by applying the second set of writing parameter values to the undegraded memory cell.

Abstract: A bus response to a bus request transmitted by a bus master over a network circuit is received by a bus response modifier. The bus response is transmitted by a bus slave and the bus request and the bus response are associated with a bus transaction over the network circuit. The bus response modifier selects a delay time to delay the bus response to fault test a system and the bus response is delayed by the delay time. A determination is made whether the fault test fails based on the delayed bus response.

Abstract: A memory device includes a test mode detector circuit that determines whether the memory device has entered a test mode based on at least one test mode entry signal received through at least one pin of a plurality of pins and generates a test mode detection signal, and a test pad connection circuit that electrically couples a first pin of the plurality of pins to a dedicated test pad of the test mode such that a signal applied to the first pin is transmitted to the dedicated test pad based on the test mode detection signal.

Abstract: According to an embodiment of the present disclosure, a semiconductor device includes an even data input circuit configured to store, in an even core cell, data that is input through an even data pad and that has a first pattern in response to an even data input strobe signal in a write operation of a parallel test. The semiconductor device includes an odd data input circuit configured to store, in an odd core cell, data that is input through the even data pad and that has a second pattern in response to an odd data input strobe signal in the write operation of the parallel test.

Abstract: Implementations described herein relate to indicating a status of the memory built-in self-test for multiple memory device ranks. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify a first data mask inversion (DMI) bit of the memory device that is associated with a first rank of the memory device and a second DMI bit of the memory device that is associated with a second rank of the memory device. The memory device may set the first DMI bit to a first value based on determining to perform the memory built-in self-test for the first rank of the memory device. The memory device may perform the memory built-in self-test for the first rank of the memory device based on setting the first DMI bit to the first value.

Abstract: A control method, for controlling a reading operation of a memory device, includes the following steps. A toggle signal is provided to the memory device, and the toggle signal has a toggle frequency. A reading operation of a page of the memory device is performed according to the toggle signal, wherein the page includes a plurality of chunks. The toggle frequency is set as a target toggle frequency, and the reading operation of a first chunk of the page is performed according to the target toggle frequency, so as to receive a data signal of the memory device. After the reading operation of the first chunk is completed, the toggle frequency is selectively adjusted to perform the reading operation of a second chunk after the first chunk according to a stable state of the data signal and the data strobe signal.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for dynamic column select swapping. A memory may have a number of sets of bit lines organized into column planes. If a set of bit lines associated with a first address in a first column plane is defective, it may be repaired by reassigning the first address to a redundant set of bit lines in a global column redundant (GCR) column plane. If a set of bit lines associated with the first address in a second column plane is also defective, then swap logic of the memory may swap the first address to a second address and assign it to the set of bitlines in the second column plane. The second address may then also be repaired by being reassigned to the GCR column plane.

Abstract: The memory device includes at least one memory block with a plurality of memory cells arranged in a plurality of word lines. The memory device includes control circuitry that is configured to program the memory cells of the at least one memory block in a plurality of program loops. The control circuitry is further configured to receive a command to write user data to the memory device. On at least a portion of a selected word line of the plurality of word lines, the control circuitry is configured to perform a smart verify operation to acquire a smart verify programming voltage. After the smart verify programming voltage is acquired, in a plurality of program loops, the control circuitry is configured to program the memory cells of the selected word line to include the user data and data that corresponds to the smart verify programming voltage.

Abstract: In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.

Abstract: Provided herein is a semiconductor device and a method of testing the semiconductor device. The method of operating a semiconductor device includes initializing a latch included in a page buffer, applying a read pass voltage to a plurality of word lines, allowing at least one of the plurality of word lines to float, and performing a sensing operation on the page buffer.

Abstract: A method for the automated selection of data sets for a method for machine learning for detecting operating variables of a motor vehicle, in which methods, measuring signal sequences for particular operating variable ranges of the motor vehicle, are detected during the operation of the motor vehicle. In the method, the operating variable ranges are assigned memory areas, each including multiple slots, each of which is configured to store a data set containing a detected measuring signal sequence, and data sets already stored in the slots being overwritable with data sets newly detected instantaneously for the same memory area in each case. For each slot of a memory area in which a data set is stored, an estimated slot error value is formed and stored together with the measuring signal sequence. The data sets, whose estimated slot error value is comparatively low, are preferably overwritten.

Abstract: An electronic device includes a monitoring signal generation circuit configured to receive an internal voltage to generate a monitoring signal, based on a voltage selection signal in a test mode, and an internal voltage drive circuit configured to receive the internal voltage and monitoring signal from the monitoring signal generation circuit and drive the internal voltage to compensate for the monitoring signal when the monitoring signal is distorted according to a leakage current in the test mode.

Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a set of memory cells coupled to a word line, and a tracking cell coupled to a tracking word line and a tracking bit line. In one aspect, the memory device includes a tracking booster circuit coupled to the tracking word line. In one aspect, the tracking booster circuit is configured to boost a first edge of a first pulse applied to the tracking word line. In one aspect, the tracking cell is configured to generate a second pulse at the tracking bit line, in response to the first pulse having the boosted first edge. In one aspect, the memory device includes a word line controller configured to apply a third pulse to the word line, based on the second pulse.

Abstract: Provided are method and device for testing product, computer device and readable storage medium, wherein in the first testing stage of testing cycle, for each processing machine, the total product number and the tested-product number of products processed by the processing machine are counted; the product testing rate of each processing machine is calculated; in the second testing stage, when machine with product testing rate lower than the preset threshold and machine with the product testing rate higher than the preset threshold appear, products in unprocessed products that meet the preset sampling rule are transferred to the processing machine whose product testing rate is lower than the preset threshold for being processed, and products that do not meet the preset sampling rule are transferred to the processing machine with the product testing rate higher than the preset threshold for being processed, until end of the testing cycle.

Abstract: A memory device includes a sense amplifying circuit coupled between a pull-up voltage line and a pull-down voltage line and configured to sense and amplify data of bit lines according to a sensing control signal; a fail detection circuit configured to calculate counting values of fail bits for each temperature based on the data and configured to generate a minimum error code for each temperature by detecting a minimum value for each temperature from the counting values for each temperature, in response to a test mode signal; and a sense amplifying control circuit configured to drive the pull-up voltage line and the pull-down voltage line by generating a pull-up voltage and a pull-down voltage corresponding to current temperature information based on the minimum error code for each temperature and configured to generate the sensing control signal according to the test mode signal.

Abstract: Embodiments of the disclosed technology relate to a memory system, a memory controller and a method for operating a memory system. According to the embodiments of the disclosed technology, a memory system may include a volatile memory accessed through a plurality of address fields, and divided into a plurality of subareas on the basis of a reference address field among the plurality of address fields; and a memory controller including a plurality of cores to which the plurality of subareas are allocated and which generate test signals corresponding to a test pattern. The memory controller may transmit the test signals generated in the plurality of cores, respectively, to the volatile memory.

Abstract: Systems and methods of anomaly detection in time-series are disclosed. A time-series dataset is received and a set of segments is iteratively defined from the time-series dataset by identifying a set of changepoints in the time-series dataset based on a changepoint type and a sensitivity parameter, determining whether the set of segments defined by the changepoints satisfy at least one threshold criteria, and modifying the sensitivity parameter when the threshold criteria is not met or outputting the set of segments when the threshold criteria is met. A segment-specific anomaly detection threshold is determined for each segment in the set of segments and a set of anomaly-flagged segments is generated. The set of anomaly flagged segments are generated by an anomaly detection process based on the segment-specific anomaly detection threshold for a corresponding segment. An anomaly-flagged time-series is generated by combining the set of anomaly-flagged segments.

Abstract: Described apparatuses and methods relate to selectively disabling a die that may be included in a multiple-die package without necessarily disabling all the remaining dies within the package. A nonvolatile circuit, such as one or more fuses, may be included within individual dies and/or otherwise incorporated within the package. The nonvolatile circuit maintains a value for the die that is indicative of the operability of the die. Die disablement logic is operatively coupled to the nonvolatile circuit and can disable the die based on the value indicating that the die is unusable. The disabling of the die by the die disablement logic may be controlled by an override signal that allows the disabling or prevents the logic from disabling the die. Thus, the die disablement logic can prevent a defective die from functioning, but the die disablement logic may be overridden for testing or debugging.

Abstract: Disclosed herein are methods, apparatuses and systems related to adjusting operation of memory dies according to reliability measures determined in real-time. The apparatus may be configured to determine the reliability measures based on (1) initiating and completing a programming operation within respective timings following an erase operation and (2) reading the programmed data within a window from completing the programming operation.

Abstract: A test circuit may include: a plurality of replication receivers configured to generate a plurality of oscillation signal pairs in response to a plurality of oscillation enable signals; and an oscillation control circuit configured to generate the plurality of oscillation enable signals in response to a test enable signal, and to generate a detection signal in response to any one of the plurality of oscillation signal pairs.

Abstract: A method for testing a chip includes writing, by a built-in self-test (BIST) circuit of the chip, a first row of a memory of the chip with a first set of values and reading, by the BIST circuit, a second row of the memory a first plurality of times. The second row is adjacent to the first row. The method also includes reading, by the BIST circuit, the first row to extract a second set of values from the first row and based on determining that at least one of the second set of values differs from a corresponding one of the first set of values, designating the first row as a vulnerable row.

Abstract: The embodiments of the present application provide a test board, which is applied in temperature and humidity tests for a memory module, and includes: a memory slot configured to be connected with the memory module; a power supply terminal configured to supply power to the memory module; an overcurrent protection unit connected in series between the memory slot and the power supply terminal and configured to be blown when the memory module is short-circuited; and an indicating unit connected in series between the overcurrent protection unit and a ground terminal and configured to indicate a state of the overcurrent protection unit. The embodiments of the present application provide a test board capable of indicating temperature and humidity test results.

Abstract: A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.

Abstract: An in-memory computing circuit includes an initial computing circuit and a target computing circuit. Herein, the initial computing circuit is configured to perform first operation processing on first data and second data to output a first operation result, and perform second operation processing on the first data and the second data to output a second operation result. The target computing circuit is configured to perform the first operation processing on the second operation result and the first operation result to output a first target result, and perform the second operation processing on the first data and the second operation result to output a second target result.

Abstract: A control method includes: decoding a third Operand (OP) in a third Mode Register (MR) and a fourth OP in a first MR; and in response to the semiconductor memory being in a preset test mode, controlling, in a case where the third OP meets a first decoding condition, the impedance of a Data Mask (DM) pin to be a first value; or controlling, in a case where the third OP meets a second decoding condition, the impedance of the DM pin to be a second value according to the fourth OP; wherein the third OP is configured to indicate whether the DM pin is a test object in the preset test mode, and the fourth OP is configured to indicate whether the DM pin is enabled.

Abstract: A dual-line cascade application system for simultaneously supplying electrical power and transmitting data, including a controller, cascade chips connected to the controller, and LED lights connected to the cascade chips. Each cascade chip is provided with a voltage clamp module, an electrical power supply module, a data storage module, a PWM constant current output driving circuit, an R end (Red LED output end), a G end (Green LED output end), a B end (Blue LED output end), a W end (White LED output end), a VCC/DATA end and a GND/DATA end, as well as a data sampling and calibration module, a power line data sampling and transmission module, a chip initial address setting by command module, a module which determines if E-fuse address of the chip is identical to an address of received data, and an E-fuse module which are sequentially connected. A method using the system is also provided.

Abstract: Device testing techniques including allocating a log memory, testing a device, and storing test result during testing of the device in the allocated log memory. The allocated log memory can be accessed through an application programming interface (API) during testing of the device, wherein the allocated log memory remains unlocked during testing of the device.

Abstract: Methods to test functional memory interface logic of a core under test utilize a built-in-self-test (BIST) controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at BIST mode, an at-speed functional mode is utilized to capture a desired memory output.

Abstract: A system and method are provided for driving a dual-rail memory circuit that operates with sensing of a memory bit cell, inversion of the sense signal and level shifting in four stage delays. The system includes inversion circuitry configured to (i) receive power from a first power rail (VDDA) of the dual-rail memory, (ii) receive an output of a sense amplifier that senses a state of a bit cell of the dual-rail memory, and (iii) provide two outputs (QB, QT) limited to the first power rail VDDA. The system further includes level-shifting circuitry configured to (i) receive the two outputs of the inversion circuitry (QB, QT). (ii) receive power from a second power rail of the dual-rail memory (VDDP) and (iii) drive an output (Q) in dependence on the two outputs of the inversion circuitry (QB, QT) and limited to the second power rail VDDP which is less than the first power rail VDDA.

Abstract: Embodiments of the present disclosure provide a control method, a semiconductor memory, and an electronic device. When the semiconductor memory is in a preset test mode, a first Model Register (MR) and a second MR related to a Data Pin (DQ) are allowed to directly define the impedance of a Data Mask Pin (DM). The DM does not need to add definition of an output driver state and a related control circuit for the preset test mode to ensure that the preset test mode is adapted to the DM. The impedance of the DM may be tested in the preset test mode to avoid circuit processing errors.

Abstract: According to one embodiment, a controller configured to manage second test information including status information indicating that a test related to a write operation and a read operation on a second storage area has not been executed. In response to receiving a command for acquiring information related to the second storage area from a host, the controller transmits the second test information to the host. When execution of the test on the second storage area is requested by the host, the controller executes the test related to the write operation and the read operation on the second storage area, and updates the status information of the second test information.

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

Abstract: A processing system employs techniques for enhancing dynamic random access memory (DRAM) page retirement to facilitate identification and retirement of pages affected by multi-page DRAM faults. In response to detecting an uncorrectable error at a first page of DRAM, the processing system identifies a second page of the DRAM for potential retirement based on one or more of physical proximity to the first page, inclusion in a range of addresses stored at a fault map that tracks addresses of DRAM pages having detected faults, and predicting a set of pages to check for faults based on misses at a translation lookaside buffer (TLB).

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

Abstract: An electronic device may include: a control pulse generation circuit configured to selectively generate one of a first control pulse and a second control pulse on the basis of a reference code during a test period; and a voltage control code generation circuit configured to perform an addition operation or subtraction operation on a logic bit set of a voltage control code to set the voltage level of an operation voltage on the basis of the first and second control pulses.

Abstract: A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.

Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.

Abstract: A method, device for checking data, an electronic device and a storage medium are provided. The method includes operations as follows. A memory array is read to obtain read data, and the read data is compressed to obtain first compressed data. The first compressed data is compared with second compressed data, the second compressed data being obtained by compressing written data corresponding to the read data. In responsive to that the first compressed data is consistent with the second compressed data, whether data of a predetermined bit in the read data is consistent with pre-stored original bit data is detected, to determine whether the read data is correct. It is determined that the read data is correct if the data of the predetermined bit is consistent with the pre-stored original bit data, otherwise it is determined that the read data is incorrect.

Abstract: A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.

Abstract: A selection device includes: a storage unit storing a plurality of types of amplifiers in advance; an acquisition unit for acquiring a plurality of selected amplifiers selected for driving a plurality of designated motors designated in advance; an alignment order selection unit for selecting a predetermined arrangement order in which the plurality of selected amplifiers are arranged adjacent to each other in the width direction on the basis of the types of the plurality of selected amplifiers; and a display control unit for causing a display unit to display the predetermined arrangement order.

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.

Abstract: An electronic device includes: a wiring board; an electric connection wiring connected to a power supply; motor connection wirings arranged on a peripheral side of the wiring board and connected to the electric motor; and semiconductor modules having semiconductor elements and a resin mold. The semiconductor modules are arranged at a position on the electric connection wiring or on the peripheral side of the electric connection wiring and on a center side of the motor connection wiring. At least a part of electrodes of the plurality of semiconductor modules is mounted on the electric connection wiring.

Abstract: A data writing method includes: receiving a first writing command, and selecting a target bank and a target column address according to the first writing command, data corresponding to the first writing command being first test data; writing the first test data into the target column address of the bank selected according to the first writing command, and latching the first test data on an address bus during the writing at least until a second writing command is executed; receiving the second writing command, and reselecting the target bank and the target column address according to the second writing command; and writing the first test data latched on the address bus into a reselected target column address of a reselected target bank.

Abstract: A test device method includes: setting a core voltage of a memory device to a first voltage value and a peripheral voltage of the memory device to a second voltage value; testing the memory device by accessing the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a third voltage value and the at least one peripheral voltage of the memory device to a fourth voltage value; testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a fifth voltage value and the at least one peripheral voltage of the memory device to a sixth voltage value; and testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage.

Abstract: A memory system for storage access monitoring is provided. The memory system includes a media controller of a memory. An analog persistent circuit is coupled to the media controller and configured to monitor access to the memory. The analog persistent circuit stores persistent data related to memory access counts access signals from the command/address bus. A command/address bus is coupled to the analog persistent circuit. A memory array is communicatively coupled to the command address and the media controller.