Abstract: A memory device includes: a plurality of sense amplifier circuits sensing a data bit in response to a parallel test signal from a plurality of banks; a plurality of comparators comparing the data bit from each of the plurality of sense amplifier circuits with a test bit; and a logic circuit receiving output signals of the plurality of comparators and outputting a test result, wherein each of the plurality of comparators receives the test bit, an evolved parallel bit test (PBT) signal, at least one test ignore signal, and a test pass signal, and compares the data bit and the test bit in response to the evolved parallel bit test (PBT) signal, the at least one logic state test setting signal, and the test pass signal, and passes a corresponding bank regardless of a test operation in response to the test pass signal.

Abstract: Instructions can be executed to adjust a trim at first intervals until a quantity of program/erase cycles (PEC) have occurred. The trim defines a valley width between data states. Instructions can be executed to adjust the trim at second intervals, greater than the first intervals, after the quantity of PEC have occurred.

Abstract: Methods, systems, and devices for voltage equalization for pillars of a memory array are described. In some examples, a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, and may be selectively coupled with an access line. To support a dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling, such as a coupling having a relatively high resistance or a degree of capacitance, with a ground voltage or other voltage source (e.g., to support a passive equalization). Additionally or alternatively, a memory array may be configured to support an active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition with a ground voltage or other voltage source (e.g., to perform a dynamic equalization).

Abstract: Implementing a hardware description language (HDL) memory includes determining, using computer hardware, a width and a depth of the HDL memory specified as an HDL module for implementation in an integrated circuit (IC), partitioning, using the computer hardware, the HDL memory into a plurality of super slices corresponding to columns and the plurality of super slices into a plurality of super tiles arranged in rows. A heterogeneous memory array may be generated, using the computer hardware. The heterogeneous memory array is formed of different types of memory primitives of the IC. Input and output circuitry configured to access the heterogeneous memory array can be generated using the computer hardware.

Abstract: A memory hank has banks of sense amplifiers positioned in edge memory array mats that are coupled to digit lines with different lengths than banks of sense amplifiers coupled between inner memory array mats. During a main sense phase of a sense operation, a first sense amplifier bank positioned between an edge memory array mat and an inner memory array mat is activated at a first time prior to activation of a second sense amplifier bank positioned in the edge memory array mat at a second time.

Abstract: A memory controller includes a core processor and a built-in self-repair (BISR) logic circuit. The core processor includes a register file with a plurality of register values corresponding to repair commands that control a self-repair operation of a memory device. The BISR logic circuit receives at least one of the plurality of register values from the core processor and converts the at least one of the plurality of register values into at least one of the repair commands to output the least one of the repair commands to the memory device. The core processor transmits the at least one of the plurality of register values to the BISR logic circuit in response to a firmware instruction that is output from an external firmware coupled to the memory controller.

Abstract: Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Abstract: The present application discloses an apparatus for repairing a defect of a memory module, comprises: a central buffer having an address recording module for recording defective address information indicating one or more defective memory addresses in the memory module; the central buffer is configured to receive an access command for accessing a target address in the memory module from a memory interface, and to determine whether to generate a repair access command for repairing the target address according to a comparison result; and a data buffer having a data recording module for recording repair data; wherein the data buffer is coupled between the memory interface and the memory module to buffer data interacted therebetween, and is coupled to the central buffer to receive the access command or the repair access command; the data buffer is configured to write target data associated with the access command into the data recording module as repair data corresponding to a target address according to the repair

Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

Abstract: Embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array including multiple planes, a peripheral circuit configured to perform an operation on the multiple planes, a control memory configured to store control codes for controlling the peripheral circuit, and a plurality of independent control logic configured to, when a command corresponding to each of the planes is received from a memory controller, control the peripheral circuit with reference to a control code corresponding to the command in response to the command. The control memory includes a common memory configured to be accessible in common by the plurality of independent control logic, and a temporary storage including areas respectively corresponding to the planes.

Abstract: Apparatus having a plurality of sets of memory devices and a multiplexer, wherein each set of memory devices of the plurality of sets of memory devices corresponds to a respective enable signal of a plurality of enable signals, wherein, for each set of memory devices of the plurality of sets of memory devices, each memory device of that set of memory devices is configured to receive commands in response to the respective enable signal for that set of memory devices having a particular logic level, and wherein, for each set of memory devices of the plurality of sets of memory devices, the multiplexer is configured to selectively connect input/output signal lines of that set of memory devices to an interface of the apparatus in response to the respective enable signal for that set of memory devices.

Abstract: Methods, systems, and computer readable mediums for selecting and configuring a computing system to support a replicated application are disclosed. According to one example, a method includes capturing resource availability data associated with a plurality of computing systems, wherein each of the plurality of computing systems resides at a separate and distinct geographical site. The method further includes determining, for each of the plurality of computing systems, a suitability score based on the captured resource availability data and at least one external factor associated with the computing system, selecting one of the plurality of computing systems to host the replicated application based on the determined suitability scores, and establishing a logical environment on the selected computing system to support the enterprise application.

Abstract: An array substrate and a fabrication method thereof, an array substrate motherboard, and a display device are disclosed. The array substrate includes a display region and a bonding region outside the display region. The array substrate further includes: a bonding electrode, located in the bonding region and spaced apart from an outer edge of the bonding region; and an electrostatic barrier line, the electrostatic barrier line has one end electrically connected with the bonding electrode, and the other end extends to the outer edge of the bonding region, and resistivity of the electrostatic barrier line is greater than resistivity of the bonding electrode.

Abstract: A memory device includes a first pad, a second pad, and a double data rate (DDR) test controller. The first pad may receive a write enable signal. The second pad may receive a data strobe signal. The DDR test controller is connected to the first pad and the second pad and outputs an internal write enable signal and an internal data strobe signal. The DDR test controller generates the internal data strobe signal based on the write enable signal received through the first pad, in at least a portion of a DDR test operation of the memory device.

Abstract: A test method for a memory device including a plurality of memory cells includes generating a first test pattern, performing a first pattern write operation of writing the first test pattern in the plurality of memory cells, reading first data from the plurality of memory cells in which the first test pattern was written, generating a second test pattern based on the first data, and performing a second pattern write operation of writing the second test pattern in the plurality of memory cells. The second test pattern is generated such that a write operation is skipped with regard to failure cells from among the plurality of memory cells at which a write failure occurs, during the second pattern write operation.

Abstract: An apparatus for power supply mode switching includes a first voltage regulator to output a first voltage, a second voltage regulator to output a second voltage, a third voltage regulator to output a third voltage, an electronic load, a first switch between the first voltage regulator and the electronic load, a second switch between the second voltage regulator and the electronic load, and a third switch between the third voltage regulator and the electronic load. And, a method for power supply mode switching includes supplying power to an electronic load with a first voltage; switching to a second voltage; maintaining coupling of the electronic load with the second voltage while a voltage across the electronic load is less than a reference voltage; and switching to a third voltage when the voltage is greater than or equal to the reference voltage and the third voltage is less than the second voltage.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reclaiming one or more portions of storage resources in a computer system serving one or more virtual computing instances, where the storage resources in the computer system are organized in clusters of storage blocks. In one aspect, a method includes maintaining a respective block tracking value for each storage block that indicates whether a call to reclaim the storage block is outstanding; determining, from the block tracking values, a respective cluster priority value for each of the clusters based on a count of storage blocks in the respective cluster for which a call to reclaim is outstanding; and reclaiming a first portion of storage resources in the computer system in accordance with the cluster priority values.

Abstract: An apparatus includes a memory sub-system comprising a plurality of memory blocks and a memory block defect detection component. The memory block defect detection component is to set, for a memory block among the plurality of memory blocks, a first block defect detection rate and determine whether the first block defect detection rate is greater than a threshold block defect detection rate for the at least one memory block. In response to a determination that the first block defect detection rate is greater than the threshold block defect detection rate for the memory block, the memory block defect detection component is to assert a program command on the memory block determine whether a program operation associated with assertion of the program command on the at least one memory block is successful.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor word line characteristics. In one embodiment, the memory device includes a memory array including a word line (e.g., a local word line) and a word line driver coupled thereto. When the memory device activates the word line driver, the memory device may generate a diagnostic signal in response to the word line voltage reaching a threshold. Further, the memory device may generate a reference signal to compare the diagnostic signal with the reference signal. In some cases, the memory device may generate an alert signal based on comparing the diagnostic signal with the reference signal if the diagnostic signal indicates a symptom of degradation in the word line characteristics. The memory device may implement certain preventive and/or precautionary measures upon detecting the symptom.

Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

Abstract: Various implementations described herein are directed to a device having memory with a first array and a second array. The device may have power rails formed in frontside metal layers that supply core voltage to the memory. The power rails may include a first path routed through a first frontside metal layer to the first array of the memory, and the power rails may include a second path routed through the first frontside metal layer and a second frontside metal layer to the second array of the memory.

Abstract: A device includes at least one tunable resistive element. Each tunable resistive element comprises a first terminal, a second terminal, and a dielectric layer arranged between the first and second terminals. The device is configured to apply at least one electrical set pulse to the resistive elements to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer. The device is configured to apply at least one electrical reset pulse to displace a subset of the oxygen vacancies of the conductive filament. The at least one electrical reset pulse comprises a first part, which is adapted to increase the temperature of the conductive filament and increase the mobility of the oxygen vacancies of the conductive filament, and a second part, which is configured to displace the subset of the oxygen vacancies of the conductive filament.

Abstract: The disclosure performs a pre-test that checks electrical connections between each electrical contact of the socket and the corresponding pin of the semiconductor chip during a pre-test stage before a burn-in test. The electrical connection between each of the electrical contacts and each of the pins may be checked through multiple signal channels. Even when one of the signal channels failed, the pre-test and the burn-in test may still be performed as long as another one of the signal channels passes the pre-test. In addition, the pre-test stage through multiple signal channels also provides information for determining whether the failure of semiconductor chip is caused by the electrical connection between the socket of the burn-in board or the semiconductor chip itself.

Abstract: Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event.

Abstract: A memory device includes: first power pins in a first power area and configured to receive a first power voltage; data pins configured to transmit or receive data signals, the data pins being arranged in a first region and in a second region each including the first power area; control pins configured to transmit or receive control signals in the first region and in the second region; second power pins in a second power area between the first region and the second region and configured to receive a second power voltage different from the first power voltage; and ground pins in the second power area and configured to receive a ground voltage.

Abstract: A method of testing using a memory test apparatus connected to a memory device includes receiving a test command. When the test command is a finite state machine (FSM) operation command, the memory device is tested in accordance with the FSM operation command, and an operation is performed to output a result depending on a pass/fail result. But, when the test command is a direct access command, an auto-operation test of input data is performed in a test region according to received address information, and a test result is output, which may include output data with fail information or the auto-operation.

Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract: The present invention provides an improved testing of a complex device under test, in particular a parallel analysis of signals of a device under test. Multiple signals of the device under test may be acquired and characteristic parameters of the acquired signals may be determined. The determined characteristic parameters of the multiple signals may be stored. In particular, the characteristic parameters may be stored in form of an array, table or spread sheet.

Abstract: A boost direct current-to-direct current (DC-DC) converter using a delta-sigma modulator (DSM), the boost DC-DC converter may comprise a boost driving circuit outputting an output voltage to output terminals by boosting an input voltage, a resistance distribution circuit outputting a feedback voltage by distributing the output voltage of the boost driving circuit, a compensator outputting a compensated feedback voltage by compensating for the feedback voltage outputted by the resistance distribution circuit based on a reference voltage, a delta-sigma modulator outputting a digital signal by modulating the compensated feedback voltage and a duty controller outputting a duty control signal for controlling a switching duty of the boost driving circuit by receiving the output of the delta-sigma modulator.

Abstract: According to one embodiment, a semiconductor integrated circuit includes: a first core that includes a first logic circuit that has a plurality of first scan chains, and a first generator that generates a first test pattern; a second core that includes a second logic circuit that has a plurality of second scan chains, and a second generator that generates a second test pattern; a controller that controls a test operation of the first and second cores. The controller is configured to: obtain a seed for a test pattern from the first generator; supply the obtained seed to the second generator; perform a test on the first and second cores for a same number of cycles; obtain first and second test results respectively from the first and second cores; and compare the first and second test results.

Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

Abstract: A memory system and an operating method thereof are provided. The memory system includes a storage device including a mode register suitable for activating or inactivating an auto mode and a memory suitable for storing data, and a storage device controller controlling the mode register to enter a test mode, after inactivating the auto mode, during a test operation of the storage device, and controlling the mode register to activate the auto mode again when the test operation of the storage device is completed.

Abstract: Provided herein may be a test circuit, a memory device, a storage device, and a method of operating the same. The word line test circuit may include an operation signal generator configured to generate a plurality of operation signals in response to a test command, a comparison result generator configured to, in response to the plurality of operation signals, generate a target voltage based on a test current, in which a current of a target word line varying with a test voltage is reflected, and to generate a comparison signal based on a result of a comparison between the target voltage and a reference voltage, and a word line defect detector configured to detect a defect in the target word line based on at least one reference count and a count of a reference clock, cycles of which are counted until a level of the comparison signal changes from a first level to a second level.

Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.

Abstract: A ground bounce generator includes a resistor and at least one switch coupled in parallel with the resistor. The ground bounce generator is in a device under test circuit including a source, at least one ground bounce generator, at least one device under test, and a ground. The device under test is coupled in series between the source and the ground bounce generator. The device under test and the ground bounce generator are coupled in series between the source and the ground.

Abstract: Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint.

Abstract: Systems, apparatus and methods are provided for an error correction code (ECC) architecture with reduced decoding latency in error control. An apparatus may comprise control circuitry configured to receive a status report that a decoding task has failed, determine that a higher priority is needed for a re-decoding task, generate a NAND read task having a second priority level higher than a first priority level of the failed decoding task, and generate an ECC re-decoding task having the second priority level.

Abstract: An electronic device includes a memory device receiving a power supply voltage, a data strobe signal, and a data signal, and a system-on-chip that exchanges data with the memory device using the data strobe signal and the data signal. The system-on-chip performs write training that measures a magnitude of a delay of the data strobe signal due to variation in the level of the power supply voltage and adjusts a delay of the data signal using a result of the write training.

Abstract: A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.

Abstract: A memory system includes: a plurality of nonvolatile memories; a controller connected to the plurality of nonvolatile memories via a plurality of channels that includes a plurality of memory physical layer circuits arranged corresponding to the plurality of channels, respectively, one or more pads for calibration corresponding to the plurality of memory physical layer circuits, and a processor that controls the plurality of memory physical layer circuits. A single reference resistor is connected to the plurality of memory physical layer circuits via the pad. An output based on a ZQ calibration of the plurality of memory physical layer circuits is wired-OR connected to the single reference resistor via the one or more pads. The processor performs a calibration for each of the plurality of memory physical layer circuits in a time division manner using the single reference resistor.

Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

Abstract: A diagnostic system may utilize telemetry from a monitored system to infer information about the operation of various components systems within the monitored system. In embodiments, inferences may be drawn from a comparison of various component systems using a system of implication and exoneration. Exoneration is utilized to isolate faulty components from functioning components by comparing information between the systems, which may run in parallel. A dynamic grouping algorithm may eventually isolate faulty components and suggest the root cause as well as multiple distinct faults.

Abstract: Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections. In exemplary aspects disclosed herein, to allow cross-connections to be made across different gates between PMOS and NMOS transistors formed in the circuit cell, cut areas in the circuit cell are located in different horizontal routing tracks and offset from each other in the direction of longitudinal axes of gates. Gate cross-connections can be routed around offset gate cut areas and coupled to active gates to form gate cross-connections. In this manner, fewer metal layers may be required to provide such cross-connections in the circuit cell, thus reducing area. Further, gate contacts of cross-connected gates can be formed as gate contacts over active areas (GCOAs) in diffusion areas of the circuit cell, thus facilitating easier routing of interconnections in non-diffusion area of the circuit cell for further ease of routing.

Abstract: A memory with a test function and a method thereof. The memory includes a memory array having cells, input buffers divided into even- and odd-numbered groups and output buffers divided into even- and odd-numbered groups; at least two data input pads, respectively providing test data to the cells through the even-numbered and the odd-numbered input buffers; a first and a second logic gates, respectively performing a first logic operation on outputs of the even-numbered and odd-numbered output buffers; a third logic gate, performing a second logic operation on outputs of the first and the second logic gates; and at least one data output pad, coupled to an output of the third logic gate for providing a test result of the cells.

Abstract: A system, method and apparatus for measuring carrier lifetime of a device comprises subjecting a test device to a voltage via a voltage source associated with the test system, disconnecting the test device from the voltage source, measuring the voltage as a function of time, measuring the current as a function of time, and determining a carrier lifetime of the test piece according to the slope of the measured voltage and the measured current.

Abstract: Disclosed approaches for measuring memory performance include inputting respective sets of parameter values for master circuits. Each set specifies control over a transaction issuance rate, a transaction size, or an address pattern. Configuration data is generated for implementing master circuits in programmable logic circuitry based on the sets of parameter values. Each master circuit is configured to issue memory transactions according to the respective set of parameter values. The programmable logic circuitry is configured with the configuration data, and the master circuits are activated. Each master circuit issues memory transactions based on the respective set of parameter values. Each master circuit measures performance metrics of memory circuitry in processing the memory transactions and stores data indicative of the performance metrics.

Abstract: Apparatuses and methods related to memory authentication. Memory devices can be authenticated utilizing authentication codes. An authentication code can be generated based on information stored in a fuse array of the memory device. The authentication code can be stored in the memory device. The stored authentication code can be compared to a captured authentication code based on fuse array information broadcast to memory components of the memory device. The authenticity of the memory device can be determined based on the comparison and can result in placing the memory device in an unlocked state.

Abstract: A component subsystem and a method for authenticating the component subsystem. The component subsystem may be installed in a host device. The method can include an authentication protocol, wherein the host device sends a test voltage value to the component subsystem which, in turn, generates a test voltage based on the test voltage value. The test voltage is applied to a test cell that includes a wordline, a bitline, and a memory film. A response voltage is read from the bitline and compared to an expected value. If the response voltage matches the expected value, host device and/or component subsystem functionality is enabled. If the response voltage does not match the expected value, the host device and/or component subsystem functionality is disabled.