Testing Patents (Class 365/201)
  • SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME
    Publication number: 20140347940
    Abstract: Semiconductor devices are provided. The semiconductor device includes a control signal generator and a first data input unit. The control signal generator generates an inverted control signal including a first bit and a second bit using a decoded signal in response to a test enable signal. The first data input unit inverts a first bit of input data in response to the first bit of the inverted control signal to generate a first bit of first internal data. Further, the first data input unit inverts a second bit of the input data in response to the second bit of the inverted control signal to generate a second bit of the first internal data.
    Type: Application
    Filed: September 13, 2013
    Publication date: November 27, 2014
    Applicant: SK hynix Inc.
    Inventor: Hee Won KANG
  • METHODS AND APPARATUSES FOR STACKED DEVICE TESTING
    Publication number: 20140347944
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dies arranged in a stack in which the dies or a logic chip in communication with the dies stores a flag for indicating whether a threshold number of cells of the dies have failed during test operations.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Boon Hor Lam, Dennis Montierth
  • Nonvolatile logic array with built-in test result signal
    Patent number: 8897088
    Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 25, 2014
    Assignee: Texas Instrument Incorporated
    Inventors: Steven Craig Bartling, Sudhanshu Khanna
  • Semiconductor memory device
    Patent number: 8897081
    Abstract: A semiconductor memory device includes a pad configured to receive a first write data from outside of the semiconductor memory device, and a write circuit configured to generate a plurality of second write data which are to be written in memory cells of all banks to be tested in response to a test mode signal, data strobe signals, a write enable signal, and the first write data transferred through the pad.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: November 25, 2014
    Assignee: SK Hynix Inc.
    Inventors: Young-Jun Ku, Ki-Ho Kim
  • SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SEMICONDUCTOR INTEGRATED CIRCUIT
    Publication number: 20140340975
    Abstract: A semiconductor integrated circuit is provided with: a memory under test; a test-result-storage memory; a test-data generation part for generating in a sequential manner a test address signal and test data for supplying to the memory under test; and a control circuit. The control circuit includes a delay circuit, which, when the control circuit stores in a sequential manner in the test-result-storage memory a test result according to the test address signal and test data in the memory under test, delays the storage-destination address signal in the test-result-storage memory from the test address signal set in the memory under test, in accordance with a time delay that includes at the least the latency from the setting of the test address signal in the memory under test to the reading out of the test data.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Inventor: Keigo NAKATANI
  • SEMICONDUCTOR CIRCUIT AND LEAKAGE CURRENT TEST SYSTEM
    Publication number: 20140340971
    Abstract: A semiconductor circuit includes a test control unit configured to generate a driving activation signal and a sensing activation signal in response to a command and an address; a pad; a driver configured to drive the pad to a predetermined level in response to activation of the driving activation signal; and a sensing unit configured to compare a voltage level of the pad with a reference voltage in response to activation of the sensing activation signal, and output a sensing signal.
    Type: Application
    Filed: September 4, 2013
    Publication date: November 20, 2014
    Applicant: SK hynix Inc.
    Inventors: Jung Taek YOU, Min Joo YOO
  • Memory system with a layer comprising a dedicated redundancy area
    Patent number: 8891322
    Abstract: Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising a second layer memory element and a second layer fuse box coupled to the first redundant memory element. In addition, these systems and methods may further include a redundancy register coupled to the first layer, wherein upon the failure of part of the second layer memory element, the redundancy register provides information to the fuse blowing control that allocates part of the first redundant memory element to provide redundancy for the failed part of the second layer memory element by blowing elements in the first layer fuse box and the second layer fuse box.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: November 18, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hong Beom Pyeon
  • Lifetime mixed level non-volatile memory system
    Patent number: 8891298
    Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: November 18, 2014
    Assignee: Greenthread, LLC
    Inventor: G. R. Mohan Rao
  • Semiconductor memory device capable of measuring write current and method for measuring write current
    Patent number: 8891323
    Abstract: A method for measuring a write current of a semiconductor memory device includes the steps of: programming initial data into memory cells which are to be programmed substantially at the same time; determining whether the memory cells are programmed into the same state or not; inputting test data when the memory cells are programmed into the same state; setting write current paths of the memory cells by comparing the initial data and the test data; and measuring a write current consumed when the test data are programmed into the memory cells.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 18, 2014
    Assignee: SK Hynix Inc.
    Inventors: Chang Yong Ahn, Ho Seok Em
  • Non-volatile memory, method of operating the same, memory system including the same, and method of operating the system
    Patent number: 8885409
    Abstract: A nonvolatile memory device includes an array of nonvolatile memory cells and a plurality of page buffers configured to receive a plurality of pages of data read from the same page in the array using different read voltage conditions. A control circuit is provided, which is electrically coupled to the plurality of page buffers. The control circuit is configured to perform a test operation by driving the plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits, which are derived from a comparison of at least two of the multiple pages of data read from the same page of nonvolatile memory cells using the different read voltage conditions. An input/output device is provided, which is configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Hoon Lee, Hyun Seok Kim, Sung-Hwan Bae, Jong-Nam Baek, Jae Yong Jeong
  • Semiconductor memory device and method of driving the same
    Patent number: 8885436
    Abstract: Disclosed is a semiconductor memory device, including a plurality of internal voltage generation units configured to be enabled in response to each of a plurality of decoding signals and to generate an internal voltage, a controller configured to generate a plurality of control signals in response to a power up signal and a test mode signal, and a decoder configured to generate the plurality of decoding signals corresponding to at least one decoding source signal and to simultaneously activate some or all of the plurality of decoding signals in response to the control signals.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: November 11, 2014
    Assignee: SK Hynix Inc.
    Inventors: Yeon-Uk Kim, Hee-Joon Lim
  • Compression of content entries in storage for replacing faulty memory cells
    Patent number: 8885426
    Abstract: A method of manufacturing a dynamic random access memory device is provided. The method includes testing a DRAM device using a testing process. The method includes identifying, under control by a computing device, a plurality of bad memory cells from the DRAM device and determining a list of addresses associated with the plurality of bad memory cells. The method includes sorting the list of addresses in either ascending or descending order and subjecting the information from the sorted list of address to a compression process, under control by the computing device, to provide a compressed format including a first content entry in the sorted list and a series of off-set values as provided by a recurrence relationship. The method also stores the compressed format into a non-volatile memory.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: November 11, 2014
    Assignee: Inphi Corporation
    Inventors: Andrew Burstein, Nirmal Saxena, Javier Villagomez
  • MEMORY MARGIN MANAGEMENT
    Publication number: 20140328132
    Abstract: A method for testing and correcting a memory system is described. The method includes selecting a target memory unit of the memory system having a timing margin in response to a trigger to start a timing margin measurement. The stored data in the target memory unit is moved to a spare memory unit. The memory system performs reads and writes of user data from the spare memory unit while measuring the target memory unit. The timing margins of the target memory unit are measured. The reliability of the measured timing margins of the target memory unit based on a timing margin profile is determined.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Electronic circuit for remapping faulty memory arrays of variable size
    Patent number: 8879295
    Abstract: A memory under repair having variable size blocks of failed memory addresses is connected to a TCAM comprising cells storing data values of ranges of the failed memory addresses in the memory under repair. The TCAM is connected to a virtual address line. Matchlines in the TCAM drive wordlines in a RAM connected to the TCAM. Each entry in the TCAM corresponds to one entry in the RAM and represents a single block of failed memory addresses. A first input of an XOR gate in an integrated circuit device is operatively connected to the RAM and a second input is operatively connected to the virtual address line. Responsive to a virtual address being an address in one of the ranges of failed memory addresses, the XOR gate calculates a physical memory address redirecting the virtual address to an unused good memory location in place of the failed memory address.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Dean L. Lewis
  • Microprocessor mechanism for decompression of fuse correction data
    Patent number: 8879345
    Abstract: An apparatus includes a semiconductor fuse array and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed configuration data. The array has a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores the configuration data in an encoded and compressed format. The second plurality of fuses stores first compressed fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the array and accesses all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: November 4, 2014
    Assignee: Via Technologies, Inc.
    Inventors: G. Glenn Henry, Dinesh K. Jain
  • Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs
    Patent number: 8873318
    Abstract: Failure bit map (FBM) data and a built-in-self-test-repair (BISTR) module enable collecting and analyzing FBM data of an entire memory to identify the best repairing method (or mechanism) to make repairs. As a result, the repair method is better and more efficient than algorithms (or methods) known to the inventors, which only utilize partial (or incomplete) failure data. At the same time, the compressed data structures used for the FBMs keep the resources used to capture the FBM data and to repair the failed cells relatively limited.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Volodymyr Shvydun, Saman M. I. Adham
  • Address output circuit and semiconductor memory device
    Patent number: 8873319
    Abstract: A semiconductor memory device includes a signal generation unit configured to generate a toggling signal and first and second pulse signals in response to a test signal and a burst pulse signal. An address output unit may be configured to receive first to fourth input addresses and output sequentially first to fourth output addresses in response to the toggling signal and the first and second pulse signals. A repair unit may be configured to perform a repair operation on a word line selected by the first to fourth output addresses.
    Type: Grant
    Filed: March 3, 2012
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Sang Il Park
  • Semiconductor apparatus
    Patent number: 8873313
    Abstract: A semiconductor apparatus includes: a memory cell block configured to store data; a fuse block including a plurality of fuses configured to store fuse information; an I/O driver configured to output the data transmitted through a global line to a pad; and a fuse driver configured to output the fuse information transmitted through a test global line to the pad during a test mode.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hong Gyeom Kim
  • Method of refreshing a memory device, refresh address generator and memory device
    Patent number: 8873324
    Abstract: A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-Woo Park, Joo-Sun Choi, Hong-Sun Hwang
  • Semiconductor memory device having data compression test circuit
    Patent number: 8873305
    Abstract: A semiconductor memory device includes a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal, and a transmission element configured to transmit second input data only to the second global line driver in response to the test signal.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Bok Rim Ko
  • INTEGRATED CIRCUIT WITH PROGRAMMABLE STORAGE CELL ARRAY AND BOOT-UP OPERATION METHOD THEREOF
    Publication number: 20140313841
    Abstract: An integrated circuit may include a first programmable storage cell group suitable for storing program validity information, second to N-th programmable storage cell groups suitable for storing a plurality of data, wherein N is an integer equal to or more than 3, and a validity determination unit suitable for determining whether the program validity information read from the first programmable storage cell group is valid or not so that read operations for the second to N-th programmable storage cell groups is performed or skipped based on the determined result.
    Type: Application
    Filed: August 16, 2013
    Publication date: October 23, 2014
    Applicant: SK hynix Inc.
    Inventors: Joo-Hyeon LEE, Jun-Hyun CHUN, Ho-Uk SONG
  • Apparatuses, integrated circuits, and methods for measuring leakage current
    Patent number: 8867290
    Abstract: Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first voltage, and a measurement node is charged to a second voltage, the second voltage being less than the first voltage. The measurement node is proportionally coupled to the word line. A voltage on the measurement node is compared with a reference voltage. A signal is generated, the signal being indicative of the comparison. Whether a leakage current of the word line is acceptable or not can be determined based on the signal.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: October 21, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Test circuit and method of semiconductor memory apparatus
    Patent number: 8867287
    Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jin Youp Cha, Jae Il Kim
  • Chip with embedded non-volatile memory and testing method therefor
    Patent number: 8867289
    Abstract: A testing method for a chip with an embedded non-volatile memory and the chip is provided. A remapping circuit and the non-volatile memory are connected to a processor. The non-volatile memory has a test area and an area under test. The test area stores a test program, and the area under test stores data under test. When the processor tests the chip, the processor outputs an original instruction address, and the remapping circuit remaps the original instruction address to generate a remapped instruction address. The processor reads the test program in the test area, and executes the test program to read the data under test in the area under test and to perform a test of toggling the logic circuit.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: October 21, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Yen Wu, Chi-Chun Hsu, Po-Sen Huang, Li-Ren Huang, Wen-Dar Hsieh
  • Memory device and test method thereof
    Patent number: 8867288
    Abstract: A method for testing a memory device includes entering a test mode in which multiple memory banks operate in a same manner, allowing a row corresponding to a row address in the multiple memory banks to be activated, latching a bank address and the row address corresponding to the multiple memory banks, writing same data in a column selected by a column address in the multiple memory banks, reading the data written in the writing of the data from the multiple memory banks, checking whether the data read from the multiple memory banks in the reading of the data are equal to each other, and programming the bank address and the row address to a nonvolatile memory when the data read from the multiple memory banks are different from each other.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyunsu Yoon, Jeongsu Jeong, Youncheul Kim, Gwangyeong Stanley Jeong, Hyunju Yoon
  • Semiconductor apparatus with open bit line structure
    Patent number: 8867282
    Abstract: A semiconductor apparatus with an open bit line structure includes a memory bank including a plurality of memory cell blocks and dummy mats, in which a plurality of bit lines are formed, a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference, and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventors: Tae Sik Yun, Kee Teok Park
  • Repairable multi-layer memory chip stack and method thereof
    Patent number: 8867286
    Abstract: A repairable multi-layer memory chip stack wherein each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus, and correspondingly outputs a decoded address. The memory array module determines whether to allow a data bus to access the data of the memory array module corresponding to a decoded address in accordance with an activation signal of the control unit. The redundant repair element includes a valid field, a chip ID field, a faulty address field and a redundant memory. When the valid field is valid, the value of the chip ID field matches the ID code, and the value of the faulty address field matches the decoded address, the redundant memory is coupled to the data bus.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: October 21, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Hsueh Wu, Kun-Lun Luo, Chen-An Chen, Yee-Wen Chen
  • CIRCUIT ARRANGEMENT, A METHOD FOR TESTING A SUPPLY VOLTAGE PROVIDED TO A TEST CIRCUIT, AND A METHOD FOR REPAIRING A VOLTAGE SOURCE
    Publication number: 20140307515
    Abstract: A circuit arrangement may include: a memory, composed of a memory cell array, including a plurality of memory cells, and a peripheral circuitry; a voltage source configured to provide at least one supply voltage; a test circuit integrated with the memory cell array and the voltage source, wherein the test circuit receives the supply voltage; the test circuit including: at least one test memory cell; at least one failure detection circuit configured to detect a data retention failure in the at least one test memory cell.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 16, 2014
    Inventors: Leonardo Henrique Bonet Zordan, Alberto Bosio, Patrick Girard, Nabil Badereddine
  • Memory testing with selective use of an error correction code decoder
    Patent number: 8862953
    Abstract: A method includes directing an access of a memory location of a memory device to an error correction code (ECC) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location. The method further includes determining whether a fault is detected at the memory location based on a comparison of the test pattern and the value.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Gollub, Girisankar Paulraj, Diyanesh B. Vidyapoornachary, Kenneth L. Wright
  • Immunity of phase change material to disturb in the amorphous phase
    Patent number: 8861293
    Abstract: Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: October 14, 2014
    Assignee: Ovonyx, Inc.
    Inventors: George A. Gordon, Semyon D. Savransky, Ward D. Parkinson, Sergey Kostylev, James Reed, Tyler A. Lowrey, Ilya V. Karpov, Gianpaolo Spadini
  • Verification read data output circuit of a semiconductor device and method for operating the same
    Patent number: 8861286
    Abstract: A semiconductor device and a method for operating the same are provided relating to a nonvolatile memory device for sensing data using resistance change. The semiconductor device comprises a verification read control unit configured to sequentially output verification read data received from a sense amplifier into a global input/output line in response to a test signal, and a read data latch unit configured to store sequentially the verification read data received from the global input output line in response to a latch enable signal in activation of the test signal.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: October 14, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jung Hyuk Yoon, Dong Keun Kim
  • Defect detection on characteristically capacitive circuit nodes
    Patent number: 8860425
    Abstract: A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Liang-Teck Pang, William Robert Reohr, Phillip John Restle
  • Method and apparatus for increasing yield
    Patent number: 8861248
    Abstract: Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: October 14, 2014
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Eran Rotem
  • Storage cell bridge screen technique
    Patent number: 8861294
    Abstract: A semiconductor memory includes a circuit block that is configured to receive a test mode command, a first sense amplifier that is coupled to sense and amplify a state of a first memory cell when enabled, and a second sense amplifier that is coupled to sense and amplify a state of a second memory cell when enabled. In an active cycle, the circuit block generates one or more control signals in response to the test mode command that cause the second sense amplifier to be enabled a predetermined amount of time after the first sense amplifier is enabled.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: October 14, 2014
    Assignee: SK hynix Inc.
    Inventors: TaeHyung Jung, KeeSoo Kim
  • SEMICONDUCTOR MEMORY DEVICE HAVING COMPRESSION TEST MODE
    Publication number: 20140301149
    Abstract: A semiconductor memory device having a compression test mode is provided. The semiconductor memory device comprises a memory unit, i test pads, a timing circuit, a compression circuit, and a signal distribution circuit. The memory unit comprises m memory banks divided into n activating groups, wherein each bank comprises a plurality of sensing amplifiers for sensing and amplifying data in bit lines. The timing circuit sequentially generates n control signals each for activating a plurality of sensing amplifiers in one of the n activating groups. The compression circuit compresses data sensed and amplified by the plurality of sensing amplifiers in each bank in a compression test mode. The signal distribution circuit distributes signals output from the compression circuit among the i data pads in rotation. The integer n and the integer i are adjustable.
    Type: Application
    Filed: April 9, 2013
    Publication date: October 9, 2014
    Applicant: Elite Semiconductor Memory Technology Inc.
    Inventor: Jen-Shou HSU
  • TECHNIQUES FOR CONTROLLING RECYCLING OF BLOCKS OF MEMORY
    Publication number: 20140301143
    Abstract: In operation, respective lifetime expectancy scores are calculated for each of a plurality of blocks of a memory based on a respective count percentage of free space of each of the blocks. The blocks are recycled based on at least some of the life expectancy scores. A total amount of the blocks that are re-written is minimized while equalizing lifetime expectancy score variation between the blocks.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 9, 2014
    Applicant: LSI CORPORATION
    Inventor: Radoslav Danilak
  • Method for detecting and correcting errors for a memory whose structure shows dissymmetrical behavior, corresponding memory and its use
    Patent number: 8856603
    Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 7, 2014
    Assignees: European Aeronautic Defence And Space Company EADS France, Astrium SAS
    Inventors: Florent Miller, Thierry Carriere, Antonin Bougerol
  • Semiconductor memory device and method of testing the same
    Patent number: 8854909
    Abstract: A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: October 7, 2014
    Assignee: SK Hynix Inc.
    Inventor: Suk Min Kim
  • Apparatuses and methods for comparing a current representative of a number of failing memory cells
    Patent number: 8854898
    Abstract: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jae-Kwan Park
  • Semiconductor device for supplying and measuring electric current through a pad
    Patent number: 8854907
    Abstract: The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device capable of supplying and measuring an electric current through a pad. The semiconductor device includes a memory cell, a data pad configured to receive data to be programmed into the memory cell or a write current to be supplied to the memory cell from an external device, and output data read out from the memory cell or a cell current flowing from the memory cell to the external device, and a path switching unit configured to set up a path so that the memory cell and the data pad are directly coupled when a test operation is performed.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 7, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sang Kug Lym, Dong Keun Kim
  • Nonvolatile memory device with improved integrated ratio
    Patent number: 8854906
    Abstract: A nonvolatile memory device includes a number of page buffer groups each comprising a number of normal page buffers, I/O lines corresponding to the respective normal page buffers, and a column decoder generating a column address decoding signal for coupling the normal page buffers of one of the page buffer groups and the respective I/O lines in response to a normal control clock signal.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: October 7, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong Deok Cho
  • System and method for memory access in server communications
    Patent number: 8854908
    Abstract: A random access memory includes a plurality of memories configured to store and provide data, and a test module coupled to the plurality of memories, wherein the test module is configured to write a first write data pattern into at last a first portion of the plurality of memories in response to a data pattern value, wherein the test module is configured to read a read data pattern from the plurality of memories, wherein the test module is configured to compare the first write data pattern to the read data pattern, and wherein the test module is configured to report errors in response to a comparison of the write data pattern to the read data pattern.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 7, 2014
    Assignee: Inphi Corporation
    Inventors: Andrew Burstein, David Wang
  • Method for optimizing refresh rate for DRAM
    Patent number: 8848471
    Abstract: A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras, Moinuddin K. Qureshi
  • Semiconductor device and test method thereof
    Patent number: 8848473
    Abstract: A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 30, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Naohisa Nishioka
  • Fabrication and testing method for nonvolatile memory devices
    Patent number: 8848472
    Abstract: A plurality of master chips are arranged in a row on the wafer, each master chip including a power supply circuit providing a power supply voltage, and a plurality of slave chips are arranged in a column to at least one side of a corresponding master chip among the plurality of master chips, each slave chip including a memory cell array functionally operative in response to the power supply voltage provided by the corresponding master chip during wafer level testing.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hiroshi Sugawara
  • Semiconductor device and testing method thereof
    Patent number: 8848469
    Abstract: A semiconductor device includes a plurality of cell blocks activated in response to a plurality of selection signals, respectively, a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and activate at least two of the pre-selection signals by decoding addresses in a multi-test mode, a selection signal controller configured to selectively activate the plurality of selection signals in response to the plurality pre-selection signals and control active periods of the activated selection signals so as not to overlap, and a decision circuit configured to decide whether or not the cell blocks activated in response to the activated selection signals are repaired in response to stored repair information and the plurality of selection signals.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 30, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Bo-Yeun Kim, Ji-Eun Jang
  • Integrated circuit chip and semiconductor memory device
    Patent number: 8842486
    Abstract: An integrated circuit chip includes an internal circuit configured to generate output data, an inversion determination unit configured to activate/deactivate an inversion signal according to state information regarding a state of the integrate circuit chip, and a signal output circuit configured to invert or not to invert the output data in response to the inversion signal and output the inverted or non-inverted output data.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 23, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang-Ho Do
  • Automated control of opening and closing of synchronous dynamic random access memory rows
    Patent number: 8842480
    Abstract: An apparatus including a protocol engine and a built-in self test (BIST) engine. The built-in self test (BIST) engine is coupled to the protocol engine. The built-in self test (BIST) engine may be configured to directly control when to open and close rows of a synchronous dynamic random access memory (SDRAM) during double data rate (DDR) operations.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: September 23, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jackson L. Ellis, Shruti Sinha
  • MEMORY WITH BIT LINE CURRENT INJECTION
    Publication number: 20140269124
    Abstract: Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector. The current injector may be configured to generate multiple current levels and may be operable to controllably select one of the current levels to either source current to or sink current from the input of the sense amplifier.
    Type: Application
    Filed: May 30, 2014
    Publication date: September 18, 2014
    Applicant: Apple Inc.
    Inventors: Michael R. Seningen, Michael E. Runas
  • Semiconductor device including integrated circuit
    Patent number: 8836360
    Abstract: A semiconductor device that can be manufactured with reduced costs and that includes a first connecting terminal, a second connecting terminal, a third connecting terminal, and a first circuit module configured to operate in response a first signal and a second signal. When a mode signal is in a first state, the first circuit module receives the first signal from the first connecting terminal and receives the second signal from the second connecting terminal. Otherwise, when the mode signal is in a second state, the first circuit module receives the first signal from the first connecting terminal and receives the second signal from the third connecting terminal. A memory module including at least one such memory device may also be provided.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-ju Oh