Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

Abstract: A scalable, reconfigurable Memory Built-In Self-Test (MBIST) architecture for a semiconductor device, such as a multiprocessor, having a Master and one or more Slave MBIST controllers is described. The MBIST architecture includes a plurality of MBISTDP interfaces connected in a ring with the Master MBIST controller. Each MBISTDP interface connects to at least one Slave controller for forwarding test information streamed to it from the Master MBIST controller over the ring. Test information includes test data, address, and MBIST test commands. Each MBISTDP interface forwards the information to the Slave controller attached thereto and to the next MBISTDP interface on the ring. Test result data is sent back to the Master MBIST controller from the MBISTDP interfaces over the ring.

Abstract: A security circuit may include a functional circuit including a test chain that connects flip-flops to verify hardware of the functional circuit, the functional circuit configured to generate an output signal by encrypting an input signal based on a control signal, a mode signal, and the chain; and/or a test controller configured to generate the input, control, and mode signals, and configured to generate an authentication result based on the output signal. A security circuit may include a first device including a plurality of flip-flops in a test chain, the first device configured to receive first, second, and third signals, and configured to generate a fourth signal by encrypting the first signal based on the second and third signals and the chain; and/or a second device configured to generate the first, second, and third signals, and configured to generate an authentication result based on the fourth signal.

Abstract: A memory circuit is provided. The memory circuit includes a memory array, a plurality of word lines and a memory controller. The memory array has a plurality of memory blocks. The memory controller outputs an access instruction and an access address to address the word lines for accessing the memory array, or the memory controller outputs a refresh instruction and a refresh address to address the word lines for refreshing the memory array, wherein the memory controller performs a refresh operation on each of the memory blocks corresponding to each of the word lines at predetermined intervals. The memory controller counts the number of times the access instructions have been output and determines whether that number equals a predetermined value or not. According to the determination result, the memory controller selects an address adjacent to the access address as the refresh address for the next refresh operation.

Abstract: Assist circuits for SRAM memory tests allow voltage scaling in low-power SRAMs. Word line level reduction (WLR) and negative bit line (NBL) boost assist techniques improve read stability and write margin of SRAM core-cells, respectively, when the memory operates at a lowered supply voltage. Assist circuits are activated at particular points in the memory cell circuit. The assist circuits are selectively activated for modifying the voltage along particular circuit elements to identify the potential defects that might be otherwise masked until substantially large. A March test invokes elements for activating the assist circuits to identify defects and indicate functional fault models (FFMs) associated with the defects.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A semiconductor device includes a test port configured to communicate with a test system, a test command controller coupled to communicate with the test port, a peripheral module configured to communicate with the test command controller, a processor, and a test memory configured to communicate with the test command controller and the processor. The test command controller is configured to issue a first set of one or more instructions to test the peripheral module and to issue a second set of one or more instructions to the processor to process information in the test memory resulting from the test of the peripheral module.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a first memory cell transistor; a first bit line; a first sense amplifier unit; a voltage generator; and a switch circuit. In a case where a power-supply voltage is equal to or lower than a first voltage and is higher than a second voltage when an access operation to the first memory cell transistor is started, the first sense amplifier unit is electrically disconnected from the first bit line and is electrically connected to the voltage generator via the switch circuit.

Abstract: A semiconductor memory device and a memory module have a reconfiguration preventing function. The semiconductor memory device may include a memory cell array, a test information storing unit, and a control unit. The control unit may include a control signal storing unit and may prevent programming of the test information storing unit according to a control signal stored in the control signal storing unit.

Abstract: The method of transferring data between a first and a second set of elements via a switch that includes a set of paths each associated with a weighting coefficient representing a data stream for each path. The method includes a credit flow control between the first set of elements and the switch and a credit flow control between the switch and the second set of elements. An available credit coefficient is computed for each element of the first set on the basis of a credit allocated by each element of the second set and of the weighting coefficient of each path.

Abstract: In an operating method for a display device in a vehicle, the display device includes a touch-sensitive surface. A first output is displayed in an area of the display device. A first movement and a second movement by an operator relative to the touch-sensitive surface are detected simultaneously. The area is divided automatically along a first direction into a first subarea and a second subarea, if the first movement and the second movement proceed substantially in a second direction perpendicular to the first direction and away from each other. The first output is displayed in the first subarea and a second output is displayed in the second subarea.

Abstract: An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes normal-retention storage rows that exhibit retention times greater or equal to a first time interval, and having been tested to generate information identifying low-retention storage rows that exhibit retention times less than the first time interval. Refresh logic refreshes the normal-retention storage rows at a first refresh rate corresponding to the first time interval, and refreshes each low-retention storage row at a second refresh rate that is greater than the first refresh rate.

Abstract: A circuit, configured to detect faults in an array of data storage elements, comprises: a resistor network; a switching network for selectively coupling a specified portion of the resistor network to the array of data storage elements; a current monitoring module, where the current monitoring module is operable to monitor current flow through the specified portion of the resistor network; and a control module coupled to the switching network and the current monitoring module. The control module is operable to control the switching network, so as to couple the specified portion of the resistor network to the array of data storage elements, and to determine whether one or more predefined characteristics of the output of the current monitoring module meet predetermined fault criteria. The control module is further operable to initiate one or more remedial actions, when the one or more predefined characteristics meet the predetermined fault criteria.

Abstract: A semiconductor system includes a semiconductor device comprising: a plurality of first input pins suitable for receiving a plurality of command/address signals; a plurality of multi-purpose registers; and a parity check unit suitable for determining a parity check result as a pass when the number of first logic values in the command/address signals corresponds to a logic value of a parity bit, determining the parity check result as a fail when the number of the first logic values does not correspond to the logic value of the parity bit, and controlling the command/address signals to be stored in the multi-purpose registers; and a function test device suitable for applying the command/address signals to the first input pins during a function test, and controlling the command/address signals such that the number of the first logic values does not correspond to the logic value of the parity bit.

Abstract: A power supply system includes a power source and a power extending board detachably connected between the power source and an electronic device. The power source includes at least two outputs. The power extending board includes at least two first transmitting terminals and a second transmitting terminal connected to the two first transmitting terminals. Each of the two outputs transmits a first driving voltage from the power source to the second transmitting terminal via a corresponding first transmitting terminal. The first driving voltages from the power source are identical to each other. The second transmitting terminal transmits a second driving voltage to the electronic device. The second driving voltage is identical to each of the first driving voltages.

Abstract: This technology includes: a refresh signal generation unit configured to generate a first preliminary refresh signal with a cycle varying according to temperature changes; a magnification adjustment unit configured to generate a second preliminary refresh signal and a third preliminary refresh signal, which have a cycle variation slope equal to the first preliminary refresh signal and have cycle magnifications different from the first preliminary refresh signal according to the first preliminary refresh signal; and a selection unit configured to output one of the first preliminary refresh signal, the second preliminary refresh signal, and the third preliminary refresh signal as a refresh signal according to a control signal.

Abstract: A semiconductor memory device includes; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Abstract: A semiconductor memory apparatus includes: a user setting unit configured to generate test data and a delay control signal in response to an external command and an external address; a delay locked loop (DLL) clock generation unit including a replica configured to have a delay time controlled in response to the delay control signal; and a data output unit configured to output the test data in response to a DLL clock signal outputted from the DLL clock generation unit.

Abstract: An embodiment provides a method, including: reading validity timing information written to a non-volatile memory device; and determining validity of the non-volatile memory device using the validity timing information read from the non-volatile memory device. Other aspects are described and claimed.

Abstract: A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state.

Abstract: A semiconductor memory apparatus may include a read/write circuit unit configured to receive an external voltage, to read data from a memory cell array, and to generate a pre-read signal, while an internal voltage is generated during a test mode, and a controller configured to selectively drive a write circuit unit in response to the pre-read signal.

Abstract: A memory device may include an address latch circuit that latches an address received from an exterior of the memory device, a repair signal generation circuit that generates a soft repair signal, a selection information generation circuit that generates first selection information by using first bits of a latched address latched by the address latch circuit, first to Nth register circuits that store second bits of the latched address as repair data by being selected by the first selection information when the soft repair signal is activated, and first to Nth memory blocks that perform repair operations using the repair data stored in the respective first to Nth register circuits.

Abstract: The described embodiments include a memory with a memory array and logic circuits. In these embodiments, logical operations are performed on data from the memory array by reading the data from the memory array, performing a logical operation on the data in the logic circuits, and writing the data back to the memory array. In these embodiments, the logic circuit is located in the memory so that the data read from the memory array need not be sent to another circuit (e.g., a processor coupled to the memory, etc.) to have the logical operation performed.

Abstract: Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block.

Abstract: A semiconductor device includes a nonvolatile memory block suitable for outputting data stored in a plurality of nonvolatile memory cells included therein based on first control information, and programming data in the nonvolatile memory cells based on second control information; a control block suitable for generating the first control information based on an initialization signal, wherein the control block sequentially generates the second control information and the first control information when a program mode is activated; and a test control block suitable for deactivating the nonvolatile memory block and determining whether at least one control signal among a plurality of control signals included in the first and second control information is normally generated, in a test operation on the program mode.

Abstract: If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit 12 includes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FF1 provided in a subsequent stage of a flip-flop FF0, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FF1 and output of the flip-flop FFT. Test data tv1 and test data tv2 are input to the malfunction pre-detecting circuit 12 in an operation test mode for testing operation of the malfunction pre-detecting circuit 12. The test data tv2 is input to the delay circuit DL. The comparator CMP compares the test data tv1 and output of the flip-flop FFT in the operation test mode.

Abstract: A non-volatile memory device includes a two-dimensional array of non-volatile memory cells where a first portion of memory cells being configured as an one-time-programmable memory area; a bypass read-out circuit configured to sense a signal level on a bit line in response to a memory cell in the one-time-programmable memory area being selected and to generate a first signal indicative of the signal level on the bit line; and a trim data latch circuit having an input terminal configured to receive the first signal. The trim data latch circuit is configured to store a signal related to the first signal as a trim data value and to provide trim data value to circuitry of the non-volatile memory device. The trim data value may be applied to adjust a signal level of the circuitry of the non-volatile memory device.

Abstract: A method of operating a non-volatile memory device includes erasing a memory cell block, supplying a first drain turn-on voltage higher than a target level to the drain select line of the memory cell block, and performing a soft program operation by supplying a soft program voltage to the word lines of the memory cell block.

Abstract: A method of testing interconnected dies can include forming a cell for the interconnected dies, applying at least a first input to the cell to perform an open or short defects test, and applying at least a second input to the cell to perform one or more of a resistive defects test or a burn-in-test. Test circuitry for testing an interconnection between interconnected dies can include a wrapper cell embedded within a die where the wrapper cell includes a scannable data storage element, a hold data module, a selection logic, a transition generation module, and one or more additional input ports for receiving inputs causing the wrapper cell to perform an open or short defects test in a first mode and causing the wrapper cell to perform one or more of a resistive defects test in a second mode or a burn-in-test in a third mode.

Abstract: A semiconductor memory device includes a plurality of memory cells electrically coupled to a plurality of word lines and a word line failure detection unit suitable for supplying a test voltage to a test target word line selected from among the plurality of word lines, and for detecting the test voltage transferred from at least one of the plurality of word lines, wherein the at least one of the plurality of word lines does not include the test target word line.

Abstract: A semiconductor device includes a plurality of chips comprising a plurality of I/O terminals connected in common via through electrodes. Each of the chips includes an I/O compression circuit operable to output a compression result obtained by compression of data of a plurality of internal data buses to a first I/O terminal of the plurality of I/O terminals. Each of the chips also includes a test control circuit having a register group that sets the number of the first I/O terminal. Setting information that assigns different first I/O terminals to different chips is set in the register group. Each of the chips inputs or outputs data with use of the number of the I/O terminal that is different from those in other chips. Thus, the I/O compression circuits can concurrently perform an I/O compression test in parallel in the plurality of chips without a bus fight.

Abstract: A flash memory, a flash memory system, and an operating method thereof. The method of operating a flash memory includes counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range (defined by a first reference read voltage for distinguishing between initially separated adjacently located threshold voltage distributions and a first search read voltage having a first voltage difference from the first reference read voltage), and a second adjacent threshold voltage range (defined by the first reference read voltage and a second search read voltage having a second voltage difference from the first reference read voltage), and setting a first optimal read voltage based on the difference between the first and second counted numbers of the memory cells.

Abstract: A semiconductor memory device may include a memory cell, a bit line connected to the memory cell, a bit line data latch circuit configured to sense-amplify data stored in the memory cell connected to the bit line and to store write data in the memory cell via the bit line; an input/output driver configured to output read data on the bit line to an external device or to drive the write data provided from the external device; and a selection unit configured to select whether the read data and the write data are communicated between the input/output driver and the memory cell with or without use of the bit line data latch circuit.

Abstract: An overclocking process for a data storage device using a flash memory. A controller for the flash memory tests the flash memory using test clocks with various frequencies to determine at least one clock signal suitable to the flash memory. The clock candidates suitable to the flash memory are selected from the test clocks. The flash memory is operated in a variable-frequency manner by which the flash memory is switched between the clock candidates, such that electromagnetic interference is spread over different bands.

Abstract: Provided is a flash memory device capable of efficiently performing a refresh operation. The flash memory device includes a normal memory array including a plurality of normal memory cells arranged in a matrix of word lines and bit lines, wherein the plurality of normal memory cells are divided into a plurality of memory blocks and are programmable and erasable; a refresh address generation unit configured to generate a refresh block address, wherein the refresh block address is sequentially increased in response to activation of a refresh driving signal; and a refresh driving unit driven to refresh a memory block specified by the refresh block address among the memory blocks of the normal memory array in a unit refresh frame, and generate the refresh driving signal. In the flash memory device, a refresh operation may be efficiently performed to fix a data disturbance.

Abstract: An embodiment of a method for detecting permanent faults of an address decoder of an electronic memory device including a memory block formed by a plurality of memory cells, including the steps of: selecting an address, which identifies a selected set of memory cells; writing at the selected address a code word generated on the basis of an information word, of the selected address, and of an error-correction code; and then detecting an error within a word stored at the selected address. The method moreover includes the steps of: selecting a set of excitation addresses; writing a test word at the selected address, and then writing an excitation word at each excitation address; and next comparing the test word with a new word stored at the selected address.

Abstract: A data storage device includes a nonvolatile memory device, an error correction code unit suitable for detecting and correcting a data error read from the nonvolatile memory device in response to an operation clock, and a clock unit suitable for selectively providing the operation clock to the error correction code unit depending on whether the data is read from the nonvolatile memory device or not.

Abstract: A nonvolatile memory system and a method for using programming time to reduce bit errors in the nonvolatile memory system are disclosed. The method includes programming a plurality of memory cells of a nonvolatile memory device, identifying weak cells using programming time and preventing subsequent programming to the identified weak cells.

Abstract: Semiconductor devices are provided. The semiconductor device includes a control signal generator and a first data input unit. The control signal generator generates an inverted control signal including a first bit and a second bit using a decoded signal in response to a test enable signal. The first data input unit inverts a first bit of input data in response to the first bit of the inverted control signal to generate a first bit of first internal data. Further, the first data input unit inverts a second bit of the input data in response to the second bit of the inverted control signal to generate a second bit of the first internal data.

Abstract: Multiple measurements are made with one memory sense operation having a first word line sensing voltage on a memory cell. The multiple measurements include a first measurement, of whether the memory cell stores either: (a) data corresponding to a first set of one or more threshold voltage ranges below the first word line sensing voltage of the one memory sense operation, or (b) data corresponding to a second set of one or more threshold voltage ranges above the first word line sensing voltage of the one memory sense operation. The multiple measurements include a second measurement, of error correction data of the memory cell indicating relative position within a particular threshold voltage range of a stored threshold voltage in the memory cell.

Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.

Abstract: Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit. The test controller can be Joint Test Action Group-compatible. An isolation signal is generated using the power manager. The isolation signal can comprise at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit. The isolation signal can be stored in a boundary scan register controlled with the test controller. The main power domain is isolated from a power-collapsible domain of the integrated circuit with the isolation signal. Power of the power-collapsible domain is collapsed. When power is collapsed, the power-collapsible domain is tested using the test controller and the power manager.

Abstract: A method writes data in a resistive memory device in which paths for performing write operations to record first-state data and second-state data are controlled to cause current to flow in opposing directions in a resistive memory cell whose switching type has been determined. The method includes performing a write operation in a predetermined direction when writing the first-state data and second-state data, making a determination with respect to success in target data through verification, and attempting an additional write operation through a path reversed from a write path of corresponding data according to a result of the determination.

Abstract: A first erase test is performed by applying an erase pulse to series of memory cells which are included in a memory cell array and which are divided into a plurality of groups until the appearance of a group for which the determination that erase is completed is made. A second erase test is performed on other series of memory cells including the series of memory cells on the basis of the number of erase pulses at the time of detecting a group for which the determination that erase is completed is made first.

Abstract: A data storage device (DSD) includes a non-volatile memory (NVM) media for storing data. A last resort zone of the NVM media is associated with a higher risk of data loss or data corruption than other portions of the NVM media and is reserved as unavailable for storing data. It is determined whether a current data storage capacity and/or an environmental condition for the NVM media has reached a threshold. The last resort zone is set as available for storing data if it is determined that the threshold has been reached and data is written in the last resort zone.

Abstract: An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access.

Abstract: An object is at least one of a longer data retention period of a memory circuit, a reduction in power consumption, a smaller circuit area, and an increase in the number of times written data can be read to one data writing operation. The memory circuit has a first field-effect transistor, a second field-effect transistor, and a rectifier element including a pair of current terminals. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of the pair of current terminals of the rectifier element is electrically connected to a source or a drain of the second field-effect transistor.

Abstract: A semiconductor memory device and method of operation are provided for a multi-bank memory array (100) with an address fault detector circuit (24, 28) connected to split word lines (WLn-WLm) across multiple banks, where the address fault detector circuit includes at least a first MOSFET transistor (51-54) connected to each word line for detecting an error-free operation mode and a plurality of different transient address faults including a “no word line select,” “false word line select,” and “multiple word line select” failure mode at one of the first and second memory banks. In selected embodiments, the address fault detector provides resistive coupling (33-40) between split word lines across multiple banks to create interaction or contention between split word lines to create a unique voltage level on a fault detection bit line during an address fault depending on the fault type.