Complementing/balancing Patents (Class 365/202)
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Patent number: 7978551Abstract: A bit line equalizing control circuit of a semiconductor memory apparatus includes a control signal generating unit that receives a bank active signal to generate a control signal such that a bit line equalizing signal is delayed and enabled, a bit line equalizing selecting unit that generates a bit line equalizing detection signal in response to a plurality of mat select signals and the control signal, and a driver that receives the bit line equalizing detection signal to generate the bit line equalizing signal.Type: GrantFiled: December 30, 2008Date of Patent: July 12, 2011Assignee: Hynix Semiconductor Inc.Inventor: Woo-Seok Song
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Patent number: 7961499Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.Type: GrantFiled: January 22, 2009Date of Patent: June 14, 2011Assignee: QUALCOMM IncorporatedInventors: Manish Garg, Chiaming Chai, Michael ThaiThanh Phan
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Patent number: 7957204Abstract: A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.Type: GrantFiled: September 20, 2005Date of Patent: June 7, 2011Assignee: Spansion LLCInventors: Yonggang Wu, Guowei Wang, Nian Yang, Sachit Chandra, Aaron Lee
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Patent number: 7948819Abstract: Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.Type: GrantFiled: September 25, 2007Date of Patent: May 24, 2011Assignee: Agere Systems Inc.Inventors: Mathew R. Henry, Douglas D. Lopata, Richard J. McPartland, Hai Quang Pham, Wayne E. Werner
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Patent number: 7940599Abstract: A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.Type: GrantFiled: March 16, 2009Date of Patent: May 10, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Olga R. Lu, Lawrence F. Childs, Thomas W. Liston
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Patent number: 7936618Abstract: The memory circuit comprises at least one memory element (T1), a sense amplifier (SA) for sensing a state of the memory element (T1), a switching device (T2) for selectively coupling the sense amplifier (SA) to the memory element (T1), The sense amplifier (SA) comprises a first module (M1) and a second module (M2). The first module (M1) provides a first current limited to a maximum value (Iref+Ibias). The second module (M2) provides a second current which decreases from a value higher than the maximum value at the start of a sensing operation until a value lower than the maximum value at the end of the sensing operation. The memory circuit has a third module (CS2) for sinking a third current (Ibias) at a side of the switching device (T2) coupled to the memory element (T1).Type: GrantFiled: April 19, 2007Date of Patent: May 3, 2011Assignee: NXP B.V.Inventor: Maurits Storms
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Patent number: 7933138Abstract: A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.Type: GrantFiled: January 30, 2009Date of Patent: April 26, 2011Assignee: Texas Instruments IncorporatedInventors: Hugh P. McAdams, Scott R. Summerfelt
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Patent number: 7911823Abstract: A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.Type: GrantFiled: May 20, 2008Date of Patent: March 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takuya Futatsuyama, Koji Hosono, Toshiaki Edahiro, Naoya Tokiwa, Kazushige Kanda, Shigeo Ohshima
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Patent number: 7898881Abstract: A semiconductor memory device includes first and second edge drivers configured to generate sensing control signals, a memory cell array between first and second edge drivers, and pluralities of unit sense amplifiers detecting data from the memory cell array in response to the sensing control signals.Type: GrantFiled: July 23, 2008Date of Patent: March 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hwa Choi, Byung-Sik Moon
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Patent number: 7898887Abstract: A sense amplifier includes a first sensing element and a second sensing element redundant to the first sensing element. The sense amplifier further comprises a switch circuit configured to switch between the first and second sensing elements when an offset of the sense amplifier is greater than a prescribed amount.Type: GrantFiled: August 29, 2007Date of Patent: March 1, 2011Assignee: Agere Systems Inc.Inventors: Dennis E. Dudeck, Donald Albert Evans, Hai Quang Pham, Wayne E. Werner, Ronald James Wozniak
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Patent number: 7894287Abstract: The present invention relates to a semiconductor memory device, and more precisely to a semiconductor memory device which controls the voltage supplied to a dummy bit line and a biasing method. The semiconductor memory device includes a dummy bit line disposed in a cell array and a switching unit which switches the supply of a bias voltage to the dummy bit line by a control signal related to an operation of the cell array.Type: GrantFiled: January 3, 2008Date of Patent: February 22, 2011Assignee: Hynix Semiconductor Inc.Inventor: Young Soo Kim
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Patent number: 7889532Abstract: In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a signal difference between a bit line and a complementary bit line. The first voltage drivers apply a power source voltage to the first sense amplifier, and the second voltage driver applies a ground voltage to the second sense amplifier. The first voltage drivers are disposed for every two or more sense amplifier blocks in a bit line sense amplifier region in which the sense amplifier blocks are arranged, and the second voltage driver is disposed in a conjunction region in which a control circuit is located to control the sense amplifier blocks. Both capacitive noise and device size are minimized.Type: GrantFiled: August 21, 2009Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyang-Ja Yang, Su-Yeon Kim
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Patent number: 7869239Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.Type: GrantFiled: April 3, 2008Date of Patent: January 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Sun Min, Kyu-Chan Lee, Chul-Woo Yi, Jong-Hyun Choi
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Patent number: 7864598Abstract: In one embodiment, a semiconductor memory device includes a plurality of pairs of bit lines, each of said pairs including a first bit line, a second bit line, a memory cell coupled to said first bit line, a sense amplifier determining the logical value stored in the memory cell according to a potential difference between the first and the second bit line, a reference voltage generation circuit, and a reference voltage supply switch coupling an output of the reference voltage generation circuit to the second bit line.Type: GrantFiled: February 4, 2008Date of Patent: January 4, 2011Assignee: Renesas Electronics CorporationInventors: Hiroyuki Takahashi, Atsushi Nakagawa
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Patent number: 7865325Abstract: A test system and a failure parsing method. The test system may comprise a cell array including defective cells formed according to various failure causes, a test apparatus configured to measure electric characteristics from the defective cells and make the measured electric characteristics numerical, and a database apparatus configured to store the numerical electric characteristics. The failure parsing method may include forming defective cells to have at least one failure cause, measuring electric characteristics of each of the defective cells, storing the measured electric characteristics of each of the defective cells in a database, and judging failure causes of a failed chip of a semiconductor wafer based on the database.Type: GrantFiled: April 25, 2008Date of Patent: January 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hyun Lee, Soo-Yong Lee
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Publication number: 20100322025Abstract: A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second digit line to the terminated end of the first digit line. The memory array is configured with the first and second digit lines arranged directly adjacent to each other.Type: ApplicationFiled: August 27, 2010Publication date: December 23, 2010Applicant: MICRON TECHNOLOGY, INC.Inventor: Werner Juengling
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Patent number: 7852694Abstract: A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second bit line in response to a sense amplifier enable signal. The precharge unit may precharge voltage levels of the first bit line and the second bit line to a precharge voltage level in response to a precharge enable signal. The equalizing circuit may be connected to the sense amplifier and the precharge unit and may control the voltage levels of the first bit line and the second bit line to be equal to each other in response to the sense amplifier enable signal. The semiconductor memory device may reduce a time required to perform a precharge operation and/or minimize an increase of the circuit size.Type: GrantFiled: June 11, 2008Date of Patent: December 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-hoon Jung, Gyu-hong Kim
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Patent number: 7848160Abstract: A semiconductor storage device includes a plurality of memory cells connected to first and second column trees, and a sensing circuit reading data from the memory cells. The sensing circuit performing a read operation by electrically connecting the column tree, which is connected to a read-selected memory cell, to a sensing node and electrically connecting the column tree, which is connected to a non-selected memory cell, to a reference sensing line.Type: GrantFiled: December 12, 2008Date of Patent: December 7, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Masao Kuriyama
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Patent number: 7826288Abstract: In a method for reducing and/or eliminating mismatch in one or more devices that require a balanced state (e.g., in cross-coupled transistors in each memory cell and/or sense amp in a memory array), the bias (i.e., the preferred state) of each of the devices is determined. Then, a burn-in process is initiated, during which an individually selected state is applied to each of the devices. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories.Type: GrantFiled: March 9, 2007Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Igor Arsovski, Harold Pilo, Michael A. Ziegerhofer
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Patent number: 7821858Abstract: In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.Type: GrantFiled: December 2, 2008Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Richard E. Matick, Stanley E. Schuster
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Patent number: 7813196Abstract: An integrated semiconductor memory contains a multiplicity of bit line pairs which each comprise a first bit line and a second bit line. Sense amplifiers are each coupled to one of the bit line pairs for evaluating a signal on the first and second bit lines. A data line pair coupled to at least one of the multiplicity of bit line pairs for outputting a datum is furthermore provided. A correction device is connected on the output side to the data line pair or to at least one bit line pair. The device is embodied for feeding a correction signal onto the line pair.Type: GrantFiled: January 29, 2008Date of Patent: October 12, 2010Assignee: Qimonda AGInventors: Rüdiger Brede, Arne Heittmann
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Patent number: 7800965Abstract: A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second digit line to the terminated end of the first digit line. The memory array is configured with the first and second digit lines arranged directly adjacent to each other.Type: GrantFiled: March 10, 2008Date of Patent: September 21, 2010Assignee: Micron Technology, Inc.Inventor: Werner Juengling
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Patent number: 7796425Abstract: A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.Type: GrantFiled: November 19, 2007Date of Patent: September 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Gil Choi, Choong-Keun Kwak, Woo-Yeong Cho
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Patent number: 7787324Abstract: A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line.Type: GrantFiled: October 11, 2007Date of Patent: August 31, 2010Assignee: Marvell World Trade Ltd.Inventors: Sehat Sutardja, Jason T. Su, Hong-Yi Chen, Jason Sheu, Jensen Tjeng
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Patent number: 7778062Abstract: A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate as underlying the cell array for data reading and writing, wherein the variable resistance element comprises a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d” orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less.Type: GrantFiled: June 12, 2007Date of Patent: August 17, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Koichi Kubo
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Patent number: 7773431Abstract: One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal.Type: GrantFiled: December 18, 2008Date of Patent: August 10, 2010Assignee: Texas Instruments IncorporatedInventors: Radu Avramescu, Sumanth Gururajarao, Hugh Thomas Mair
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Patent number: 7773401Abstract: A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data registers are respectively connected to the two groups of the nonvolatile memory cells. The compare circuit is connected to the two groups of the data registers, for performing a comparison to generate a compare result.Type: GrantFiled: April 24, 2008Date of Patent: August 10, 2010Assignee: MACRONIX International Co., Ltd.Inventors: Jian-Yuan Shen, Chi-Ling Chu, Chou-Ying Yang
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Patent number: 7764531Abstract: A method and circuit for implementing precise eFuse resistance measurement, and a design structure on which the subject circuit resides are provided. An eFuse sense amplifier coupled to an eFuse array and used for current measurements includes balanced odd and even bitlines, and a plurality of programmable reference resistors connected to the balanced odd and even bitlines. First a baseline current measurement is made through one of the programmable reference resistors, and used to identify a network baseline resistance. A current measurement is made for an eFuse path including a selected eFuse and used to identify the resistance of the selected eFuse.Type: GrantFiled: September 18, 2008Date of Patent: July 27, 2010Assignee: International Business Machines CorporationInventors: Anthony Gus Aipperspach, Toshiaki Kirihata, Phil Christopher Felice Paone, Brian Joy Reed, John Matthew Safran, David Edward Schmitt, Gregory John Uhlmann
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Patent number: 7755960Abstract: A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells.Type: GrantFiled: December 12, 2008Date of Patent: July 13, 2010Assignee: STMicroelectronics SAInventors: Bertrand Borot, Emmanuel Bechet
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Patent number: 7751267Abstract: A programmable precharge circuit includes a plurality of transistors. Each transistor has a different threshold voltage from other transistors of the plurality of transistors. Each transistor is configured to connect a supply voltage to a node, and the node is selectively coupled to bitlines in accordance with a memory operation. Control logic is configured to enable at least one of the plurality of transistors to provide a programmable precharge voltage to the node in accordance with a respective threshold voltage drop from the supply voltage of one of the plurality of transistors.Type: GrantFiled: July 24, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Rouwaida Kanj, Jayakumaran Sivagnaname
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Patent number: 7746696Abstract: A memory has first and second storage cells, each with a floating node, that store complementary data values. Interlaced inverters quickly sense a voltage difference between the storage cells and provide a data value output when the memory is read. Each floating node includes a tunneling gate of a tunneling transistor, a gate of a bitline transistor, and a plate of a coupling capacitor.Type: GrantFiled: March 4, 2008Date of Patent: June 29, 2010Assignee: XILINX, Inc.Inventor: Sunhom Paak
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Patent number: 7746713Abstract: A memory device includes a plurality of cells comprising CMOS structures. A non-strobed regenerative sense-amplifier (NSR-SA) is coupled to the cells and employs offset compensation and avoids strobe timing uncertainty to increase read-access speeds.Type: GrantFiled: April 18, 2008Date of Patent: June 29, 2010Assignee: Massachusetts Institute of TechnologyInventors: Anantha P. Chandrakasan, Naveen Verma
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Patent number: 7742354Abstract: A random access memory data resetting method is provided. The method includes following steps. First, a state machine resetting signal is provided to a RAM. Next, the state machine resetting signal is extended for a predetermined time period. Afterwards, a data resetting operation is executed in the RAM within the predetermined time period.Type: GrantFiled: April 28, 2008Date of Patent: June 22, 2010Assignee: Nanya Technology CorporationInventor: Shu-Liang Nin
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Patent number: 7729150Abstract: A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors.Type: GrantFiled: July 18, 2008Date of Patent: June 1, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Vishal Sarin, Hieu Van Tran, Isao Nojima
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Patent number: 7729189Abstract: A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals.Type: GrantFiled: October 7, 2008Date of Patent: June 1, 2010Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7719909Abstract: This invention discloses a write-sensing circuit for a semiconductor memory having at least one memory block with a continuous word-line being coupled to all the memory cells in a column of the memory block and a continuous bit-line being coupled to all the memory cells in a row of the memory block, the write-sensing circuit comprising a first and a second sense amplifier belonging to the same memory block, a first switching device coupled between the first sense amplifier and a first power supply, the first switching device being controlled by a first signal, and a second switching device coupled between the second sense amplifier and the first power supply, the second switching device being controlled by a second signal different from the first signal, wherein when the first sense amplifier is activated, the second sense amplifier can remain de-activated.Type: GrantFiled: April 9, 2008Date of Patent: May 18, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shine Chung, Cheng-Hsien Hung
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Patent number: 7719910Abstract: A sense amplifier of a DRAM includes, in series between two terminals of application of a supply voltage, at least one first transistor of a first channel type, and an amplification stage formed of two parallel branches each including a second transistor of the first channel type in series with a transistor of a second channel type. The gates of the transistors of a same branch are connected to the junction point of the transistors of the other branch. Each branch including at least one first additional transistor of the first channel type in parallel with at least each second transistor of the first channel type.Type: GrantFiled: May 19, 2009Date of Patent: May 18, 2010Assignee: STMicroelectronics Crolles 2 SASInventors: Marc Vernet, Michel Bouche
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Patent number: 7719891Abstract: In a non-volatile memory device, the level of a verifying voltage supplied to a word line is adjusted in accordance with occurrence of a source line bouncing phenomenon. The non-volatile memory device includes a bouncing sensing circuit configured to compare a source line current passing through a common source line with a reference current, and output a bouncing sensing signal in accordance with the comparing result, and a word line voltage controller configured to provide a verifying voltage increased by a certain level to a word line in accordance with level of the bouncing sensing signal.Type: GrantFiled: December 28, 2007Date of Patent: May 18, 2010Assignee: Hynix Semiconductor Inc.Inventor: Kyu Hee Lim
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Patent number: 7710759Abstract: A nonvolatile ferroelectric memory device includes a plurality of memory cells connected serially between a bit line and a sensing line, a first switching unit configured to selectively connect the memory cells to the bit line in response to a first selecting signal, and a second switching unit configured to selectively connect the memory cells to the sensing line in response to a second selecting signal. The first switching unit and the second switching unit have the same structure as that of the memory cell.Type: GrantFiled: September 26, 2006Date of Patent: May 4, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Hee Bok Kang, Jin Hong Ahn
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Patent number: 7692988Abstract: A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.Type: GrantFiled: July 8, 2008Date of Patent: April 6, 2010Assignee: NEC Electronics CorporationInventors: Takao Yanagida, Takuya Hirota
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Patent number: 7688622Abstract: A phase change memory device includes a cell array having a phase change resistance cell arranged at an intersection of a word line and a bit line and a dummy cell configured to discharge the bit line in response to a first bit line discharge signal. A column switching unit selectively controls a connection between the bit line and a global bit line in response to a column selecting signal. The dummy cell disconnects a discharging path in response to the first bit line discharge signal in a precharge mode, and discharges the bit line in response to the first bit line discharge signal in an active mode.Type: GrantFiled: June 6, 2008Date of Patent: March 30, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Suk Kyoung Hong
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Patent number: 7684271Abstract: A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plural first precharge units each precharge one bit line of a first bit line pair and one bit line of a second bit line pair in response to a bit line equalizing signal. Plural sense amplifiers each sense a data bit supplied to a respective one of the first and second bit line pairs and amplify sensed data.Type: GrantFiled: October 20, 2006Date of Patent: March 23, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Hyung-Sik Won
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Patent number: 7684270Abstract: In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD?Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.Type: GrantFiled: August 23, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventors: Takuya Hirota, Takao Yanagida, Hiroyuki Takahashi
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Patent number: 7672184Abstract: A semiconductor memory device includes a level feedback circuit and a refresh signal generator. The level feedback circuit outputs a bulk voltage applied to a cell transistor as a feedback signal. The refresh signal generator generates an internal refresh signal for driving a refresh operation at predetermined intervals during a self refresh mode. A period of the internal refresh signal is adjusted according to a voltage level of the feedback signal.Type: GrantFiled: June 29, 2007Date of Patent: March 2, 2010Assignee: Hynix Semiconductor Inc.Inventors: Jae-Hyuk Im, Chang-Ho Do
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Patent number: 7663952Abstract: Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to precharging. The final precharge voltage can be set by appropriately selecting the size of a capacitor in the precharge circuit.Type: GrantFiled: August 12, 2008Date of Patent: February 16, 2010Assignee: Micron Technology, Inc.Inventor: Shigeki Tomishima
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Patent number: 7656744Abstract: A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.Type: GrantFiled: December 14, 2006Date of Patent: February 2, 2010Assignee: Elpida Memory, Inc.Inventors: Yurika Aoki, Seiji Funaba, Yoji Nishio
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Patent number: 7656739Abstract: In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in which the second load is substantially equal to the first load. The bitcell also comprises a signal driving circuit having a first node and a second node. The first node is connected to the first set of read bitlines and the second node is connected to the second set of read bitlines.Type: GrantFiled: August 27, 2007Date of Patent: February 2, 2010Assignee: VIA Technologies, Inc.Inventor: Jung Hoon Ham
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Patent number: 7633831Abstract: An operation control circuit carries out a first access operation upon receipt of a first access command during activation of a chip enable signal, and carries out a second access operation accessing a memory core in a shorter time than the first access operation, upon receipt of the next access command during activation of the chip enable signal. For this reason, two types of access operations whose access times differ can be carried out by receiving the same access command at the same access terminal. A dedicated terminal for distinguishing between the two types of operations does not need to be formed in a controller, etc., which accesses a semiconductor memory. Selective use of the first and second access operations improves the operation efficiency of the semiconductor memory. Consequently, the operation efficiency of the semiconductor memory can be improved without increasing the cost of a system incorporating the semiconductor memory.Type: GrantFiled: May 8, 2007Date of Patent: December 15, 2009Assignee: Fujitsu Microelectronics Ltd.Inventor: Hitoshi Ikeda
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Patent number: 7626850Abstract: Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential bit cell. Such a differential bit cell includes two PMOS transistors, two NMOS transistors, and two inverters. The source of the first PMOS transistor and the source of the second PMOS transistor are electrically coupled to a bit line input, and the source of the first NMOS transistor and the source of the second NMOS transistor are electrically coupled to the bit line input. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to a word line input. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the word line input.Type: GrantFiled: April 17, 2007Date of Patent: December 1, 2009Assignee: Texas Instruments IncorporatedInventors: Charles M. Branch, Steven C. Bartling
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Patent number: RE41441Abstract: A maskable data output buffer includes an output stage receiving data signals from a data coder. The signals output from the data coder are normally complementary data signals corresponding to complementary data input signals. However, in response to receiving a mask signal, the data coder forces the output signals to be other than complementary. The output stage normally generates a data output signal corresponding to the complementary data input signals. However, when the data input signals are other than complementary, the output of the output stage assumes a high impedance condition. Since the timing of the high impedance condition is determined from the data signals themselves, the timing of the mask operation is inherently properly timed to the output of the data from the data output buffer.Type: GrantFiled: November 9, 2001Date of Patent: July 13, 2010Assignee: Micron Technology, Inc.Inventor: Todd A. Merritt