Abstract: The invention relates to a dynamic memory comprising a memory cell array (10), a test controller (12) for testing the memory cell array (10) and an oscillator (14) for controlling the refreshing of said memory cell array (10). According to the invention, said memory includes means (16) for using the oscillator (14) as a time base for the test controller. Hereby, a slow time base is achieved, which may be used for different self-tests of the memory.

Abstract: A phase change memory device is provided which is constituted by memory cells using memory elements and select transistors and having high heat resistance to be capable of an operation at 140 degrees or higher. As a device configuration, a recording layer of which, of Zn—Ge—Te, content of Zn, Cd or the like is 20 atom percent or more, content of at least one element selected from the group consisting of Ge and Sb is less than 40 atom percent, and content of Te is 40 atom percent or more is used. It is thereby possible to implement the memory device usable for an application which may be performed at a high temperature such as an in-vehicle use.

Abstract: The invention relates to a RAM store having a shared SA structure, in which sense amplifiers (SA) arranged in SA strips (10) between two respective adjacent cell blocks are used by a plurality of bit line pairs (21, 22; 21-24) from the adjacent cell blocks and the bit line pairs (21, 22; 21-24) have respective charge equalization circuits individually associated with them for the purpose of performing charge equalization between the bit line halves of the bit line pairs (21, 22; 21-24) in a precharge phase, where a shorting transistor (30) is provided which, when prompted by a control signal (EQLx), connects the bit line halves (BLT, BLC) of the bit line pairs (21, 22; 21-24) which are in the precharge phase to one another.

Abstract: A data processing apparatus comprises a plurality of input signal lines, a plurality of output signal lines and an electronic circuit. The electronic circuit inputs first data from the plurality of input signal lines and outputs second data to the plurality of output signal lines. The first data is one bit data represented by a combination of bits of the plurality of input signal lines. The second data is one bit data represented by a combination of bits of the plurality of output signal lines.

Abstract: Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

Abstract: A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.

Abstract: A non-volatile semiconductor memory device with a small layout area, having a memory cell array including a plurality of memory cells arranged in a column direction and a row direction, wherein: each of the memory cells has a source region, a drain region, a channel region disposed between the source region and the drain region, a select gate and a word gate disposed to face the channel region, and a non-volatile memory element provided between the word gate and the channel region; and a longitudinal section of the word gate has a base, a side which is perpendicular to the base, and a curved side which connects the base to the side.

Abstract: A programmable soft-start control circuit having two memory registers for regulating the ramp-up time period of charging current in a charge pump of an integrated circuit. The two memory registers are programmed to provide two different soft-start settings for two distinct charge pump turn-on conditions, initial power-up and flash programming. Charge pump feedback logic is employed to detect the charge pump turn-on condition and activate the proper pre-programmed soft-start setting loaded in the memory registers.

Abstract: A flash memory device is disclosed that includes a number of columns each of which is connected with a plurality of memory cells. A column selector circuit selects a part of the columns in response to a column address, and a plurality of sense amplifier groups are connected with the selected columns by the column selector circuit. The column selector circuit variably selects the columns according to whether the column address is 4N-aligned (where N is an integer having a value of 1 or more). For example, the column selector circuit chooses columns of the column address when the column address is 4N-aligned, and chooses columns of an upper column address when the column address is not 4N-aligned.

Abstract: A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test mode enable confirmation section for informing whether a test mode is enabled; and a fuse set for providing a constant signal by using the output from the test mode enable confirmation section in case of the test mode, regardless of elimination or non-elimination of a fuse.

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

Abstract: An analysis method for a semiconductor device includes measuring electrical characteristics of TEGs fabricated on a semiconductor substrate; classifying the TEGs into a first TEG category where a systematic failure has not occurred and a second TEG category where the systematic failure has occurred based on the electrical characteristics; creating a first comparison Mahalanobis reference space using first parameters of the TEGs in the first TEG category from among parameters of the TEGs expressed as numerical values; calculating a first comparison Mahalanobis distance of the first parameters and a second comparison Mahalanobis distance of second parameters of the TEGs in the second TEG category by using the first comparison Mahalanobis reference space; and comparing the first and second comparison Mahalanobis distances.

Abstract: Removable memory card handling for handheld field maintenance devices is provided. In one aspect, a memory card is attached to an extension tab that is larger than the card to facilitate handling and provide a larger printable surface than the card. In another aspect, a removable memory module includes a memory card permanently affixed therein. The removable module includes a locking mechanism to lock the module into the tool to maintain the environmental rating of the tool.

Abstract: An integrated circuit having first connections, a first memory cell, first and second prechargers, and first and second data transmission devices. The first connections have a dual-rail signal applied thereto. The first memory cell is connected to the first connections and buffer-stores the dual-rail signal applied to the first connections. The first precharger precharges first lines, which are connected to the first connections. The first data transmission device, which forwards the dual-rail signal stored in the first memory cell to second connections, which are connected to a second memory cell which transmits the dual-rail signal to the first connections again using the second data transmission device. The second precharger precharges second lines, which are connected to the second connections.

Abstract: A programmable read-only memory cell and method of operating the programmable read-only memory cell. In one embodiment, the programmable read-only memory cell comprises a floating gate arranged in a trench, an epitaxial channel layer formed on the floating gate, the channel layer connecting a source electrode to a drain electrode, and a selection gate arranged above the channel line.

Abstract: A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complementary data lines. The data lines are coupled to respective inputs of a DC sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data are selectively coupled to the inputs of the DC sense amplifier from the complementary digit lines for an addressed column. In a test mode, the multiplexer connects the I/O lines for both arrays to the data lines to compress the data from the two arrays.

Abstract: An integrated sensing device comprising an array of sensor processor cells capable of being arranged into a detection array: Each sensor processor cell comprises a sensing medium; at least one transconductance amplifier configured for feedforward template multiplication; at least one transconductance amplifier configured for feedback template weights; a plurality of local dynamic memory cells; a data bus for data transfer; and a local logic unit. The array of sensor processor cells, by responding to data control signals, is capable of transforming, reshaping, and modulating the original sensed image into varied represenations which include (and extend) traditional spatial and temporal processing transformations.

Abstract: A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to cause a channel current to flow according to the threshold voltage of the non-volatile memory element.

Abstract: There is provided a memory for storing data comprising:

Abstract: A method for enhancing photoreactive absorption in a specified volume element of a photoreactive composition. In one embodiment, the method includes: providing a photoreactive composition: providing a source of light (preferably, a pulsed laser) sufficient for simultaneous absorption of at least two photons by the photoreactive composition, the light source having a beam capable of being divided: dividing the light beam into a plurality of equal path length exposure beams: and focusing the exposure beams in a substantially non-counter propagating manner at a single volume element of the photoreactive composition simultaneously to react at least a portion of the photoreactive composition.

Abstract: The present invention is related to methods of fabricating a resistance variable memory element and a device formed therefrom having improved switching characteristics. According to an embodiment of the present invention a resistance variable material memory element is annealed to remove stoichiometric amounts of a component of the resistance variable material. According to another embodiment of the present invention a silver-germanium-selenide glass is annealed for a duration of about 10 minutes in the presence of oxygen to drive off selenium and increase the rigidity of the glass.

Abstract: Method for determining a repair solution for a memory module in a test system, memory areas of the memory module being successively tested in order to obtain, for each memory area, a defect datum which specifies whether the respective memory area is defective, wherein defect addresses, the address values of which specify the defective memory areas of the memory module, are generated from addresses of the memory areas and the associated defect data, the defect addresses being stored in the test system, the repair solution being determined from the stored defect addresses.

Abstract: A data write circuit includes a receiver which receives pixel data with an affix of display state designating data for designating a display state; a setting section in which set are write control data containing first display state designating data for designating a specific display state and write mode designating data for designating a write mode when the data is written into the memory; and a controller which performs control to write data corresponding to the pixel data into the memory, in accordance with a write mode designated by the write mode designating data, depending on a relationship between the display state designating data and the first display state designating data.

Abstract: A nonvolatile semiconductor memory is disclosed, which comprises first and second nonvolatile memory cells, first and second bit lines, first and second column selection transistors, a first column resetting and bit line testing transistor connected to a first node to which the first and second column selection transistors are connected, a sense amplifier which amplifies a cell data on the first node, and a control circuit which controls to turn the resetting and testing transistor on to reset a potential of the first node, after data the first or second memory cell selected by turning the first or second column selection transistor on has been sensed by the sense amplifier in a first time duration, and controls to electrically separate the sense amplifier from the first node while the first and second column selection transistors and the resetting and testing transistor are turned on simultaneously in a second time duration.

Abstract: The present invention includes a method of fabricating a non-volatile memory device having two transistors for two-bit operations to improve electron trapping efficiency and integration degree of the non-volatile memory device, and a method of driving the non-volatile memory device. The EEPROM device acccording to the present invention comprises a silicon substrate including a first and a second channel area, a first and a second conductive gate on the first and the second channel area, respectively, facing each other, a first and a second insulation layer in the bottom of the first and the second gate, and a first and a second junction area of a second conductive type between the first and the second channel area overlapping with the first and the second conductive gate.

Abstract: A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit triggers a wordline decoder to activate a select wordline. The timing circuit prevents activation of the wordline decoder until the isolation signal is received.

Abstract: An effective Electric Wafer Sort (EWS) flow is implemented by expanding the functions of the micro-controller embedded in a FLASH EPROM memory device and of the integrated test structures. The architecture provides for executing test routines internally without involving any external complex or expensive test equipment to control the test program. The processes are executed by the onboard micro-controllers (that may be reading either from an embedded ROM or from a GLOBAL CACHE provided). Managing test routines by an internal process permits the device architecture to be transparent from a tester point of view, by purposely creating a standard interface with a set of defined commands and instructions to be interpreted by the on board microcontroller and internally executed.

Abstract: In the memory cell array of a semiconductor memory the memory elements or memory cells with a magnetoresistive effect can have a hard-magnetic memory layer and a soft-magnetic sensor layer. The magnetization axis of the hard-magnetic layer lies parallel to the line connected thereto, and the magnetization axis lies parallel to the line connected thereto. By an AC voltage or AC current source, a voltage or current signal is impressed on a respective selected line. The magnetization direction of the soft-magnetic layer is sinusoidally deflected from the easy magnetization axis. In addition to the impressed signal, the magnetoresistive resistance of the memory cell also changes as a result. Depending on the magnetization direction of the hard-magnetic layer, the signal is modulated in-phase or in-antiphase by the variable resistance. The sign supplies the memory information.

Abstract: A word line driver includes multiple current paths for driving a word line of a memory device to a negative voltage and a positive voltage. When driving the word line from the negative voltage to the positive voltage, the word line driver uses a first current path to drive the word line to the positive voltage in one stage. When driving the word line from the positive voltage to the negative voltage, the word line driver drives the word line from the positive voltage to ground using the first current path in a first stage. In a second stage, the word driver further drives the word line from ground to the negative voltage in using a second current path.

Abstract: The content of a few pages of the dynamic random access memory is backed up, then one tries to refresh them less quickly, for example two times less quickly, and one observes whether this does or does not cause errors. The operation is repeated on the entire memory. Depending on the number of errors that have appeared on the pages refreshed less often, the refresh period is decreased or increased. Thus, the memory self-adjusts its refresh period to what is necessary for it.

Abstract: A hybrid magnetic-semiconductor structure can be used as a memory element for the nonvolatile storage of digital information, as well as in other environments, including for example logic applications for performing digital combinational tasks, or a magnetic field sensor. The hybrid device uses ferromagnetic materials for implementing a variable spin resistance. The ferromagnetic layers are fabricated to permit the device to have two stable magnetization states, parallel and antiparallel. In the “on” state the device has two settable, stable resistance states determined by the relative orientation of the magnetizations of the ferromagnetic layers. An external magnetic field can change the magnetization state of the device by orienting the magnetization of the ferromagnetic layers to be parallel or antiparallel, thus changing the resistance of the device to a current of spin polarized electrons.

Abstract: A semiconductor device (such as a DRAM) includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines.

Abstract: The present invention relates to a system and method for equalizing the capacitance between at least two lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the lines using an algorithm. After determining the twisting pattern, the lines are twisted according to the pattern so that each of the lines runs along every other line for a same distance across the length of the bus.

Abstract: A test clock signal for determining timing of transferring a signal to an embedded memory, a memory clock signal for determining timing of latching signal/data of the embedded memory, and a latch timing signal for sampling a signal read from the memory are selectively sampled in accordance with a correcting test clock signal by a common flip flop. The phase differences of the latch timing signal, test clock signal and memory clock signal are measured externally. Thus, it is possible to accurately measure timing conditions such as set up/hold time and access time of the embedded synchronous memory.

Abstract: The disclosure is a NAND flash memory with the function of error checking and correction during a page copy operation. The NAND flash memory is able to prohibit transcription of erroneous bits to a duplicate page from a source page. Embodiments of the inventive flash memory include a correction circuit for correcting bit errors of source data stored in a page buffer, a circuit configured to provide the source data to the correction circuit and to provide correction data to the page buffer, and a copy circuit configured to copy the source data to the page buffer, and to store the correction data in the other page from the page buffer.

Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

Abstract: A charging circuit includes a charging driving circuit, a time constant circuit, a control circuit, a voltage detection circuit, and a delay and inversion circuit. The charging driving circuit starts a charging operation in accordance with a delay signal output from the delay and inversion circuit, and terminates the charging operation in accordance with a detection signal output from the voltage detection circuit.

Abstract: A computer supplies an enable command and a password to a controller after a memory card is attached to the computer. The controller allows acceptance of an access command if the supplied enable command and password coincide with those stored in a flash memory, or refuses the acceptance of the access command if the supplied enable command and password differ from those stored in the flash memory. The controller updates the enable command and password if a password setting command and newly prepared enable command and password are supplied to the controller from the computer during access command accept mode. The controller refuses the access command if the computer supplies to the controller a correct enable command but a wrong password during the access command accept mode.

Abstract: The present invention provides a content addressable memory (CAM) match detection circuit that maintains traditionally achieved levels of accuracy while greatly reducing the amount of power dissipated. In accordance with an exemplary embodiment of the invention, rather than allowing the Matchline voltage to swing between a precharge voltage level (e.g., VDD) and Ground, the Matchline voltage is restricted to swinging between the precharge voltage level (e.g., VDD) and a Negative Reference voltage level that is lower than the precharge voltage level but higher than Ground.

Abstract: An integrated semiconductor circuit includes a cell array havinb memory cells which can be read by word lines and bit lines. Two bit lines in each case are connected to inputs of the same signal amplifier. In order to compensate for parasitic capacitances which arise at thin sidewall insulations between the patterned word lines and adjacent bit line contacts which connect the bit lines located at a higher level to the active regions located at a deeper level, two additional word lines and dummy contacts of the bit lines are dummy contacts lead past this additional word lines. The additional parasitic capacitances produced by the dummy contacts alter the electrical potential of the respective reference bit line at the signal amplifier in the same way as the parasitic capacitances of activated bit lines, as a result of which the measured differential potential is corrected with respect to the parasitic effects.

Abstract: The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

Abstract: A flash memory structure. The structure includes device isolation regions defined on an active area of a substrate, a deep well of first conductive type, stacked gate structures, a tunneling oxide layer, wells of second conductive type, sources and drains, wherein the aforementioned deep well of first conductive type is located in the active area and below the device isolation regions. The aforementioned wells of second conductive type are formed in the area corresponding to the drains and below the device isolation regions between the adjacent stacked gate structures. The aforementioned sources and drains are in the active areas located on both sides of the control gates, wherein the drains are enclosed by the wells of second conductive type; and the sources are located on both sides of the wells of second conductive type and electrically connected with each other via the deep well of first conductive type.

Abstract: A pre-treating circuit for accessing the disc and a method thereof, which are especially used for treating the signal waveform that violates the encoding rule of the disc information, are provided. The present invention can modulate the signal waveform that violates the encoding rule, so that the waveform is not changed during at least 3 continuous periods of the clock signal. The present invention also replaces any wrong 16-bit data which violate the encoding rule, with approximated 16-bit data before they are decoded, or receives approximated 8-bit data which correspond to the incorrect 16-bit data, by directly referring to a table. Therefore, the subsequent decoding module can acquire more data for continuous processing, so as to improve the data reading reliability and to prevent the “picky disc” or “disc error reading” problem from happening.

Abstract: A circuit is provided for equalizing a signal between a pair of bit lines. The circuit comprises a first equalizing element that is operatively coupled between the pair of bit lines for equalizing the signal, the first equalizing element being located proximate a first end of the pair of bit lines. The circuit further comprises a precharging element that is operatively coupled between the pair of bit lines for precharging the pair of bit lines to a precharge voltage, the precharging element being located proximate to the first equalizing element. The circuit also comprises a second equalizing element that is operatively coupled between the pair of bit lines for equalizing the signal, and located at a predetermined position along the bit lines. As a result of having multiple equalizing elements located along pairs of bit lines, the precharge and equalize function is performed faster than in conventional approaches.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208t) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208t) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.

Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

Abstract: A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells disposed at the points at which the bitlines and wordlines cross each other. According to a first aspect of the present invention, the isolating layer is removed from the bitlines at the portions that are not covered by the wordlines, whereas the areas between the bitlines remain unaffected. Alternatively, the isolating layer is removed from the whole cell array. Then, an electrical conductive material is provided on the exposed portions of the bitlines. The method is used to provide bitline contacts in a nitride read only memory (NROM™) chip.

Abstract: The invention relates to a memory device and the like. The memory device comprises one or more memory block. The memory block has a memory cell array consists of multiple memory cells (210) arranged in a matrix form. A region of the multiple memory cells (210) includes multiple divisional domains (201a-201e) divided in the direction along word line (WL). Each of the word lines (WL) has multiple divisional selection lines (WLa-WLe) divided corresponding to the multiple divisional domains. The memory block has a switching mechanism (220) for switching the divisional word lines (WL) that are to be simultaneously activated in each of the divisional domains. Multiple memory cells (210) associated with each of the divisional word lines store a horizontal or vertical array of pixel data. The inventive memory device enables simultaneous access to multiple items of pixel data constituting a pixel block having an arbitrary configuration.