Complementing/balancing Patents (Class 365/202)
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Patent number: 7619939Abstract: A cell array selection circuit, a cell array bit line precharge circuit, and a sense amplifier bit line precharge circuit are provided in a semiconductor storage apparatus. In a standby state of read/write operation, the cell array selection circuit is controlled to an inactive state, and the bit line precharge circuits are controlled to an active state. In an active state of read/write operation, the cell array selection circuit to be selected is controlled to an active state, and the cell array bit line precharge circuit and the sense amplifier bit line precharge circuit are controlled to an inactive state. Cell array selection transistors, sense amplifier bit line precharge transistors, and control signals supplied to gate electrodes of the transistors are set in which change in potential provided on a cell array bit line pair when the states of the transistors change is cancelled.Type: GrantFiled: December 5, 2007Date of Patent: November 17, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Yasuyuki Kajitani
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Patent number: 7609570Abstract: A switched capacitor charge sharing technique for integrated circuit devices which allows for efficient charge sharing and signal level generation of exact desired values, and wherein the signal levels of the circuits sharing the charge do not have to have the same voltage levels. In a particular embodiment of the technique of the present invention disclosed herein, a switched capacitor is used to share charge between, for example, two different signals or two different groups of signals. The size of the capacitor can be adjusted to obtain the required signal level of the various signals.Type: GrantFiled: January 22, 2007Date of Patent: October 27, 2009Assignees: United Memories, Inc., Sony CorporationInventors: Michael C. Parris, Douglas B. Butler, Kim C. Hardee
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Patent number: 7606088Abstract: The disclosed embodiments relate to an equalization circuit, which may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense amplifier. An equalizer may be connected to the input to the first sense amplifier to provide an equalizing voltage to the input to the first sense amplifier. The input to the first sense amplifier may be equalized by the equalizing voltage independent from the input to the second sense amplifier.Type: GrantFiled: October 7, 2008Date of Patent: October 20, 2009Assignee: Micron Technology, Inc.Inventor: Chul Min Jung
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Patent number: 7606092Abstract: A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.Type: GrantFiled: February 1, 2007Date of Patent: October 20, 2009Assignee: Analog Devices, Inc.Inventors: Michael D. Eby, Gregory P. Mikol, James E. DeMaris
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Patent number: 7606095Abstract: A precharge voltage supply circuit and a semiconductor memory device using the same are described. The precharge voltage supply circuit includes a first voltage supplier configured to reduce a precharge voltage and supply the reduced precharge voltage in response to a power down mode signal that is activated in a power down mode, a second voltage supplier configured to supply a power voltage in a predetermined section from a point of time when exiting the power down mode, and a third voltage supplier configured to supply the precharge voltage after a lapse of the predetermined section.Type: GrantFiled: February 5, 2008Date of Patent: October 20, 2009Assignee: Hynix Semiconductor Inc.Inventor: Mi Hyun Hwang
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Patent number: 7602641Abstract: A method of making a non-volatile memory (NVM) cell structure includes the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node of the SRAM cell, the first pass gate structure being responsive to first and second states of a first pass gate signal to respectively couple and decouple the first NVM cell and the SRAM cell. A first equalize structure is formed to connect the first pass gate structure and the first NVM cell and is responsive to a first equalize signal to connect the first NVM cell to ground. A second pass gate structure is connected between the second NVM cell and the second data node of the SRAM cell, the second pass gate structure being responsive to first and second states of a second pass gate signal to respectively couple and decouple the second NVM cell and the SRAM cell.Type: GrantFiled: September 25, 2008Date of Patent: October 13, 2009Assignee: National Semiconductor CorporationInventors: Pavel Poplevine, Annie-Li-Keow Lum, Andrew Cao, Ernes Ho
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Patent number: 7602632Abstract: A method for operating a memory cell. Memory cells represent binary values by storing a characteristic parameter. The method of memory cell operation entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time.Type: GrantFiled: September 18, 2007Date of Patent: October 13, 2009Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Chung H. Lam, Bipin Rajendran
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Patent number: 7590010Abstract: A data output circuit includes a sense amplifier and first and second latches. The sense amplifier is for amplifying differential data to generate amplified differential data. The first latch is for latching the amplified differential data to generate first latched data having a same phase as the amplified differential data. The second latch is for latching the amplified differential data to generate second latched data having an opposite phase from the amplified differential data. The amplified differential data from outputs of the sense amplifier are applied substantially simultaneously to inputs of the first and second latches.Type: GrantFiled: January 4, 2008Date of Patent: September 15, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Taek-Seon Park, Sung-Min Yim
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Publication number: 20090225612Abstract: A method of equilibrating digit lines, a memory array device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second digit line to the terminated end of the first digit line. The memory array is configured with the first and second digit lines arranged directly adjacent to each other.Type: ApplicationFiled: March 10, 2008Publication date: September 10, 2009Applicant: MICRON TECHNOLOGY, INC.Inventor: Werner Juengling
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Patent number: 7564729Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.Type: GrantFiled: March 27, 2008Date of Patent: July 21, 2009Assignee: International Business Machines CorporationInventors: John Edward Barth, Jr., Paul C. Parries, William Robert Reohr, Matthew R. Wordeman
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Publication number: 20090154273Abstract: A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells.Type: ApplicationFiled: December 12, 2008Publication date: June 18, 2009Applicant: STMICROELECTRONICS SAInventors: Bertrand Borot, Emmanuel Bechet
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Patent number: 7539073Abstract: A semiconductor memory device having a shared bit line sense amplifier structure is provided. The semiconductor memory device includes: a plurality of cell arrays each of which has a plurality of bit line pairs, in which the cell arrays includes a first cell array disposed at an edge portion of a cell region and a second cell array disposed adjacent to the first cell array; a first precharging unit for precharging some bit line pairs of the first or second cell array; a second precharging unit for precharging the other bit line pairs of the first cell array; and an auxiliary precharging unit for assisting a precharge operation of the second precharging unit.Type: GrantFiled: June 25, 2004Date of Patent: May 26, 2009Assignee: Hynix Semiconductor Inc.Inventors: Dong-Keun Kim, Chang-Ho Do
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Patent number: 7539070Abstract: A semiconductor memory apparatus includes a plurality of unit cell blocks formed in row and column directions, at least a pair of first input and output lines formed at predetermined intervals in the row direction, at least a pair of second input and output lines formed at predetermined intervals in the column direction, I/O switches connected to a first node group and a second node group and control data input and output of the first input and output lines and the second input and output lines, the first node group corresponding to half of the nodes in the row direction where the first input and output lines intersect the second input and output lines formed at the odd-numbered intervals of the intervals between columns of unit cell blocks, and the second node group corresponding to half of the nodes in the row direction where the first input and output lines intersect the second input and output lines formed at the even-numbered intervals of the intervals between columns of unit cell blocks and a reset seleType: GrantFiled: October 3, 2006Date of Patent: May 26, 2009Assignee: Hynix Semiconductor Inc.Inventor: Bok-Rim Ko
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Patent number: 7535752Abstract: According to an aspect of the invention there is provided a semiconductor memory device, including a first inverter being composed of a first P-channel MOS transistor, a first N-channel MOS transistor, a second inverter being composed of a second p-channel MOS transistor and a second N-channel transistor, a data-retaining portion having a third N-channel MOS transistor, a fourth N-channel MOS transistor, a fifth N-channel MOS transistor and a sixth N-channel MOS transistor, a data-reading portion for reading out data stored in the data-retaining portion via a first bit line, including at least one N-channel MOS transistor, wherein gate widths of the fifth N-channel MOS transistor and the sixth N-channel MOS transistor, respectively, is larger than gate widths of the first N-channel MOS transistor, the second N-channel MOS transistor, the third N-channel MOS transistor, the fourth N-channel MOS transistor, the first P-channel MOS transistor and the second P-channel MOS transistor, respectively.Type: GrantFiled: February 28, 2007Date of Patent: May 19, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Atsushi Kawasumi
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Patent number: 7535782Abstract: A sense amplifier of a DRAM includes, in series between two terminals of application of a supply voltage, at least one first transistor of a first channel type, and an amplification stage formed of two parallel branches each including a second transistor of the first channel type in series with a transistor of a second channel type. The gates of the transistors of a same branch are connected to the junction point of the transistors of the other branch. Each branch including at least one first additional transistor of the first channel type in parallel with at least each second transistor of the first channel type.Type: GrantFiled: May 23, 2006Date of Patent: May 19, 2009Assignee: STMicroelectronics Crolles 2 SASInventors: Marc Vernet, Michel Bouche
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Patent number: 7532539Abstract: A semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to a load subjected to a process to be performed is disclosed. The semiconductor device includes a memory cell array having SRAM cells arranged in an array form, word lines connected to the SRAM cells for respective rows, a row decoder which selects the word lines one by one during normal operation and multi-select word lines which are not adjacent to each other during low-voltage operation, a load circuit which sets the level of the selected word line to potential lower than power supply voltage, and a controller which controls the row decoder and load circuit to selectively control selection of the word lines and the load circuit.Type: GrantFiled: August 3, 2007Date of Patent: May 12, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Osamu Hirabayashi
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Patent number: 7518930Abstract: In a method for generating a selected word line voltage, a constant voltage that is substantially independent of a temperature change is generated. Additionally, a current that varies in proportion to a temperature is generated. To generate the selected word line voltage, the current is converted to a voltage that varies in proportion to the absolute temperature and the voltage is subtracted from the constant voltage.Type: GrantFiled: April 21, 2006Date of Patent: April 14, 2009Assignee: SanDisk CorporationInventor: Toru Miwa
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Patent number: 7511988Abstract: A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.Type: GrantFiled: July 10, 2006Date of Patent: March 31, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wesley Lin, Fang-Shi Jordan Lai, Chia-Fu Lee, Sheng Chi Lin, Ping-Wei Wang, Chang-Yun Chang, Tang-Xuan Zhong, Tsung-Lin Lee
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Publication number: 20090080270Abstract: A memory device includes terminals for transferring input data and output data to and from a memory array. The memory device also includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information and time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred.Type: ApplicationFiled: December 2, 2008Publication date: March 26, 2009Inventor: Joo S. Choi
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Publication number: 20090080230Abstract: In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.Type: ApplicationFiled: December 2, 2008Publication date: March 26, 2009Applicant: International Business Machines CorporationInventors: Richard E. Matick, Stanley E. Schuster
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Publication number: 20090080274Abstract: A semiconductor device includes plural switching transistors configured to perform trimming for characteristic adjustment of the semiconductor device, and a nonvolatile memory connected to the plural switching transistors and configured to store data for determining ON and OFF of the plural switching transistors. When the semiconductor device is in operation, ON and OFF of the switching transistors are determined by the data.Type: ApplicationFiled: September 19, 2008Publication date: March 26, 2009Inventor: Hiroaki Nakanishi
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Patent number: 7508726Abstract: A signal sensing circuit and a semiconductor memory device using the same are provided. The signal sensing circuit comprises a sense amplifier, a kick transistor, a first control transistor, a second control transistor, a pre-charge circuit, and a recovery circuit. The kick transistor is used to pull up the operation voltage of the sense amplifier to improve the small signal sensing speed of the sense amplifier. After the signal is sensed, the recovery circuit will pull down the operation voltage of the sense amplifier to the standard level. In the present invention, the small signal sensing speed is greatly improved and the operation voltage of sense amplifier is kept away from the saturated level.Type: GrantFiled: May 10, 2007Date of Patent: March 24, 2009Assignee: Etron Technology Inc.Inventors: Chun Shiah, Chun-Peng Wu, Cheng-Nan Chang
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Patent number: 7505346Abstract: One of a pair of data output units outputs data to one of the data line pair precharged to a reference voltage. A switch control unit couples the other of the data line pair to the data line, which corresponds to a data line to which data are not output, in a data output unit which does not output data during a period after data are output to one of the data line pair until a differential amplifier starts an amplifying operation. Thus, the load amount on the other of the data line pair increases. Therefore, change of the voltage on the other of the data line pair due to the influence of a coupling capacitance during data output can be prevented. That is, decrease of the read margin of data due to the coupling capacitance can be prevented.Type: GrantFiled: March 7, 2008Date of Patent: March 17, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Hiroyuki Kobayashi
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Patent number: 7505334Abstract: A method for operating a memory cell in which a variation of the characteristic parameter of the memory cell affects the effective resistance of the memory cell. The method includes measuring a first discharge time of a reference voltage through the memory cell, determining that the first discharge time is less than a minimum discharge time, adding a supplemental capacitor in parallel with the memory cell, adding including coupling the capacitor to the memory cell through a switch, measuring a second discharge time of the reference voltage through the memory cell, storing the second discharge time and determining the value stored in the memory cell based on the second discharge time.Type: GrantFiled: May 28, 2008Date of Patent: March 17, 2009Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Chung H. Lam, Bipin Rajendran
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Patent number: 7505339Abstract: A supply instruction signal attains the H-level before data is written into a plurality of memory cells. A P-channel MOS transistor is arranged between a power supply node and an input node. The P-channel MOS transistor is turned off to open the input node according to the supply instruction signal. In this case, a write driver discharges electric charges accumulated on the input node and electric charges accumulated on a bit line pair. However, a through-current does not flow from the power supply node to a ground node so that flow of the through-current to a CMOS inverter circuit forming each memory cell can be prevented. Accordingly, such a static semiconductor memory device can be provided that can prevent the flow of the through-current to the CMOS inverter circuit forming each memory cell when simultaneously writing data into the plurality of memory cells.Type: GrantFiled: June 13, 2006Date of Patent: March 17, 2009Assignee: Renesas Technology Corp.Inventor: Shigeki Ohbayashi
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Patent number: 7502273Abstract: A static random access memory (SRAM) macro includes: a cell array having one or more SRAM cells addressed by a plurality of bit lines and word lines; one or more reference cells coupled to at least one reference bit line and the word lines addressing the SRAM cells; and at least one sense amplifier having a first terminal receiving a sensing current generated by an SRAM cell selected from the cell array and a second terminal receiving a reference current generated by the reference cell controlled by the same word line coupled to the selected SRAM cell for comparing the sensing current to the reference current to generate an output signal representing a logic state of the selected SRAM cell.Type: GrantFiled: September 27, 2006Date of Patent: March 10, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Jhon Jhy Liaw
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Patent number: 7495983Abstract: A semiconductor memory device includes at least one cell array and first and second bit line sense amplifying units. A cell array includes a plurality of bit line pairs and a plurality of bit line equalizers connected to each other through a signal line. Each bit line equalizer equalizes a corresponding bit line pair. The first and the second bit line sense amplifying units are alternately connected to the bit line pairs and receive respective bit line equalization signals.Type: GrantFiled: December 29, 2006Date of Patent: February 24, 2009Assignee: Hynix Semiconductor Inc.Inventor: Dong-Keun Kim
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Patent number: 7480189Abstract: A write circuit structure may be used to transfer data between global bit lines and local bit lines of a cache. The write circuit structure located between the hierarchical bit lines may be buffers in parallel with P-channel devices in one embodiment or cross-coupled P-channel and N-channel devices in another embodiment.Type: GrantFiled: September 20, 2002Date of Patent: January 20, 2009Assignee: Intel CorporationInventors: Lawrence T. Clark, Jay B. Miller
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Patent number: 7474583Abstract: A semiconductor memory device has SRAM cells each including: a pair of inverters; a feed control switch connected between a feeding point of the pair of inverters and a power supply voltage supply line; and a boosting device configured to boost a voltage of the feeding point electrically isolated from the power supply voltage supply line by the feed control switch.Type: GrantFiled: December 27, 2006Date of Patent: January 6, 2009Assignee: Sony CorporationInventor: Ikuhiro Yamamura
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Patent number: 7474549Abstract: A bit-line equalizer, a semiconductor memory device including the bit-line equalizer, and a method for manufacturing the bit-line equalizer, in which the bit-line equalizer includes: first and second polysilicon gates formed in a first direction in proximity to each other, the first and second polysilicon gates having a predetermined distance between them; and a plurality of equalizing transistors formed in a second direction along the first and second polysilicon gates, the equalizing transistors equalizing bit-line pairs, with the equalizing transistors being alternately formed in proximity to the first and second polysilicon gates. The bit-line equalizer can vary the widths of the equalizing transistors irrespective of a memory cell pitch in order to improve an equalizing time.Type: GrantFiled: June 1, 2007Date of Patent: January 6, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-bong Chang, Jung-hwa Lee
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Patent number: 7468903Abstract: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.Type: GrantFiled: November 13, 2006Date of Patent: December 23, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Dao-Ping Wang, Hung-Jen Liao, Kun Lung Chen, Yung-Lung Lin, Jui-Jen Wu, Chen Yen-Huei
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Patent number: 7466597Abstract: A NAND flash memory device according to some embodiments includes a cell array, a page buffer configured to copyback read the data in the cell array, and an error detector for detecting errors that occur during the copyback reading and for generating a detection signal. Detecting errors is performed concurrently with a copyback program operation and completes before finishing a copyback program verify operation. The data stored in the page buffer may be copyback programmed when the detection signal is a pass signal. The copyback operation may end without executing the copyback program operation when the detection signal is a fail signal. Since the copyback program operation and the error detection operation are performed concurrently, the errors occurring during the copyback operation may be detected without additional time delay. Additionally, occurrence of two-bit error may be prevented because the copyback program is not executed when the fail signal is generated.Type: GrantFiled: December 22, 2004Date of Patent: December 16, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Hyung-Gon Kim
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Patent number: 7460423Abstract: An embodiment of the present invention is an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.Type: GrantFiled: January 5, 2007Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: Richard E. Matick, Stanley E. Schuster
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Patent number: 7460387Abstract: In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.Type: GrantFiled: January 5, 2007Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: Richard E. Matick, Stanley E. Schuster
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Patent number: 7453726Abstract: A single 4-transistor non-volatile memory (NVM) cell includes a shared static random access memory cell. The NVM cell utilizes a reverse Fowler-Nordheim tunneling programming technique that, in combination with the shared SRAM cell structure, allows an entire cell array to be programmed at two cycles. A single NVM cell approach with shared SRAM allows a 50% area reduction with an insignificant increase in program time.Type: GrantFiled: January 23, 2007Date of Patent: November 18, 2008Assignee: National Semiconductor CorporationInventors: Pavel Poplevine, Annie-Li-Keow Lum, Andrew Cao, Ernes Ho
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Patent number: 7453751Abstract: A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a bit line of a memory circuit when the sense amplifier is reset and a signal voltage on the same bit line when a signal representing a data bit is present in the bit line. The differential amplifier amplifies the difference between the signal voltage and the reference voltage.Type: GrantFiled: July 12, 2006Date of Patent: November 18, 2008Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, David R. Cuthbert
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Patent number: 7443749Abstract: A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals.Type: GrantFiled: July 27, 2006Date of Patent: October 28, 2008Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7443750Abstract: A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals.Type: GrantFiled: July 27, 2006Date of Patent: October 28, 2008Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7440309Abstract: A memory includes a sense amplifier segment and a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell located at each cross point of each word line and each bit line. The first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.Type: GrantFiled: June 15, 2005Date of Patent: October 21, 2008Assignee: Infineon Technologies AGInventor: Klaus Hummler
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Patent number: 7436696Abstract: A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current, and a pass-gate MOS device having a third drive current coupled to the pull-up MOS device and the pull-down MOS device. The first drive current and the third drive current preferably have an ? ratio of between about 0.5 and about 1. The second drive current and the third drive current preferably have a ? ratio of between about 1.45 and 5.Type: GrantFiled: October 17, 2006Date of Patent: October 14, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ping-Wei Wang, Yuh-Jier Mii, Hung-Jen Liao
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Patent number: 7436720Abstract: A semiconductor memory device includes plates accessed by different row addresses and a sense amplifier column between the adjacent plates. The sense amplifier column is a mixture of configurations, one in which one of the pair of bit lines is twisted, and another in which neither of the pair of bit lines is twisted. If an address analysis indicates that there is an access through an input/output wiring, input/output data is not inverted. If the address analysis indicates that there is an access through another input/output wiring and that it is an access to a plate, the input/output data is not inverted, while if it is an access to another plate, the input/output data is inverted.Type: GrantFiled: November 29, 2006Date of Patent: October 14, 2008Assignee: Elpida Memory, Inc.Inventors: Tomoko Nobutoki, Kyoichi Nagata
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Patent number: 7433250Abstract: An equalization circuit may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense amplifier. An equalizer may be connected to the input to the first sense amplifier to provide an equalizing voltage to the input to the first sense amplifier. The input to the first sense amplifier may be equalized by the equalizing voltage independent from the input to the second sense amplifier.Type: GrantFiled: June 28, 2006Date of Patent: October 7, 2008Assignee: Micron Technology, Inc.Inventor: Chul M Jung
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Patent number: 7423923Abstract: Circuits and methods are provided for precharging pairs of many digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to precharging. The final precharge voltage can be set by appropriately selecting the size of a capacitor in the precharge circuit.Type: GrantFiled: December 19, 2006Date of Patent: September 9, 2008Assignee: Micron Technology, Inc.Inventor: Shigeki Tomishima
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Patent number: 7423895Abstract: A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors.Type: GrantFiled: March 13, 2007Date of Patent: September 9, 2008Assignee: Silicon Storage Technology, Inc.Inventors: Vishal Sarin, Hieu Van Tran, Isao Nojima
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Patent number: 7414896Abstract: Methods and apparatus that may help reduce standby current in memory devices are provided. By separating equalizing and precharging functions into separate circuit structures, current paths between a source of precharge voltage and a defective wordline (e.g., having an inadvertent short to a bitline due to a manufacturing defect) may be eliminated.Type: GrantFiled: September 13, 2005Date of Patent: August 19, 2008Assignee: Infineon Technologies AGInventor: Jong-Hoon Oh
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Patent number: 7405470Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.Type: GrantFiled: March 29, 2005Date of Patent: July 29, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Iwasaki
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Patent number: 7403439Abstract: Circuit arrangements and methods are provided for regulating and maintaining voltage on bitlines of a semiconductor memory device. According to one embodiment, first and second regulation devices are connected to a charging circuit. At the beginning of a charging period, voltage on the bitlines is regulated with the second regulation device as the bitlines are initially charged to a voltage. After initially charging the bitlines to the voltage, voltage on the bitlines is regulated with the first regulation device that also limits current to the bitlines when there is a leakage anomaly associated with the bitlines. According to another embodiment, a charging circuit that is connected to sense nodes of a sense amplifier while the sense nodes are connected to the bitlines is activated so that the charging circuit assists in charging the bitlines at the beginning of a charging period.Type: GrantFiled: May 1, 2006Date of Patent: July 22, 2008Assignee: Qimonda North America Corp.Inventors: Christopher Miller, Charles Drake
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Publication number: 20080165601Abstract: In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.Type: ApplicationFiled: January 5, 2007Publication date: July 10, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard E. Matick, Stanley E. Schuster
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Patent number: 7394701Abstract: A word line driving circuit includes a read voltage generator and a word line driver. The read voltage generator precharges a clamp capacitor with a power supply voltage to stably generate a read voltage in response to a read command. A capacitance of the clamp capacitor is varied to compensate for a fluctuation of a power supply voltage level. The word line driver distributes electric charges precharged in the clamp capacitor to a word line in response to a word line selecting signal. Therefore, the word line driving circuit reduces unnecessary power consumption in a standby mode by operating the word line rapidly with charge sharing in a read mode.Type: GrantFiled: June 15, 2006Date of Patent: July 1, 2008Assignee: Samsung Electronics., Ltd.Inventors: Jong-Hoon Jung, Myoung-Kyu Seo, Hyo-Sang Lee, Hoon-Jin Bang
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Patent number: 7385865Abstract: In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.Type: GrantFiled: December 1, 2004Date of Patent: June 10, 2008Assignee: Intel CorporationInventors: Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Gunjan H. Pandya, Vivek K. De