Abstract: This invention discloses a write-sensing circuit for semiconductor memories comprising a first and a second local bit-lines (BLs) forming a complementary BL pair, a first and a second global bit-lines (GBLs) forming a complementary GBL pair, and at least one switching circuit controlled by the first and second GBLs and controllably coupling a predetermined power supply source to the first and second BLs, separately, wherein when the first and second GBLs are asserted during a write operation, the switching circuit couples only one of the first and second BLs to the predetermined voltage supply source.

Abstract: An architecture, circuit and method for providing a high speed operation DRAM memory with reduced cell disturb. A DRAM global bit line select circuit couples a pair of local bit lines and the associated sense amplifier to the global bit lines using a circuit optimized for high speed operation. The select circuit and method also reduces or eliminates the bit line disturb effect of the prior art. The circuit and architecture of the DRAM incorporating the select circuit is particularly useful for embedding DRAM memory with other logic in an integrated circuit. For a read operation the select circuit discharges the appropriate global bit line directly to ground thus speeding the read cycles. For a write operation, a dedicated control line is used to couple write data to from the global bit lines to the selected local bit lines. Methods for operating the DRAM and the select circuits are disclosed.

Abstract: This invention discloses a write-sensing circuit for semiconductor memories comprising a first and a second local bit-lines (BLs) forming a complementary BL pair, a first and a second global bit-lines (GBLs) forming a complementary GBL pair, and at least one switching circuit controlled by the first and second GBLs and controllably coupling a predetermined power supply source to the first and second BLs, separately, wherein when the first and second GBLs are asserted during a write operation, the switching circuit couples only one of the first and second BLs to the predetermined voltage supply source.

Abstract: A transistor level shifter circuit constituted by a plurality of PMOS TFT is included. The transistor level shifter circuit primarily includes a conversion circuit, a first amplifier circuit, and a second amplifier circuit. With the simplified circuit arrangement and a smaller quantity of required transistors, the transistor level shifter circuit is adapted to operate efficiency under both high RC load and frequency.

Abstract: Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying memory cell data delivered to a selected bit line and complementary bit line to evaluate the voltage difference between the selected bit line and complementary bit line. Then, the scheme precharges the selected bit line and complementary bit line and the non-selected bit line and complementary bit line. This does not require high precharge driving capability for inactivated bit line and complementary bit line equalized to a predetermined voltage level so that precharge current and operating current can be reduced.

Abstract: One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.

Abstract: A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.

Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Abstract: An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting/disconnecting a sense amplifier to/from a bit line of a first cell field region, and for connecting/disconnecting the sense amplifier to/from from a bit line of a second cell field region, as a function of the state of control signals applied at control lines. Driver devices drive the control signal. Additional switches change the state of the control signals.

Abstract: A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell array block disposed in a direction in which bit lines of the memory cells are arranged, a conjunction block disposed at an intersection of the word line driver block and the sense amplifier block, an equalizer for equalizing a pair of local data lines, the equalizer disposed in the conjunction block, and a local data line sense amplifier configured to sense and amplify signals on a pair of local data lines, and having transistors of a first type disposed in the conjunction block and transistors of a second type disposed in the sense amplifier block.

Abstract: A semiconductor memory device with split bit-line structure is disclosed to realize compact high-density memory device with high speed. The semiconductor memory device includes a first bit-line coupled to a first memory cell, and a second bit-line coupled to a second memory cell. The first and the second bit-lines are formed on different metallization layers. The first and the second memory cells are in the same column of a memory cell array.

Abstract: A system-on-chip integrated circuit selectively gates clocks to individual modules corresponding to the state of a corresponding bit of a peripheral enable register. A reset circuit supplies a signal to a reset input of the digital module for a normal mode if the bit indicates the power-up state and a reset mode if the bit indicates a power-down state. Return to normal mode is delayed a predetermined time after the said bit of indicates the power-up state to ensure clean power up. A false acknowledge circuit for each module supplies an acknowledge signal in response to a received command if the corresponding bit indicates the power-down state.

Abstract: A semiconductor memory device includes at least one cell array and first and second bit line sense amplifying units. A cell array includes a plurality of bit line pairs and a plurality of bit line equalizers connected to each other through a signal line. Each bit line equalizer equalizes a corresponding bit line pair. The first and the second bit line sense amplifying units are alternately connected to the bit line pairs and receive respective bit line equalization signals.

Abstract: According to some preferred embodiments of the present invention, a semiconductor memory device includes an array of memory cells and plural pairs of complementary bit lines, each pair of the complementary bit lines being connected to the memory cells arranged in the same column. The array is divided into plural memory blocks each including plural memory cells arranged in the same column. The corresponding complementary bit lines of the plural memory blocks are connected to corresponding common complementary data lines, respectively. Some pairs of the complementary data lines are crossed at least one time so that the complementary data lines of each pair of the some pairs of the complementary data lines are reversed in position and that the crossed data line and a non-cross data line are arranged alternately whereby crosstalk to be generated between adjacent data lines are reduced.

Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Abstract: A pre-charge voltage supply circuit of a semiconductor device is disclosed which includes a first switch which supplies a pre-charge voltage in response to a first signal having a predetermined voltage level, and has a turn-on resistance of a predetermined level, and a second switch which is connected in parallel to the first switch, supplies the pre-charge voltage in response to a second signal, and has a turn-on resistance lower than the turn-on resistance of the first switch.

Abstract: Dual port memory blocks that have a reduced layout area are provided. The write drivers and sense amplifiers are shared between the dual ports to reduce the number of write drivers and sense amplifiers to save layout area. The write drivers for the two ports are used to write into all of the first port's bitlines. The sense amplifiers for the two ports are used to read from all of the second port's bitlines. A memory block can to support true dual port (TDP) and simple dual port (SDP) operation using substantially less write drivers and sense amplifiers.

Abstract: In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in which the second load is substantially equal to the first load. The bitcell also comprises a signal driving circuit having a first node and a second node. The first node is connected to the first set of read bitlines and the second node is connected to the second set of read bitlines.

Abstract: A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the memory device, and disabling the persistent auto precharge mode of operation in response to the applied disable command. Memory devices operating according this method may be used in memory systems that infrequently experience page hits, such as server systems, while the ability to disable the persistent auto precharge mode allows such memory devices to be used in systems that frequently experience page hits, such as graphics or input/output applications.

Abstract: An antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse including a capacitor. The capacitor may include a gate over a gate oxide and an n-well under the gate oxide. The n-well may have two n+ regions used as contact points for the n-well. Upon programming, an electrically conductive path (e.g., a short) is permanently burned through the gate oxide. The antifuse cell occupies a relatively small area while providing a relatively tight read current distribution.

Abstract: A non-volatile semiconductor memory device including: a plurality of cell arrays each having electrically rewritable and non-volatile memory cells arranged therein; a plurality of page buffers disposed in correspondence with the cell arrays respectively for reading and writing data by a page of the respective cell arrays; and a data bus shared by the cell arrays for data transferring between the page buffers and external terminals, wherein the non-volatile semiconductor memory device has a page copy mode defined as follows: read out data of a copy source page within a first cell array to a first page buffer; transfer the read out data to a second page buffer via the data bus; and then write the read out data into a copy destination page of a second cell array.

Abstract: A static random access memory (SRAM) includes a memory array, a sense amplifier circuit, a replica circuit and a dummy cell. The replica circuit has the same elements as memory cells, and includes plural replica cells which output a signal whose level corresponds to the number of stages provided to a common replica bit line. The dummy cell is connected as a load with the common replica bit line. The source of a drive transistor of the dummy cell is connected with a power source which is at the High level. This suppresses a leak current flowing from a replica bit line to the dummy cell.

Abstract: A memory system and a method of reading and writing data to a memory device provide byte-by-byte write data insertion without adding extra pins or balls to the packaged device. Accordingly, the high frequency performance of the device can be improved.

Abstract: A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a bit line of a memory circuit when the sense amplifier is reset and a signal voltage on the same bit line when a signal representing a data bit is present in the bit line. The differential amplifier amplifies the difference between the signal voltage and the reference voltage.

Abstract: A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals.

Abstract: An equalization circuit for a pair of resistive-capacitive data lines includes primary and secondary equalization circuits attached at both ends of the data line pair. A primary equalization circuit at one end of the data line pair receives a primary control signal, and a secondary equalization circuit at the other end of the data line pair receives a secondary control signal, which is different than the primary control signal. The equalization devices in the primary equalization circuit are attached near the read and write amplifiers and operate normally since all the information is available as to whether or not the corresponding data line pair should be equalized. The additional equalization devices in the secondary equalization circuit placed at the other end of the data line pair receive a simpler control signal that lacks the information as to whether or not any particular data line pair is being equalized.

Abstract: A memory device includes a pair of complementary bitlines including a first bitline and a second bitline. A bitline precharge block is coupled between the first bitline and the second bitline. A sense amplifier is coupled to both the first bitline and the second bitline and a sense amplifier precharge block is coupled to the sense amplifier. The sense amplifier precharge block can be activated independently from the bitline precharge block. An isolation block is coupled between the pair of complementary bitlines and the bitline precharge block on one side and the sense amplifier and sense amplifier precharge block on another side.

Abstract: A memory cell, including a word line, a bit line, a first node storing a bit value voltage level, a driver transistor coupled between the first node and a ground level, and at least one data transfer transistor having a gate electrode coupled to the word line, a source electrode coupled to the bit line, and a drain electrode coupled to the first node, wherein a channel length of the at least one data transfer transistor is smaller than a channel length of the driver transistor. By making the channel length of a data transfer transistor smaller than that of a driver transistor to which the data transfer transistor is coupled, operation speed and in particular read operation speed of the memory cell is improved, while maintaining memory cell stability.

Abstract: Disclosed is a sense amplifier arrangement that achieves high-speed access and shorter cycle time when array voltage is lowered in a DRAM. In a TG clocking sense system to separate data lines between the array side and the sense amplifier side in an early stage of a sensing period, a restore amplifier RAP is added, which amplifies data lines on the array side by referring to the data in the sense amplifier, and the restore amplifier is driven by a voltage VDH higher than the array voltage VDL. As a result, high-speed sense operation of the TG clocking system is made compatible with high-speed restore operation of overdrive system, and it is possible to achieve high-speed access operation and shorter cycle time.

Abstract: A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors.

Abstract: A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell has three main operating modes, reading, writing, and data retention. Reading is performed by sensing current flowing from a powered-up wordline through a conductive one of the cross-coupled transistors. Writing is performed by pulsing the source of the conductive one of the cross-coupled transistors with a positive voltage to flip the conductive states of the cross-coupled transistors. Data retention is performed by using leakage currents to retain the conductive states of the cross-coupled transistors. A decoder for an array of static ram cells may be operated synchronously and in a pipelined fashion using a rotary traveling wave oscillator that provides the clocks for the pipeline. The cell is capable of detecting an alpha particle strike with suitable circuitry.

Abstract: A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complementary data lines. The data lines are coupled to respective inputs of a DC sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data are selectively coupled to the inputs of the DC sense amplifier from the complementary digit lines for an addressed column. In a test mode, the multiplexer connects the I/O lines for both arrays to the data lines to compress the data from the two arrays.

Abstract: A semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption in a simple configuration is provided. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it.

Abstract: Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to precharging. The final precharge voltage can be set by appropriately selecting the size of a capacitor in the precharge circuit.

Abstract: Voltage transfer switches and voltage input/output circuits are provided on a complementary bus line pair to be shared among a plurality of columns of a memory cell array. After a complementary bit line pair is precharged to a predetermined voltage, the voltage of uninverted bit line and the voltage of inverted bit line are exchanged before any of all memory cells belonging to the same column is selected by a word line. With this structure, a predetermined potential difference is ensured between the complementary bit line pair at the time of an activation of a sense amplifier even if the total sum of the off-leak currents of access transistors in all the memory cells belonging to the same column is almost as large as the ON-current (drive current) of a single drive transistor.

Abstract: An SRAM device comprising a column having opposing bit lines, asymmetric memory cells spanning the opposing bit lines in alternating orientations, and a sense amplifier. The sense amplifier includes sensing circuitry configured to sense values stored in the cells and switching circuitry configured to apply signals to the sensing circuitry as a function of the orientations.

Abstract: A semiconductor memory in which a drop in the potential of a bit line due to coupling capacitance at the time of writing data can be restored in a space-saving way without increasing a load at read time. In response to a selection signal, a selection circuit selects complementary bit lines and connects the selected complementary bit lines to write data bus lines or read data bus lines. When data is written, a voltage boosting circuit section selects a read data bus line connected to a bit line of the pair of complementary bit lines located opposite to a bit line the potential of which is decreased on the basis of the data to be written and raises the potential of the selected read data bus line. As a result, a potential level which has dropped due to coupling capacitance between the bit lines can be restored.

Abstract: The disclosed embodiments relate to an equalization circuit, which may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense amplifier. An equalizer may be connected to the input to the first sense amplifier to provide an equalizing voltage to the input to the first sense amplifier. The input to the first sense amplifier may be equalized by the equalizing voltage independent from the input to the second sense amplifier.

Abstract: A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the memory device, and disabling the persistent auto precharge mode of operation in response to the applied disable command. Memory devices operating according this method may be used in memory systems that infrequently experience page hits, such as server systems, while the ability to disable the persistent auto precharge mode allows such memory devices to be used in systems that frequently experience page hits, such as graphics or input/output applications.

Abstract: A hierarchical movie is provided. A hierarchical movie is a movie that contains one or more embedded movies. Embedded movies may themselves contain embedded movies. Each movie contains zero or more media sequences. Within a hierarchical movie, media sequences that should be edited together may be grouped together using embedded movies. The media sequences of a hierarchical movie may be sequenced during playback based on a different time coordinate system than the time coordinate system that governs any embedded movies. This allows a movie to contain both time-based and time-independent media sequences. Also, the relative timing of events in the movie may vary from performance to performance. The hierarchical movie structure allows movies to be used as user interface controls, and even as field-sensitive databases.

Abstract: A sense amplifier is connected to a pair of bit lines to read/write data. A bit line equalizer equalizes the potentials of the pair of bit lines. A sense amplifier equalizer equalizes the potentials of two power supply nodes of the sense amplifier. The sense amplifier equalizer is constituted by two types of MOS transistors whose gate oxide films have different thicknesses. MOS transistors of one type are formed in a thick film type Tr area. MOS transistors of the other type are formed in a thick film type Tr area.

Abstract: A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.

Abstract: A parallel sense amplifier includes a measuring branch for receiving an input current to be measured, a plurality of reference branches each one for receiving a reference current, and a plurality of comparators each one for comparing a voltage at a measuring node along the measuring branch with a voltage at a reference node along a corresponding reference branch; the amplifier further includes a multiple current mirror for mirroring the input current into each reference branch.

Abstract: A connection gate circuit includes first and second N channel MOS transistors connected in series between a first bit line of a pair of bit lines and a first global IO line of a pair of IO lines, and third and fourth N channel MOS transistors connected in series between a second bit line of the pair of bit lines and a second global IO line of the pair of IO lines. The first and second N channel MOS transistors have their gates receiving a sense amplifier activation signal activating a sense amplifier. The third and fourth N channel MOS transistors have their gates receiving a column selection signal.

Abstract: Methods and apparatus for refreshing a dynamic memory cell in a memory circuit are provided, wherein the required time between refresh operations may be increased by increasing the potential difference between a high charge potential and common center potential used during a refresh mode relative to the potential difference between the high charge potential and the common center potential used during read or write modes.

Abstract: A semiconductor readout circuit reads out a potential of each of plural data lines by comparing the potential with a potential of a common reference data line, using a sense amplifier provided for each of the data lines. This semiconductor readout circuit has a current control circuit provided for each of the data lines. The current control circuit controls the potential of the corresponding one of the data lines so that a potential difference between the potential of the corresponding data line and the potential of the reference data line can be reduced based on an output as to the potential difference detected by the sense amplifier.

Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A sense amplifier connected to first and second bit lines, comprising means for precharging said bit lines to a high voltage, means for connecting one or the other of the bit lines to a memory cell, said connection causing according to the state of the memory cell a maintaining of the bit line at the high voltage or a voltage reduction, first and second transistors respectively controlled by the first and second bit lines, and, in series with the first and second transistors, a controllable means for the current through the transistor controlled by the bit line connected to the memory cell to be greater than the current through the other transistor when the voltages of the two bit lines are at the high voltage.

Abstract: A cross-point memory includes a plurality of memory cells, a plurality of global word lines, a plurality of local word lines, and a plurality of global bit lines. At least a given one of the global word lines is configurable for conveying a write current for selectively writing a logical state of one or more of the memory cells. Each of the local word lines is connected to at least one of the memory cells for assisting in writing a logical state of the at least one memory cell corresponding thereto. Each of the global bit lines is connected to at least one of the memory cells for writing a logical state of the memory cell corresponding thereto. The memory further includes a plurality of selection circuits, each of the selection circuits being operative to electrically connect a given one of the local word lines to a given one of the global word lines in response to a control signal applied thereto.

Abstract: A sense amplifying circuit and a bit comparator having the sense amplifying circuit. The sense amplifying circuit may include a selecting unit, a sensing unit, a latching unit, an output unit, and a switching unit. The selecting unit may select one pair from a first pair of a first signal and a first inverted signal and a second pair of a second signal and a second inverted signal, in response to a selection signal and an inverted selection signal. The sensing unit may sense voltage levels of one pair of signals selected from the first pair and the second pair. The latching unit may precharge first and second nodes in response to a clock signal and controls voltage levels of the first and second nodes in response to a sensing result of the sensing unit. The output unit may invert the voltage levels of the first and second nodes to generate first and second output signals. The switching unit is capable of controlling the operation of the selecting unit in response to the clock signal.