Abstract: The present disclosure includes apparatuses and methods for data replication. An example apparatus includes a plurality of sensing circuitries comprising respective sense amplifiers and compute components and a controller. The controller may be configured to cause replication of a data value stored in a first compute component such that the data value is propagated to a second compute component.

Abstract: The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.

Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.

Abstract: A sub-wordline driver for a semiconductor memory device is disclosed. The sub-wordline driver includes a selection controller and a plurality of driving circuits. The selection controller selectively outputs any one of a first-group wordline selection signal and a second-group wordline selection signal in response to a selection signal and a wordline drive signal. The plurality of driving circuits selectively output any one of a plurality of sub-wordline drive signals in response to a main wordline drive signal, the wordline drive signal, the first-group wordline selection signal, and the second-group wordline selection signal.

Abstract: The present disclosure includes apparatuses and methods for data replication. An example apparatus includes a plurality of sensing circuitries comprising respective sense amplifiers and compute components and a controller. The controller may be configured to cause replication of a data value stored in a first compute component such that the data value is propagated to a second compute component.

Abstract: A circuit device includes a positive phase signal line, a negative phase signal line and a single-ended signal line. The positive phase signal line includes a first positive-phase-signal-line terminal and a second positive-phase-signal-line terminal for transmitting a first signal. The negative phase signal line includes a first negative-phase-signal-line terminal and a second negative-phase-signal-line terminal for transmitting a second signal. The single-ended signal line is disposed between the positive phase signal line and the negative phase signal line, and includes a first single-ended signal line terminal and a second single-ended signal line terminal for transmitting a single-ended signal. The first signal of the positive phase signal line causes a first noise on the single-ended signal line. The second signal of the negative phase signal line causes a second noise on the single-ended signal line. The first noise and the second noise eliminate one another.

Abstract: The present disclosure provides a test system, and a method of operating the same. The test system is for testing a DRAM (dynamic random access memory). The DRAM includes an array including a first memory row and a second memory row. The first memory row includes a first word line. The second memory row includes a second word line and a test cell. The second word line is immediately adjacent to the first word line. The test cell is controllable by the second word line. The test system includes a work station. The work station is configured to evaluate a row hammer effect on the second memory row based on a leakage charge, caused by an AC component of a pulse applied to the first word line, from the test cell.

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The wordline driver may include multiple transistors. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. Gates of the read assist transistor and at least one transistor of the multiple transistors may be coupled together. While activated, the read assist transistor may provide a read assist signal to the wordline when the wordline is selected and driven by the wordline driver.

Abstract: The present disclosure includes apparatuses and methods related to a shift skip. An example apparatus comprises a plurality of sensing circuitries, comprising respective sense amplifiers and respective compute components. A controller is configured to, responsive to a mask data unit associated with a first sensing circuitry having a particular value, cause a data value to be shifted from a second sensing circuitry to a third sensing circuitry without shifting the data value to the first sensing circuitry, wherein the first sensing circuitry is physically located between the second sensing circuitry and the third sensing circuitry.

Abstract: The present disclosure includes apparatuses and methods for data replication. An example apparatus includes a plurality of sensing circuitries comprising respective sense amplifiers and compute components and a controller. The controller may be configured to cause replication of a data value stored in a first compute component such that the data value is propagated to a second compute component.

Abstract: The invention provides a flash memory device, which comprises a controller, a plurality of flash memories, a switcher, a power supply module, and a voltage detection circuit. When the system voltage is higher than a voltage threshold, the voltage detection circuit outputs an enable signal to the switcher to turn on the switcher, the system voltage is provided to the power supply module, the power supply module executes a charging process by the system voltage, and generates an output voltage based on the system voltage. The output voltage is an operating voltage of the controller and the flash memories. When the system voltage is lower than the voltage threshold, the voltage detection circuit outputs a disable signal to the switcher to turn off the switcher, the system voltage is inhibited to provide to the power supply module, the power module generates the output voltage by executing a discharging process.

Abstract: A sense amplifier circuit includes: a data line; a sense amplifier output node; a keeper circuit; a logic gate; a noise threshold circuit; and an inverter. The keeper circuit includes a first transistor and a second transistor connected in series and coupled between a first power node and the data line. A gate node of the first transistor is coupled to the sense amplifier output node. The logic gate has an input connected to the bit line and an output connected to the sense amplifier output node. The noise threshold circuit includes: a third transistor and a fourth transistor connected in series between a second power node and the sense amplifier output node; and an inverter connected between a gate node of the third transistor and the sense amplifier output node.

Abstract: Various implementations described herein are directed to a device for dynamic capacitance balancing. The device may include a sense amplifier configured to receive complimentary data signals from complimentary bitlines and provide first and second sensed data signals based on received complimentary data signals. The second sensed data signal may be a compliment of the first sensed data signal. The device may include a balance coupler configured to receive the second sensed data signal from the sense amplifier and provide a modified second sensed data signal having capacitance similar to the first sensed data signal. The device may include a latch configured to receive the first sensed data signal from the sense amplifier, receive the modified second sensed data signal from the balance coupler, and provide a latched data signal based on the first and modified second sensed data signals.

Abstract: A method of maintaining a voltage level of a bit line of a sense amplifier circuit includes providing a power supply voltage at a power supply node, receiving the power supply voltage from the power supply node with an NMOS transistor, and maintaining a voltage level of the bit line by supplying sufficient current with the NMOS transistor to compensate a leakage current of the bit line. The method includes receiving the voltage level of the bit line with a noise threshold control circuit, inverting the voltage level with the noise threshold control circuit, and driving a sense amplifier output with the noise threshold control circuit.

Abstract: A metal trench de-coupling capacitor structure includes a vertical trench disposed in a substrate, an insulating layer deposited on the sidewall of the vertical trench, an inter-layer dielectric layer covering the substrate and the insulating layer, and a metal layer penetrating the interlayer dielectric layer to fill up the vertical trench. The metal layer is electrically connected to a power source.

Abstract: The present disclosure discloses an output buffer, a gate electrode driving circuit and a method for controlling the same. The output buffer includes a first transistor, a second transistor and an input signal control unit. The input signal control unit controls an input signal to obtain a pull-up signal and a pull-down signal, which are input to input terminals of the first transistor and the second transistor, respectively. The above output buffer uses the input signal control unit to divide one input signal into two signals, i.e., the pull-up signal and the pull-down signal.

Abstract: A semiconductor device and a method of operating the same are provided. The semiconductor device includes a memory block including a plurality of pages having a plurality of first cells and a plurality of second cells, a circuit group configured to read first cells and second cells of a selected page of the pages a strobe signal control circuit configured to store source bouncing information generated during a read operation of the first cells of the selected page and output a strobe signal based on stored information, and a control circuit configured to control the circuit group in response to the strobe signal during a read operation of the second cells of the selected page.

Abstract: A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.

Abstract: In a method, a current value of a memory cell of a tracked circuit is determined. The memory cell is coupled with a data line. A tracking current value of a tracking memory cell of a tracking circuit is determined. The tracking memory cell is coupled with a tracking data line. A current value of a transistor of the tracking circuit is determined, based on a current value of a transistor of the tracked circuit, the current value of the memory cell, and the tracking current value of the tracking memory cell. A signal of the tracked circuit is generated based on a signal of the tracking circuit.

Abstract: Memory sense amplifier voltage modulation. An embodiment of a an apparatus includes a memory including a sense amplifier; a first node for an high voltage rail for the sense amplifier and a second node for a low voltage rail for the sense amplifier; one or more elements to provide a first voltage to the first node and a second voltage to the second node; and a voltage control engine to control the one or more elements, where the voltage control engine is to independently set a value of the first voltage and a value of the second voltage over time.

Abstract: Methods, circuits, and systems for phase change memories. A matching bit line, on which no data-containing PCM cells have been selected, is used to cancel out time-dependent current components due to parasitic capacitive and leakage resistance loading of bit lines. This can effectively allow direct comparison of the current from the phase change memory cell to the desired reference current, at a time before the voltage of the first bit line permits stable operations using DC comparison.

Abstract: A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage.

Abstract: An electronic system, a reduced-noise reference voltage platform for a voltage converter device, and a method of manufacture of a reduced-noise reference voltage platform for a voltage converter device are disclosed. For example, the reduced-noise reference voltage (e.g., ground) platform includes a first conductor unit, a second conductor unit, and an insulator unit interposed between a first surface of the first conductor unit and a first surface of the second conductor unit. The reduced-noise reference voltage platform also includes a phase terminal connected to the first conductor unit, and a reference voltage (e.g., ground) terminal connected to the second conductor unit, wherein a second surface of the second conductor unit forms a platform coupled to the reference voltage (e.g., ground).

Abstract: Methods for programming memory cells. One such method for programming memory cells includes generating an encoded stream using a data stream and programming the memory cells using the encoded stream to represent the data stream. A particular bit position of the encoded stream has a first voltage level when the particular bit position of the data stream has a particular logical state, and the particular bit position of the encoded stream has either a second voltage level or a third voltage level when the particular bit position of the data stream has a logical state other than the particular logical state.

Abstract: Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain, and further including an amplifier stage coupled to the bias circuit to receive the bias voltage and configured to amplify a input current at an input-output node, a loop gain of the current amplifier stage is controlled at least in part to the bias voltage.

Abstract: A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.

Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.

Abstract: In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power consumption in a device. The first signal is combined with the second signal to generate a combined signal, and at least a portion of the second signal is shifted in time to cause a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal.

Abstract: A semiconductor storage apparatus according to the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of pairs of bit lines, a plurality of sense amplifiers, a pair of common data lines, a data-to-be-written output circuit configured to, in writing data, set voltages of the common data lines forming the pair, a column selection signal output unit configured to output a plurality of column selection signals, and a plurality of column selection gates, in which in writing the data, the column selection signal output unit selectively turns on one of the column selection gates by setting each of voltages of the column selection signals to one of a level of a higher-potential power supply voltage and a level of a lower-potential power supply voltage, before activating the sense amplifiers.

Abstract: A semiconductor memory device includes a first core region and a second core region disposed along a first reference line parallel to a major axis, the first reference line connecting an input pad and an output pad; first and second cell blocks disposed in the first core region along the first reference line; third and fourth cell blocks disposed in the second core region along the first reference line; and a repeater positioned between the third and fourth cell blocks, and configured to receive data outputted from the first cell block or the second cell block, amplify the received data and transfer the amplified data to a second global input/output line. Reducing the number of needed global input/output lines leads to layout area reduction. Moreover, since repeaters are driven in read operations for a limited number of cell blocks, signal gain may be reduced, thus reducing overall power consumption.

Abstract: A method for providing a SRAM cell having a dedicated read port separated from a write port includes providing a first and a second bit-line placed in parallel forming a complementary bit-line pair for the dedicated read port, and providing a third and a fourth bit-line placed in parallel forming a complementary bit-line pair for the write port. The method further includes providing a positive voltage supply line disposed between a first and a second ground line placed in parallel, providing a first and a second metal line adjacently flanking and in parallel to the first bit-line, and providing a third and a fourth metal line adjacently flanking and in parallel to the second bit-line to provide a new SRAM cell structure having a balanced read and write operation speed and an improved noise margin.

Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.

Abstract: A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include a digital control circuit configured to control the clock and data recovery circuit. The digital control circuit and the clock and data recovery circuit may be formed on a single substrate.

Abstract: Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first voltage, and a measurement node is charged to a second voltage, the second voltage being less than the first voltage. The measurement node is proportionally coupled to the word line. A voltage on the measurement node is compared with a reference voltage. A signal is generated, the signal being indicative of the comparison. Whether a leakage current of the word line is acceptable or not can be determined based on the signal.

Abstract: A semiconductor apparatus with an open bit line structure includes a memory bank including a plurality of memory cell blocks and dummy mats, in which a plurality of bit lines are formed, a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference, and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode.

Abstract: A sense amplifier includes a first transistor. The first transistor includes a gate connected to a bit line, and a first source/drain (S/D) electrically coupled with a global bit line. The sense amplifier further includes a second transistor. The second transistor includes a gate connected to a first signal line, and a first S/D coupled to the global bit line, wherein the second transistor is configured to pre-charge the bit line.

Abstract: A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation.

Abstract: Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, and circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, memory devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.

Abstract: A current-limiting device may be configured to be placed along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus.

Abstract: Configurable parameters may be used to access NAND flash memory according to schemes that optimize such parameters according to predicted characteristics of memory cells, for example, as a function of certain memory cell device geometry, which may be predicted based on the location of a particular device within a memory array.

Abstract: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Abstract: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Abstract: The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.

Abstract: A device, computer system, and method are disclosed. In one embodiment, the device includes a memory buffer driver circuit that can drive signals on a memory channel at a given voltage level. The voltage at the voltage level is supplied to the memory buffer driver circuit from a rail of a power delivery network. The voltage level exhibits a repeatable fluctuation cycle at a resonant frequency of the power delivery network. The device also includes an on-die termination logic circuit that asserts a first termination resistance on the memory channel after the memory channel enters an idle state but before the voltage level reaches a peak of the repeatable fluctuation cycle. The on-die termination logic circuit then deasserts the first termination resistance on the memory channel at a later point in time.

Abstract: Methods for programming, memory devices, and methods for reading are disclosed. One such method for programming a memory device (e.g., an SLC memory device) includes encoding a two level data stream to a three level stream prior to programming the memory.

Abstract: A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications.

Abstract: A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM cell. The critical areas of the delays may be positioned so that a common line of sight cannot be made between each delay and a circuit node.