Abstract: An auxiliary line driver (514) able to sense data driven on a signal path (502) by a primary line driver (512), and then drive the data on the signal path (502). The auxiliary driver (514) allows a small primary line driver (512) to drive a large load, or a large number of loads (504, 506) without consuming a large area in the region where the primary line driver (512) is fabricated. The auxiliary line driver is particularly useful for driving the memory array of a micromirror device, especially during a block clear operation in which a large number of memory cells (506) are written to simultaneously. When the auxiliary line driver (514) receives an enable signal (518), the auxiliary line driver drives the last input provided to the input of the auxiliary line driver (514).

Abstract: A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.

Abstract: An integrated circuit comprising a first bitline pair 310 on a first bitline level which is adjacent to a second bitline pair 320 on a second bitline level is provided. The first bitline pair comprises m twists 340, where m is a whole number≧1 and the second bitline pair comprises n twists 350 and 351, where n is a whole number ≠m. The twists transform coupling noise from adjacent bitline pairs into common mode noise, which results in improved signal margin.

Abstract: A flash memory device (100) provides for simultaneous read and write operations in two banks (194, 196) of flash memory cells. A plurality of output circuits (182) switch large amounts of current during reading of stored data. To reduce noise in read circuitry (174) and write circuitry (142), a separate power supply bus (204) and ground bus (208) is provided for the output circuits. The power supply bus is independent of the power supply bus which serves the internal circuitry, such as the read circuitry and the write circuitry.

Abstract: Integrated circuit memory devices include one or more input receivers that have a reference voltage input terminal. A conductor electrically couples the reference voltage input terminals to a reference voltage, and a capacitor is connected between the conductor and a first ground voltage. Preferably, the location of the connection between the capacitor and the conductor is selected in accordance with the electrical characteristics of the input receivers. Accordingly, the capacitor may reduce fluctuations or noise in the reference voltage applied to the reference voltage input terminals of the input receivers. The fluctuations or noise in the reference voltage may cause the input characteristics and/or the set-up and hold times of the input receivers to vary with respect to one another. A reduction in fluctuations or noise in the reference voltage may result in more consistent input characteristics among the input receivers and more consistency in the set-up and hold times.

Abstract: First and second global input/output lines are twisted between first and second main blocks. First and second SD signal lines in the first main block are respectively arranged adjacent to first and second global input/output lines. First and second SD signal lines in the second main block are respectively arranged adjacent to the second and first global input/output lines. An SD signal supplied for the first or second SD signal line makes noises applied to the first and second global input/output lines identical, so that an influence by the noises is substantially eliminated between the first and second global input/output lines. As a result, the global input/output line is provided with higher resistance to noise without any increase in a layout area.

Abstract: The present invention discloses a digital-to-analog converter (DAC) with noise equalized and a device capable of equalizing noise in SRAM. In the DAC, when the BLANK signal is high, a transient current still flows to ground for equalizing noise. The device capable of equalizing noise in SRAM comprises a dummy read/write memory cell for adding read/write operations and a auto-detection circuit for detecting when to add read/write operations.

Abstract: An apparatus (and method) is provided that reduces noise in an embedded DRAM caused by noise in the Vdd supply. A circuit switches or decouples the bit line precharge voltage supply from the memory array to reduce noise in the memory array at time of bit line sensing. In addition, another circuit is utilized to switch or decouple the memory cell plate voltage supply from the memory array to reduce noise in the memory array at the time of bit line sensing. The circuit(s) includes a switch to perform the decoupling, or alternatively, include a switch coupled in parallel with a high impedance.

Abstract: A method and circuit for rapidly equilibrating paired digit lines of the memory array of a dynamic random access memory device during testing of the memory device includes a plurality of pass gates which are used to connect the equilibrating voltage directly to the paired digit lines, bypassing the conventional equilibration circuitry of the memory device. The pass gates used are contained in spare rows of the memory array and are fabricated as part of the memory device. The pass gates are enabled by activating the row lines for the spare rows while the memory device is being operated in a test mode.

Abstract: This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control means cutting off the first control signal line in case that predetermined number of control signals are abnormal, and a second voltage control means cutting off the second control signal line in case that predetermined number of control signals are abnormal.

Abstract: A method is provided for reducing the effects of power supply distribution related noise in an integrated circuit, the integrated circuit having a power supply bus, a ground bus, a DRAM-technology capacitor, and a load circuit. The method includes forming the DRAM-technology capacitor adjacent the load circuit, and connecting the DRAM-technology capacitor directly between the supply voltage bus and the ground voltage bus.

Abstract: An output circuit is constructed such that a load capacitor is not charged by an external power supply but by a first charge storage element within a semiconductor chip that is charged before the load capacitor. The charge stored in the load capacitor is released not directly to the ground but to a second charge storage element within the semiconductor chip and discharged before discharging of the load capacitor.

Abstract: In a region of a transfer gate provided in a central portion of multilevel writing bit lines, noise in adjacent bit lines at the time of re-writing is counteracted by reversing the order of complementary bit line pair every other pair. With this, in a multilevel dynamic type semiconductor memory device in which one sense amplifier commonly includes a plurality of bit lines and some of the bit lines are selectively activated in a time-dividing manner, the influence of noise between the adjacent bit lines can be deleted.

Abstract: A DRAM having open-bit-lines wherein noise to be impressed to word-lines can be restricted within a certain range. The DRAM includes a logic reversing circuit for reversing the logic levels of a portion of bits in a bit sequence to be stored, and a circuit for recording and detecting whether the logic levels of the portion of the bits is reversed for each stored bit sequences. Logic reversal takes place when one logic level predominates the bits of the bit sequence. Examples of the portion of bits in a bit sequence subject to logic level reversal would be the odd-numbered bits or even-numbered bits in a sequence.

Abstract: A sensing circuit for sensing the binary state of a memory cell in a non-volatile memory device that includes an amplifier electrically connected to the memory cell and current generating circuitry connected to the amplifier for generating a first current in response to one binary state of the memory cell and a second current in response to another binary state of the memory cell. The sensing circuit also includes circuitry to speed initialization of the current generating circuitry and circuitry to prevent transient noise in the output of the sensing circuit during initialization of the current generating circuitry.

Abstract: A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123<n>, LPHe<n>, LPHo<n>) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires.

Abstract: A method is provided for reducing the effects of power supply distribution related noise in an integrated circuit, the integrated circuit having a power supply bus, a ground bus, a DRAM-technology capacitor, and a load circuit. The method includes forming the DRAM-technology capacitor adjacent the load circuit, and connecting the DRAM-technology capacitor directly between the supply voltage bus and the ground voltage bus.

Abstract: The wordline driving circuit includes a noise prevention circuit in each control circuit of a subwordline drive selector. When a row signal from a sub-row decoder indicates that the associated control circuits are not to drive wordlines associated therewith, the noise prevention circuit in each control circuit is triggered to remove noise from the wordline.

Abstract: To reduce both the noise level according to separation or short-circuitng of the electrical supply line of the sense amplifiers and the electrical supply line of the word line driving circuit and to effectively prevent destruction of the stored data in the nonselecteded memory cell. Electrical supply line (Vssw) of the power supply voltage with respect to word line driving circuit (SWD) and electrical supply line (Vssa) of power supply voltage with respect to sense amplifier driving circuit (SAD) are arranged separately in memory array area 2 (e.g., in the space in the row direction of memory array (SMAx,y)) and connected to shared electrical supply wiring (Vsso) within peripheral circuit area 3.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: There is disclosed, for use in an x86-compatible processor having a physically-addressable cache, an address translation device for translating linear addresses received from a plurality of linear address sources and selectively accessing physical addresses, linear addresses, and controls signals stored in the address translation device.

Abstract: A data reading circuit for a semiconductor memory device is provided that reduces noise effects by stably operating a latch sense amplifier during a high speed operation. The data reading circuit produces a stable output voltage. The data reading circuit includes a sense amplifier controller that generates a first pulse signal having a time width for fully equalizing a sense amplifier. The sense amplifier generates the first pulse signal by delaying an address transition detection signal while a high level read signal is being outputted. The sense amplifier controller also combines the address transition detection signal and the first pulse signal to output a second pulse signal. A first current mode dual latch sense amplifier senses a data signal from a memory cell in accordance with the second pulse signal from the sense amplifier controller and transfers the sensed data in accordance with the first pulse signal.

Abstract: An improved cell array and sense amplifier structure and embodied method are disclosed. The structure exhibits an improved noise characteristic by decreasing a coupling noise which occurs between bit lines by using, as a reference bit line, a bit line from an array of memory cells other than the array to which the bit line belongs, thus forming a predetermined spacing between a bit line and a reference bit line. The structure includes: an upper sense amplifier having an input terminal commonly connected with a first pair of bit lines of an adjacent first cell array and another input terminal commonly connected with a first pair of bit lines of a non-adjacent second cell array; and a lower sense amplifier having an input terminal commonly connected with a second pair of bit lines of the second cell array and another input terminal connected with a second pair of bit lines of the first cell array.

Abstract: An activation arrangement for reducing worst case localized supply noise for shared circuitry includes a first group of circuit blocks, a second group of circuit blocks, a shared circuit, and a selection circuit. The first and second circuit blocks are arranged symmetrically about the shared circuit. The selection circuit is configured to selectively activate each circuit block in the first group and, concurrently, a circuit block in the second group corresponding to the circuit block of the first group. The selection circuit is configured so that when the circuit block of the first group that is closest to the shared circuit is to be activated, the corresponding circuit block in the second group is the circuit block that is farthest from the shared circuit.

Abstract: Apparatus and methods for determining the robustness of a device to soft errors generated by alpha-particle and/or cosmic ray strikes by measuring the charge Q.sub.c that flow through a node of an equivalent diode structure when the diode structure is impinged by a light pulse with energy equivalent to that of the alpha-particle and/or cosmic ray strikes. In one embodiment, the method includes the steps of producing a light pulse having a light pulse energy, the light pulse energy is at a first light pulse energy; applying the light pulse to the device at a predetermined location, the predetermined location having an area and a geometry; varying the light pulse energy to a second light pulse energy which generates a soft error; detecting soft errors in the device; providing a diode having the same area and geometry as the predetermined location; applying the light pulse with the second light pulse energy to the diode; and determining the amount of charges that flow through the diode.

Abstract: A pull-down circuit in a sense amplifier, such a sense amplifier in a memory integrated circuit, includes a pull-down transistor having a drain coupled to a common node, a gate, and a source coupled to ground. An inverter provides a gate control signal to the gate of the pull-down transistor. A choke transistor has a drain coupled to a power terminal of the inverter, a gate, and source coupled to the power supply voltage. A regressive drive bias circuit is coupled to the gate of the choke transistor and provides a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor and provides a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.

Abstract: A single ended sensing scheme amplifies the logic state stored within a non-volatile memory circuit by relying upon three stages, a clamping circuit, a first operational amplifier and a second operational amplifier. The clamping circuit clamps the voltage at a voltage level with a small voltage swing between the logic states. The first stage and second stage operational amplifiers increase the clamped voltage level. A reference memory circuit ensures that the sensing scheme output is properly adjusted to compensate for voltage and temperature variations as well as noise injection from the power supply and ground.

Abstract: A sense circuit for a DRAM circuit in which small potential difference between bit lines and is produced when the memory cell in the memory cell array is connected to one of the bit lines. The sense circuit starts sensing and amplifying when the sense starting signal changes to "L" level. An inverter provides a sense activating signal of "H" level to an NMOS device, while another inverter provides a sense activating signal of "L" level to a PMOS device. Sense amplifiers 33 are then activated and the potential difference between the bit lines and is amplified. Since the "L" level of the sense activating signal that is generated by the inverter is set to a value midway between a first power potential VSS and a second power potential VCC, the conductive resistance of the PMOS device is higher than that of a conventional circuit supplied with the first power potential VSS. Consequently, the voltage drop due to the PMOS device increases and power noise is reduced.

Abstract: In an SRAM for SNM measurement, the original word line of the SRAM cell for SNM measurement is divided into two segments for SNM measurement, wherein one segment is connected to the first node of the SRAM cell for SNM measurement, another segment is connected to the second node of the SRAM cell for SNM measurement. In addition, an adjacent word line adjacent to the SRAM cell for SNM measurement is connected to the SRAM cell for SNM measurement to form the word line of the SRAM cell. Therefore, the process of the SRAM for SNM measurement can be improved only by modifying the mask for the layout of the polysilicon layers in conventional ones.

Abstract: A power line noise prevention circuit for a semiconductor memory device which can suppress noises on supply and ground voltage lines with no conventional degradation in operation speed when internal circuits consuming a large current amount are sequentially operated. When a plurality of data output buffers output high data at the same time, the power line noise prevention circuit applies a high voltage to the supply voltage line for the operation time to prevent a supply voltage from being reduced in level. To the contrary, when a plurality of data output buffers output low data at the same time, the power line noise prevention circuit applies a substrate voltage to the ground voltage line for the operation time to prevent a ground voltage from being increased in level.

Abstract: A semiconductor memory device according to this invention has a hierarchical bit line structure where a plurality of local bit lines are provided in parallel to each global bit line and some of the local bit lines in the column direction are connected to the global bit line. Such memory device further has an open bit line structure where global bit lines are provided on both sides of sense amplifiers, and has bit-line transfer circuits, provided between the global bit lines and the sense amplifiers, for isolating the global bit lines from the sense amplifiers when the sense amplifiers are activated. The use of the hierarchical bit line structure in combination with the open bit line structure enhances the layout efficiency of memory cells, and the provision of the bit-line transfer circuits overcomes a problem of erroneous data reading which would otherwise be caused by bit line noise inherent to the open bit line structure.

Abstract: An amplifier 300 includes a differential pair of transistors 307a, 307b. A third transistor 306 controls current through transistors 307a, 307b of the differential pair in response to a stepped control signal.

Abstract: A semiconductor memory device having a ground noise isolation circuit which prevents the influence of noise which occurs due to ground bouncing which causes erroneous data reading of a memory cell. The ground noise isolation circuit generates a pulse signal having a predetermined width in accordance with a chip enable signal for controlling the output of a data output unit when the data output unit outputs data and by disconnecting a sense amplifier driving transistor during the generation of the pulse signal.

Abstract: A memory read circuit includes an input to be connected to a bit line to which there are connected memory cells, and an output to produce an output logic potential. A current source produces a first current and a current-voltage converter produces the output logic potential. This potential represents the value of a second current obtained by the rerouting of a part of the first current towards the bit line when one of the cells is read, so that once the bit line is charged, the value of this second current is determined solely by the state of the selected cell and is independent of the equivalent capacitive load of the bit line.

Abstract: A memory drive circuit includes at least one memory module constructed of a plurality of memory elements, a memory controller for driving said memory module, and a buffer, disposed between the memory module and the memory controller, for receiving a drive signal from the memory controller and transmitting the received drive signal to the memory module. Signal reflection noises produced in the memory module are absorbed by the buffer.

Abstract: A semiconductor device reduces power supply noise during read operations of a memory device. The semiconductor device includes a plurality of read circuits, a plurality of control circuits and a plurality of output circuits. The read circuits are coupled to the memory device and responsive to a first enable signal to provide readout data during an active period thereof. The output circuits receive the readout data and output the readout data to an external device in response to a second enable signal. The control circuits are coupled between the read circuits and the output circuits and control the output circuits. The control circuits provide output data which is gradually changed to a preset logical value during the active period and to a value equal to the value of the readout data from the read circuits after termination of the active period.

Abstract: Disclosed is a circuit for removing noise components included in a signal which an oscillator generates by using an integrator and hysteresis characteristic. The signal is oscillated by an oscillator. A square-wave generating inverter receives a sine wave signal including noise components oscillated by a quartz crystal oscillator circuit and then generates a square-wave signal having improved RC and integrator characteristics, and provides the generated square-wave signal to a Schmitt trigger. The Schmitt trigger receives the square-wave signal including the noise components from the square-wave generating inverter and removes the noise components included in the received square-wave signal. The circuit can remove noise components included in a signal oscillated by an oscillator due to a surrounding influence such as a temperature. Therefore, state clocks which is used in a microprocessor and a microcontroller, may be generated.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: A low voltage high density memory device is described. The memory device uses isolation transistors to adjust the voltage stored on memory cells. The memory device is designed to reduce the differential voltage between memory cells storing different data states. A method is described for reducing leakage current of the memory cells to decrease the need for excessive refresh operations. The memory device is described as operating on a one volt supply and producing a 250 mv digit line swing.

Abstract: A memory array (10) implemented by an integrated circuit is provided. The memory array (10) includes a bank of standard array cells (12) arranged in rows and columns. The bank of standard array cells (12) includes a plurality of rows of array cells (14) operable to provide memory storage and a plurality of rows of dummy cells (16) operable to provide a reference voltage level. A row decode block (22) is coupled to the bank of standard array cells via a plurality of wordlines (18) which include array cell wordlines and dummy cell wordlines. A sense amplifier block (24) is coupled to the bank of standard array cells (12) via a plurality of bitlines (20). The sense amplifier block (24) includes a plurality of sense amplifiers (26) coupled to the bitlines.

Abstract: Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by simplifying the sensing process.

Abstract: An apparatus and method for message management using nonvolatile analog signal recording and playback is disclosed. The device is an integrated circuit with interface circuitry for use as a peripheral device to a microcontroller or a microprocessor-based system. The integrated circuit is complete with differential analog inputs, auto attenuation to improve signal quality, filter, fixed references including a band gap reference, trimming, memory array, multiple closed loop sample and hold circuits, column device, row decoder, address counters, master oscillator, chip function timing circuits, and a serial peripheral interface (SPI) and circuits on a single chip. The integrated circuit is interfaced with a host microcontroller through the SPI. The host microcontroller can send a number of commands to the integrated circuit through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options.

Abstract: The invention provides a semiconductor storage device which reduces noise arising from a coupling capacitance between adjacent digit lines in a memory cell array region having multiple bit input and output terminals. A plurality of first and second digit line selection circuits connect first and second selection digit line pairs to first and second data buses, respectively, such that at least one of non-selected digit line pairs is interposed between a selected digit line pair selected by the first digit line selection circuits and another selected digit line pair selected by the second digit line selection circuits.

Abstract: In a data transfer apparatus powered by first and second power supply voltages, a data output circuit generates first complementary output signals, a data transfer circuit having a large load capacitance transfers the first complementary output signals to generate second complementary output signals, and an amplifier circuit amplifies the second complementary output signals to generate third complementary output signals. A first transfer gate circuit is connected between the data output circuit and the data transfer circuit. A second transfer gate circuit is connected between the data transfer circuit and the amplifier circuit. The first, second and third complementary output signals are caused to be approximately at an intermediate level between the first and second voltages.

Abstract: A variable capacitor for integrated circuits used as a decoupling capacitor that operates at both low and high frequencies is disclosed. Based upon a programmable input signal, the decoupling capacitance of the circuit varies within a specific range providing a vehicle for testing decoupling capacitance requirements of new integrated circuits and functions and new silicon processes. The programmable input signal switches a transistor from the saturated region of operation to the unsaturated region of operation, varying the decoupling capacitance of the transistor. By providing circuitry to control the switching of the transistor, the circuit operates at both low and high frequencies, reducing the negative impacts of transistor channel resistance during high frequency operation.

Abstract: A power line coupling prevention circuit for a semiconductor memory device which has a plurality of memory cell arrays and supply and ground voltage lines formed between adjacent ones of the memory cell arrays. The power line coupling prevention circuit comprises a capacitor formed between the supply and ground voltage lines, and a switching device connected to the capacitor, for making the capacitor conductive. The switching device is operated in response to a data output buffer enable control signal, The capacitor has one side connected to one of the supply and ground voltage lines and the other side connected to the switching device. The switching device is adapted to control the connection of the capacitor between the supply and ground voltage lines in a read operation.

Abstract: A circuit for generating and resetting timing signals used for reading a memory device, includes first detecting circuit means for detecting a state transition of address digital signals of the memory device, the detecting means being suitable of generating a start digital signal of a read operation represented by a digital pulse of a prescribed duration upon a state transition of at least one of said address signals, second circuit means activated by said start signal for generating a timing signal for the read operation of the memory device, and third circuit means driven by said start digital signal for generating resetting signals for said timing signals, and fourth circuit means for detecting than said start signal has a duration shorter that said prescribed duration and for determining a consequent extension of the duration of said start signal sufficient to assure the generation of said resetting signals.

Abstract: A pull-down circuit in a sense amplifier, such a sense amplifier in a memory integrated circuit, includes a pull-down transistor having a drain coupled to a common node, a gate, and a source coupled to ground. An inverter provides a gate control signal to the gate of the pull-down transistor. A choke transistor has a drain coupled to a power terminal of the inverter, a gate, and source coupled to the power supply voltage. A regressive drive bias circuit is coupled to the gate of the choke transistor and provides a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor and provides a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.

Abstract: A DRAM has a sensing circuit which includes an on-chip capacitors having a total capacitance greater than about 35% of the total capacitance of the bit lines. The on-chip capacitors are coupled to a power line of the sense amplifiers and stabilizes a power supply voltage to prevent voltage drop and noise during the large sensing currents for a read/refresh cycle. A read/refresh cycle in accordance with an embodiment of the invention includes precharging bit lines and the on-chip capacitors before connecting memory transistors to the bit lines and connecting power to the sense amplifiers. Capacitors can be formed in any available space in the integrated circuit particularly in space under metal bus lines in peripheral circuitry surrounding a memory array.

Abstract: A semiconductor memory device is disclosed which comprises a regular row/column memory cell array having blocks obtained by dividing the memory cell array in the column and row directions, .Iadd.the blocks each being further divided in the column direction to form a plurality of sections, .Iaddend.a first peripheral circuit .?.irregularly.!. provided between the blocks divided in the column direction, a second peripheral circuit provided between the blocks divided in the row direction and including a first decoder, a third peripheral circuit provided between the first peripheral circuit and the respective block and including a second decoder, and .?.a fourth peripheral circuit provided at the marginal portion of the memory cell array and including bonding pads and input protection circuit.!. .Iadd.sense amplifiers provided between neighboring sections in each of the blocks.Iaddend..