Abstract: A compact sense amplifier circuit for amplifying reading signal of an EPROM includes a bit line connected to cells of the EPROM and a transistor circuit for connecting a DC power source to the bit line. The transistor circuit includes a read circuit, a write circuit, a first path for passing current when a read signal for reading one of the cells that is not written is applied to the read circuit and a second path for passing current when a read signal for reading one of the cells that is written is applied to the read circuit. The first path and the second path are arranged to pass the same amount of current, thereby reducing sensor noises.

Abstract: A system and method for minimizing memory corruption at power up and/or reset is provided. The system includes, a digitally controlled potentiometer between an adapter and the memory; and a voltage divider functionally coupled to the potentiometer. The voltage divider includes a pull-down resistor that brings down the voltage at one of the plural potentiometer pins, minimizing the chances of memory corruption at power up and/or reset. The method includes, setting the potentiometer to a resistance value such that upon power up and/or reset data cannot be written to the memory; and setting the potentiometer in an increment or decrement mode such that resistance between plural pins of the potentiometer can be increased or decreased allowing content to be written to the memory after power up and/or reset.

Abstract: An integrated memory device including a number of memory blocks including memory cells wherein the memory cells are arranged in a matrix of wordlines and bitlines, wherein the number of memory blocks including a first set of memory blocks the memory cells thereof having a first random access time and a second set of memory blocks the memory cells thereof having a second random access time, wherein the second random access time is smaller that the first random access time.

Abstract: When a command is input to a semiconductor memory device, a sub-threshold current is reduced to a predetermined value corresponding to the command. After the reduction of the sub-threshold current is completed, the semiconductor memory device starts to operate corresponding to the command.

Abstract: Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.

Abstract: Methods and apparatus for compensating offsets in a read signal generated by a sensor associated with a probe of a local-probe data storage device during read-scanning by the probe of bit-positions on a storage surface. An apparatus comprises a generator for generating an offset compensation signal, and a subtraction stage for producing an output signal dependent on the difference between the offset compensation signal and the sensor read signal at each bit-position. In some embodiments, an offset signal generator generates an offset compensation signal dependent upon a predetermined measurement of the sensor read signal. In another aspect the offset signal generator low-pass filters the sensor read signal during read scanning to generate the offset compensation signal. Particular embodiments also include a secondary offset compensation stage for applying additional offset compensation techniques to the output signal from the subtraction stage.

Abstract: The non-volatile memory device includes a current detection circuit for comparing, in data retrieve operation, storage information written in a non-volatile manner in a memory cell row with retrieval information in order to determine whether or not the storage information matches the retrieval information. The current detection circuit compares a data read current flowing through each bit line corresponding to each memory cell of a memory cell row storing the storage information with a data read current flowing through each bit line corresponding to each retrieval memory cell storing the retrieval information.

Abstract: An integrated circuit device includes a data inversion circuit configured to support an inversion mode of operation. The inversion mode of operation inverts selected ones of a plurality of N-bit words received in consecutive sequence at inputs thereof. The data inversion circuit is further configured to support a bypass mode of operation. The bypass mode of operation disables inversion of a second one of the plurality of N-bit words when a delay between receipt of the second one of the plurality of N-bit words and receipt of an immediately preceding first one of the plurality of N-bit words is greater than a predetermined time interval. Related methods are also discussed.

Abstract: A probe storage device includes an array of memory storage locations, an array of probes proximate to the array of memory storage locations, and a data density controller coupled to the array of probes. Each probe of the array of probes has a distal tip that is positioned within close proximity to a memory storage location. The probes are movable relative to the array of memory storage locations. The data density controller optionally groups the probes into at least one subset of probes. Each probe of a subset interacts identically and contemporaneously with a corresponding subset of memory storage locations.

Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.

Abstract: A dynamic on-die termination circuit for a read-only node is disclosed herein.

Abstract: Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.

Abstract: The power noise removing circuit includes a decoupling capacitor group, a repair circuit unit, a monitoring pad, and a testing unit. The decoupling capacitor group includes a plurality of decoupling capacitors that store noise flowing into an internal power line. The decoupling capacitors are DRAM cell type capacitors. The repair circuit unit controls a connection of each of the decoupling capacitors in the decoupling capacitor group to an external input power line. The monitoring pad measures the amount of current leaking from the decoupling capacitor group. The testing unit controls a connection of the decoupling capacitor group to the monitoring pad. If the decoupling capacitor group is tested as being defective, the defective decoupling capacitor group is made inoperative by disconnection from the external input power line.

Abstract: The present invention facilitates more accurate data reads by compensating for parasitic behavior—thus regulating the voltage at the drain of a core memory cell rather than at the output of a sensing circuit. More particularly, respective voltages at one or more nodes, such as the start of a bitline at a sensing circuit, for example, are adjusted to compensate for voltage drops that may occur due to parasitic behavior. Maintaining the substantially constant voltage levels at core memory cells allows comparisons to be made under ideal conditions while reducing the side leakages in virtual ground schemes. This mitigates margin loss and facilitates more reliable data sensing.

Abstract: The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

Abstract: A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.

Abstract: Methods of sensing a programmed state of a nonvolatile memory cell, as well as apparatus for carrying out the methods, are useful in memory devices. Latches in sensing devices are selectively coupled to a variable-potential node to receive a first potential to switch the latch, i.e., presetting, setting or resetting the latch. After switching, the variable-potential node may be set to an intermediate potential to increase noise immunity to the latch while holding the data value. In NAND sensing devices having a data latch and a cache latch, the variable-potential nodes of the data latch and the variable-potential nodes of the cache latch are coupled to separate ground control circuits. By independently varying the potentials applied to the variable-potential nodes of the data latch and cache latch, determined by whether the individual latch is switching or holding data, noise immunity in the data path is increased.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: A semiconductor integrated circuit includes a substrate, a digital circuit formed on a triple well formed in the substrate, a first node configured to supply a well potential of the digital circuit, a second node separate from the first node, and a substrate-potential supplying circuit, formed on the substrate, having an input node to receive an input potential from the second node and an output node to supply a substrate potential to the substrate, the substrate-potential supplying circuit having no direct-current path into which a direct current substantially flows through the input node, and configured to generate at the output node an output potential following the input potential.

Abstract: A memory device and method with reduced power consumption and improved noise performance. An illustrative embodiment provides a random access memory with an array of plural memory bit cells, having bit-latches coupled between bit-true pass-gates and bit-compliment pass-gates are organized as plural columns and rows. There are plural bit lines pairs aligned with the plural columns, each of the bit line pairs including a bit-true and a bit-compliment bit line. The bit cell pass-gates are electrically coupled to a bit-true and a bit-compliment line pair along each particular column. Plural word lines are aligned with the plural rows, each of the rows having an integer number, greater than one, of word lines aligned therewith. Each one of the integer numbers of word lines is electrically coupled to a fraction of the bit cells in its aligned row.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.

Abstract: A semiconductor integrated circuit apparatus that is capable of reducing crosstalk without increasing the number of low impedance external terminals is realized by implementing first external terminals that are adapted to input/output high frequency signals of various channels, a second external terminal that has a higher impedance than the first external terminals and is implemented between two of the first external terminals, and a capacitor of which one end is connected to the second external terminal and the other end is arranged to have a predetermined electrical potential.

Abstract: A semiconductor memory device includes a core block having sub-arrays and sense amplifier regions. First and second charge storing regions are disposed at sides of the core block. First and second decoupling capacitors are formed at the first and second charge storing regions, respectively. A plurality of first voltage supply lines are disposed to supply a power supply voltage to the sense amplifier regions and are connected to one electrode of each of the first and second decoupling capacitors. A plurality of second voltage supply lines are disposed to supply a ground voltage to the sense amplifier regions and are connected to the other electrode of each of the first and second decoupling capacitors.

Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.

Abstract: A sensor for a magnetic random-access memory (MRAM) of an embodiment of the invention includes an amplifier having at least two inputs and at least two outputs. The inputs are coupled to a magnetic storage element of the MRAM having a resistance corresponding to a value stored thereby and the outputs provide an output voltage corresponding to the resistance of the magnetic storage element. The sensor comprises a chopper switch coupled between one input of the amplifier and the magnetic storage element, a chopper switch coupled between another input of the amplifier and the magnetic storage element, and a chopper switch coupled between the outputs of the amplifier.

Abstract: A dynamic CAM cell has features that reduce the effect of noise within a CAM array. By shielding the matchline from the wordline, noise transmitted from the matchline to the wordline is reduced. By placing the searchline equally distant from a bitline and the bitline complement, the noise transmitted by the searchline is received equivalently by both the bitline and the bitline complement and therefore cancelled out.

Abstract: Techniques for replacing and eliminating paths causing channel leakage current. In one embodiment, one or more precharge enable transistors and a precharge enable signal are added to a circuit configuration. The precharge enable transistors are designed to remain on and simply pass a signal in a properly functioning path. When a leakage path is identified, such as during IDDQ testing, the precharge enable signal is set to turn off the precharge enable transistors. When the precharge enable transistors are off, the leakage path is disrupted, and the leakage current stopped. The path may be replaced with a redundant path.

Abstract: A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells, on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring using the common electrodes.

Abstract: A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

Abstract: Apparatus and method for a current limiting bleeder device that is shared between columns of different memory arrays and limits a current load on a voltage supply to prevent failure of an otherwise repairable memory device. The memory device includes first and second memory arrays having memory cells arranged in rows and columns where each of the columns of the first and second memory arrays have a equilibration circuit to precharge the respective column. A bleeder device is coupled to a precharge voltage supply and further coupled to at least one equilibration circuit of a column in the first memory array and to at least one equilibration circuit of a column in the second memory array to limit the current drawn by the equilibration circuits from the precharge voltage supply.

Abstract: The present invention provides a semiconductor memory device capable of being stably operated by reducing power noise generated while a sense amplifier performing for sensing and amplifying data supplied to a bit line. For this object, an inventive semiconductor memory device includes a cell array having a plurality of cells; a plurality of bit lines supplied with voltage stored in the plurality of the cells; a plurality of sense amplifier block for sensing and amplifying a voltage of the plurality of the bit lines, each bit line being connected to each cell; a plurality of switches for selectively connecting or disconnecting the plurality of the sense amplifier block to the plurality of the bit lines; and a sense amplifier control block for turning on the plurality of the switches by using at least two different timing sets.

Abstract: A method of reading a selected resistive memory bit having its output connected to a bitline, which is connected to a plurality of unselected electrically parallel resistive memory bits, is provided. The method comprises selecting the resistive memory bit to be read by applying a read voltage to an input of the resistive memory bit, and unselecting the plurality of unselected resistive memory bits by applying a deselect voltage to all inputs of the unselected resistive memory bits. The current out of the bitline is then sensed by a current sensor. A memory device is also provided comprising a plurality of resistive memory bits connected to a shared bitline, a means for selecting a single bit from the plurality of resistive memory bits, a means for deselecting the remaining, unselected bits from the plurality of resistive memory bits and a means for sensing the output current from the bitline.

Abstract: A main power supply line and a main ground wiring provided to supply power from one side (a first direction) of a memory region, a main power supply line and a main ground wiring provided to supply the power from the other side (a second direction opposite to the first direction) of the memory region are provided in a column direction. A bit line driver arranged on one side is supplied with power from one side, and a bit line driver arranged on the other side is supplied with the power from the other side. As a result, no current path is formed in a region of the power supply lines on the selected memory region.

Abstract: Disclosed is a method and structure that controls an output driver by generating an output data path clock signal from a system clock signal and timing the programmable impedance of the output driver according to the output data path clock signal. The method/structure controls the timing of the line driver circuits according to the output data path clock signal. By timing the programmable impedance according to the output data path clock signal, the timing of delivery of an impedance control signal is coordinated with the timing of delivery of data. The method/structure also performs impedance updates on the output driver more frequently during initialization cycles than in cycles that occur after the initialization cycles expire using at least two differently timed clock dividers and a counter.

Abstract: A plurality of decoding circuits 1a to 1f are arranged near a plurality of circuit blocks 2 to 7, which are arranged on the semiconductor chip 10 in a scattered manner, and the signal lines 8 prior to decoding, including the address lines and the data lines, are wired to each decoding circuit 1a to 1f. Through these wirings, the number of wirings routed over on the semiconductor chip 10 can be made in accordance with the number of bits of the signal lines 8 alone. So, compared with the past where the signal lines 20, which were great in number after decoding, were routed over to each circuit block 2 to 7, the wiring area as a whole can be greatly reduced. This can lead to miniaturization of chip size, reduction of crosstalk noise, and facilitation of layout.

Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross-point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract: A memory device including a circuit for actively driving a reference voltage in a memory device is disclosed. A circuit integrated in a memory device and coupled to an external voltage source substantially eliminates fluctuations in the reference voltage of the memory device caused by power supply changes and noise occurring in the memory device by generating a constant voltage and good current drive from the external voltage source.

Abstract: A semiconductor memory device is of a bank switching type having a plurality of memory array banks provided in a memory chip which can be switched from one to another for storage operation. The semiconductor memory device includes: a plurality of memory arrays in the memory array banks; an input/output circuit for transmitting information data between the memory arrays and the outside; a data bus for connecting between the memory arrays and the input/output circuit; and N-channel transistors provided across the data bus. The data bus consists of a plurality of adjacent lines. Each of N-channel transistors is connected at their drain to the corresponding lines of the data bus while at their source to the ground. When a multi-bit test is commenced for writing and reading data on the memory arrays, the N-channel transistors are turned on to connect the lines of the data bus to the ground.

Abstract: A static random access memory (SRAM) is provided that includes a logic circuit coupled to a column select signal line and a leakage reduction circuit coupled to the logic circuit and a bit line pair of a column. The logic circuit may control the leakage reduction circuit so as to reduce leakage through a column select device that is not selected.

Abstract: In a preferred embodiment, the invention provides a circuit and method for improving the soft error rate in a dual-port read SRAM cell. A write-only transfer device is connected to a cross-coupled latch, a first wordline, and a first bitline. A first read-only transfer device is connected to a second bitline, a second wordline, and a first pull-down device. A second read-only transfer device is connected to the first bitline, the first wordline, and a second pull-down device. A clear memory transfer device is connected to the cross-coupled latch, a third bitline, and a third pull-down device. This configuration allows a reduction in the size of a dual-port SRAM cell with little or no reduction in the read access time of the cell. The reduction in size also reduces SER by reducing the cross-sectional, p/n junction area exposed to radiation.

Abstract: The present invention provides a semiconductor apparatus including an internal clock generating unit and a data storing unit. The internal clock generating unit generates an internal clock signal based on an external clock signal and a clock control signal. The data storing unit which operates data processing based on the internal clock signal. The internal clock generating unit carries out synchronous control such that the internal clock signal is synchronized with the external clock signal. The data storing unit generates the clock control signal based on the data processing and outputs the clock control signal to the internal clock generating unit to control the synchronous control. The data storing unit may controls the internal clock generating unit such that the synchronous control is adjourned or restrained temporarily while the data processing is a data reading process.

Abstract: Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.

Abstract: A sensing system for a memory cell in a memory array includes a current integrator circuit configured to integrate a read current through the memory cell and a reference current through a reference memory cell. The integration process creates a set of differential measurement voltages that can be used to determine the state of the memory cell. By integrating the read current to obtain a measurement voltage, rather than directly comparing the read current to a reference current, the sensing system can use lower supply voltages than conventional sensing systems. In addition, because the measurement voltages are generated by integrating the read current over time, sensing operations are less sensitive to supply voltage fluctuations and the accuracy. Also, for memory cells that exhibit small read currents, the accuracy of sensing operations can be increased by increasing the period of integration.

Abstract: High performance memory devices have been realized by applying an Evenly Scaled Multiple Level Architecture (ESMLA) using block select arrangement. A single-bit-line-write mechanism allows us to reduce the number of bit lines by 50% for static memory devices. The resulting memory device can be as fast as registers files while its area is smaller than prior art high-density memory devices. The scaling method of the memory architecture also assures that the speed of the memory devices will scale in the same rate as logic circuits in future IC manufacture technologies.

Abstract: In one form of the invention, a radiation resistant latch has an overall output node, and first, second and third sublatches. The sublatches each have input circuitry, an output node coupled to the sublatch's input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and responsively generate binary-state output signals on their respective output nodes. The first and second sublatches are coupled to the third sublatch and the third sublatch has its output signal coupled to the overall output node such that if any one of the three sublatches is subjected to a radiation induced erroneous change of state, the output signals of the other two sublatches reduce an effect of the third sublatch feedback circuitry on an overall output signal for the latch.

Abstract: As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit lines grids. Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by “vertical transistors” in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.

Abstract: A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.

Abstract: A semiconductor memory device includes: a pair of bit lines; a first sense amplifier coupled to the pair of bit lines; and a first controller, which controls the first sense amplifier. The first sense amplifier comprises a flip-flop circuit having a pair of NMOS transistors and a pair of PMOS transistors; a first transistor connected to a source terminal of the NMOS transistors in the flip-flop circuit; and a second transistor connected to a source terminal of the PMOS transistors in the flip-flop circuit. The first controller comprises a first NOR circuit, comprising input terminals to which a write command signal and a sense amplifier driving signal are supplied and an output terminal connected to a gate of the first transistor.