Abstract: According to one embodiment, a nonvolatile semiconductor storage device having a plurality of operation modes, includes: a plurality of first lines; a plurality of second lines; a plurality of memory cells; a first selection unit that charges the first line to a first selection voltage; and a second selection unit that charges a second line to an unselection voltage and discharges the second line to a second selection voltage after the first line is charged to the first selection voltage by the first selection unit, wherein the second selection unit adjusts at least one of a level of the second selection voltage to which the second line to be selected is to be discharged and a time constant when discharging the second line to be selected, in accordance with an operation mode in which the nonvolatile semiconductor storage device operates among the plurality of operation modes.

Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

Abstract: A method for data storage includes storing multiple sets each including one or more read thresholds for use in reading data from a plurality of analog memory cells. The memory cells are arranged in multiple erasure blocks each including multiple pages, and each set of read thresholds is associated with a respective page in one of the erasure blocks. A first page, which belongs to a given erasure block and is not associated with any of the stored sets of read thresholds, is read by retrieving a stored set of read thresholds that is associated with a second page in the given erasure block, adapting the retrieved set of read thresholds to match the first page, and reading the first page using the adapted set of read thresholds.

Abstract: Disclosed is a resistance variable memory device including a memory cell connected with a bit line, a sense amplifier circuit sensing a voltage level on the bit line, and a pseudo-replica providing the sense amplifier circuit with a control signal that compensates for a drop in the sensing capacity of the sense amplifier circuit in relation to process, voltage and temperature (PVT) variations.

Abstract: A system LSI (100) having a logic circuit (104) and a plurality of SRAM macros (103) includes a power supply circuit (102) configured to receive a voltage (VDDP) supplied from the outside of the system LSI (100), and to generate a stabilized voltage (VDDM) lower than the voltage (VDDP). An SRAM memory cell (103a) of each of the plurality of SRAM macros (103) is supplied with the voltage (VDDM) generated by the power supply circuit (102), and an SRAM logic circuit (103b) of each of the plurality of SRAM macros (103) is supplied with a voltage (VDD) supplied from the outside. In addition, the logic circuit (104) is supplied with the voltage (VDD) from the outside.

Abstract: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump.

Abstract: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump.

Abstract: A semiconductor memory apparatus includes an internal circuit configured to be driven by current flowing between first and second voltage nodes, and a current control unit configured to control an amount of the current in response to an operational-speed information signal.

Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

Abstract: A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

Abstract: Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second pair of switches are adapted to couple the gates of the transistors to a voltage supply. The first and second pair of switches are coupled to respective gates of the transistors independent of the pair of transistors being respectively coupled to the digit line nodes.

Abstract: A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD?(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.

Abstract: A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.

Abstract: A semiconductor integrated circuit device includes a data circuit and a group of bit line application voltage terminals to which different voltages are applied. The data circuit holds program data to be programed into a memory cell and changes the data held according to a verify result from the memory cell. Then, the data circuit selects one of the bit line application voltage terminals based on the data held therein and applies voltage of the selected bit line application voltage terminal to a bit line BLe or BLo.

Abstract: An apparatus, system, and method are disclosed for detecting the formation of a short between a magnetoresistive (“MR”) head and a head substrate. The apparatus is presented with a logic unit containing a plurality of modules configured to functionally execute the necessary steps of generating a baseline electric potential level between a head substrate and ground, monitoring the level of the electric potential between the head substrate and ground, and detecting the formation of a short circuit between the MR head and the head substrate by detecting a change in the electric potential level monitored by the monitoring module from the baseline level to a predetermined threshold level. Beneficially, such an apparatus, system, and method would reduce read errors on the magnetic tape storage system, the time and resources required to recover from such errors, and allow for preventative measures to obviate contamination short related failures of tape drive systems.

Abstract: A system for operating a memory device includes a memory array having a number of memory cells and a set of dynamic reference cells coupled to the memory cells in word lines. Each of the dynamic reference provides the associated memory cells with a dynamic reference value for determining a status of at least one of the associated memory cells. The dynamic reference value is capable of reflecting a variation in a threshold value of at least one of the associated memory cells.

Abstract: A semiconductor device includes a first reference cell used for programming or reading non-volatile memory cells, and an adjustment circuit adjusting a first reference level of the first reference cell when the first reference level is changed.

Abstract: A reference voltage supplying circuit can include an internal reference voltage generating unit configured to generate an internal reference voltage, a pad configured to receive an external reference voltage, a switching unit selectively configured to supply the internal reference voltage or the external reference voltage to an internal voltage generator in a test mode.

Abstract: Disclosed herein is a semiconductor memory device including a plurality of memory cells including first and second inverters each having first and second driver transistors and first and second load transistors and including first and second memory node, and first and second transfer transistors. The of the first and second transfer transistors is connected to each of the first and memory nodes respectively. The memory cell is connected to a bit line and complementary bit line via the first and second transfer transistors respectively wherein a supply voltage applied to the bit line and the complementary bit line is lower than a supply voltage applied to the load transistors, and at least a memory-node-side end of a gate insulating film of the first driver transistor, second driver transistor, first load transistor, and the second load transistor have a thickness larger than a thickness of a gate insulating film of the other part.

Abstract: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump.

Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

Abstract: A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level generator circuit generates 2n?1 voltage levels from the reference voltage. A comparator circuit, such as an analog-to-digital circuit, compares the voltage from the temperature sensor to the 2n?1 voltage levels to determine which level is closest. An n-bit digital output of the resulting level is proportional to the temperature of the integrated circuit.

Abstract: A dummy memory cell for detection of write completion timing is provided as a replica of a memory cell. When assisting a write operation by power supply control and substrate potential control of the memory cell, the timing of ending the write assist operation is determined by a voltage control circuit based on information about the dummy memory cell. For example, the voltage control circuit performs, in a data write operation in the memory cell, the write assist operation of decreasing the voltage of a source power supply allocated to P-channel MOS load transistors using a pull-down transistor. Thereafter, at the time when completion of the data write operation in the dummy memory cell is detected, the voltage control circuit ends the write assist operation and restores the voltage of the source power supply to the original level using a pull-up transistor.

Abstract: In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared to a trip point, which is the threshold voltage of a voltage-sensing transistor. To account for temperature variations and manufacturing process variations, the voltage generator includes a transistor which is matched to the voltage-setting transistor, and a transistor which is matched to the voltage-sensing transistor. As a result, a voltage swing between the initial voltage and the trip point is constant, even as the initial voltage and trip point vary. In a particular implementation, the voltage generator uses a cascode current mirror circuit, and receives a reference current from a band gap voltage circuit.

Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.

Abstract: An electronic circuit includes multiple circuit elements arranged into multiple distinct subdivisions, each subdivision having a separate voltage supply connection for conveying power to the subdivision. The electronic circuit further includes a controller including multiple outputs, each of the outputs being connected to a corresponding one of the voltage supply connections. When a given one of the subdivisions does not include a weak circuit element, the controller supplies a first voltage level to the given subdivision via the corresponding voltage supply connection. When the given subdivision includes at least one weak circuit element, the controller is operative to supply at least a second voltage level to the given subdivision via the corresponding voltage supply connection, the second voltage level being greater than the first voltage level.

Abstract: In a method for supplying power supply voltages in a semiconductor memory device a first source voltage is applied to a memory cell of a memory cell array as a cell array internal voltage for operating a sense amplifier coupled to the memory cell. A second source voltage is applied as a word line drive voltage of the memory cell array. The second source voltage has a voltage level higher than a voltage level of the first source voltage. The second source voltage is also applied as a drive voltage of an input/output line driver to drive write data into an input/output line in a write operating mode.

Abstract: An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. The input can be used to determine whether to adjust a magnitude of the pre-charge voltage signal produced by the voltage generator. Adjusting the pre-charge voltage can result in power savings. That is, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.

Abstract: A nonvolatile memory device contains at least one nonvolatile memory module and an electrical buffer for buffering a supply voltage for the at least one nonvolatile memory module. A microprocessor may be connected in parallel or serial fashion to the memory device, or may contain the memory device.

Abstract: A semiconductor storage device precharging a bit line pair to a ground potential includes a sense amplifier connected between the bit line pair, a storage cell connected to one of the bit line pair and storing data, a first transistor controlling a conduction state between the other of the bit line pair and a reference cell node, a second transistor connected between a reference voltage source generating a reference voltage and the reference cell node, the second transistor exclusively controlled from the first transistor, and a capacitor setting a potential of the reference cell node.

Abstract: The present invention relates to a semiconductor memory device, and more precisely to a semiconductor memory device which controls the voltage supplied to a dummy bit line and a biasing method. The semiconductor memory device includes a dummy bit line disposed in a cell array and a switching unit which switches the supply of a bias voltage to the dummy bit line by a control signal related to an operation of the cell array.

Abstract: A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a reference cell each having a memory element that stores data based on change in resistance value. The read circuit includes: a voltage comparison unit that compares a value corresponding to a sense current from the selected cell with a value corresponding to a reference current from the reference cell; a first switch; and a second switch. Both of the first and second switches are provided at a subsequent stage of a decoder and at a preceding stage of the voltage comparison unit. The second switch circuit controls input of the value corresponding to the sense current to the voltage comparison unit, while the first switch circuit controls input of the value corresponding to the reference current to the voltage comparison unit.

Abstract: A semiconductor memory apparatus includes a sense amplifier that receives a driving voltage through a sense amplifier power supply input terminal and detects and amplifies a difference between signals that are supplied to two input lines, a sense amplifier voltage supply unit that supplies a driving voltage and an overdriving voltage higher than the driving voltage to the sense amplifier through the sense amplifier power supply input terminal using a power supply voltage, and a driving voltage control unit that maintains a driving voltage level of the sense amplifier power supply input terminal in response to the level of the power supply voltage, after a voltage of the sense amplifier power supply input terminal is elevated to a power supply level responding to the overdriving voltage in order to perform the overdriving operation.

Abstract: A dynamic type semiconductor memory device includes a sense amplifier connected with a bit line pair to amplify and sense a voltage difference on the bit line pair; a precharge circuit configured to precharge the bit line pair to a power supply voltage on a lower side in response to a first control signal; a memory cell capacitance having one end which is connected with the bit line pair through a first switch circuit which is controlled in response to a signal on a word line; and a reference cell capacitance having one end which is connected with the bit line pair through a second switch circuit which is controlled in response to a signal on a reference word line. The other end of the memory cell capacitance and the other end of the reference cell capacitance are electrically separated.

Abstract: Devices and systems for generating a bias current with a low minimum voltage, for example, are disclosed. One such device includes a first transistor having a source coupled to a voltage supply, a drain coupled to a first node, and a gate coupled to a second node, a second transistor having a source coupled to a reference, and a drain and a gate coupled to the first node, a third transistor having a source coupled to the reference, a drain coupled to a third node, and a gate coupled to the first node, a first resistive element coupled between the voltage supply and the third node, a second resistive element coupled between the voltage supply and the second node, and a fourth transistor having a source coupled to the reference, a drain coupled to the second node, and a gate coupled to the third node.

Abstract: A semiconductor device includes a DRAM cell configured to store a data; and a sense amplifier activated in response to supply of power supply voltages and configured to sense the data stored in the DRAM cell. A power supply circuit supplies the power supply voltages to the sense amplifier. A sense amplifier dummy circuit provides a replica of a state of the sense amplifier immediately after the activation of the sense amplifier; and a power supply control circuit controls the power supply circuit based on the replica such that the power supply voltages are varied with time.

Abstract: In one embodiment, a semiconductor memory device includes a plurality of pairs of bit lines, each of said pairs including a first bit line, a second bit line, a memory cell coupled to said first bit line, a sense amplifier determining the logical value stored in the memory cell according to a potential difference between the first and the second bit line, a reference voltage generation circuit, and a reference voltage supply switch coupling an output of the reference voltage generation circuit to the second bit line.

Abstract: A method for classifying memory cells in an integrated circuit is provided, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes determining, for each subset of the memory cells of a plurality of subsets of the memory cells, a threshold voltage distribution; determining whether the determined threshold voltage distributions fulfill a threshold voltage criterion; and depending on whether the determined threshold voltage distributions fulfill the threshold voltage criterion, classifying at least some of the non-selected memory cells.

Abstract: A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal.

Abstract: The present invention solves a problem of the degradation of the long-term reliability of a conventional semiconductor memory device due to early deterioration of a FET included in a reference cell therein. DRAM 1 has word lines 101 to 10n, word lines 22 and 24, memory cells 301 to 30n and a reference cell 40. Gates of FETs 32 in the memory cells 301 to 30n are connected to the word lines 101 to 10n respectively. Gates of a FET 42 and a FET 44 in the reference cell 40 are connected to the word line 22 for readout and the word line 24 for writing respectively. Here, potentials applied to the word lines 22 and 24 are lower than those applied to the word lines 101 to 10n.

Abstract: A voltage compensated sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second pair of switches are adapted to couple the gates of the transistors to a voltage supply. The first and second pair of switches are coupled to respective gates of the transistors independent of the pair of transistors being respectively coupled to the digit line nodes.

Abstract: A semiconductor device includes a first reference cell used for programming or reading non-volatile memory cells, and an adjustment circuit adjusting a first reference level of the first reference cell when the first reference level is changed.

Abstract: A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the square of the scale factor, while cell capacitance is reduced by the scale factor. The voltage used to supply the logic transistors is scaled down from the first process to the second process. However, the voltage used to supply the sense amplifiers remains constant in both processes. Thus, in an embedded DRAM array of the second process, sense amplifiers are supplied by a greater voltage than the logic transistors. This allows the sensing voltage of DRAM cells to be maintained from one process generation to another, while allowing memory size to scale with the square of the process scale factor.

Abstract: A circuit for determining the value of a datum stored in an array memory cell of a non-volatile memory device having at least one reference memory cell of known content. The circuit has a determination stage, which compares an array electrical quantity, correlated to a current flowing in the array memory cell, with a reference electrical quantity, and supplies an output signal indicative of the datum, based on the comparison; and a generator circuit, provided with an input receiving a target electrical quantity correlated to a current flowing in use in the reference memory cell, and an output, which supplies the reference electrical quantity with a controlled value close or equal to that of the target electrical quantity. The generator circuit is provided with a variable generator, and a control unit connected to, and designed to control, the variable generator so that it will generate the controlled value of the reference electrical quantity.

Abstract: In one embodiment, a DRAM is provided that includes: a word line intersecting with a pair of bit lines, the DRAM including a memory cell at each intersection, each memory cell including an access transistor adapted to couple a storage cell to the corresponding bit line if its gate voltage is raised; and a word line compensation circuit adapted to compensate for a capacitively-coupled voltage increase on the corresponding bit line if the access transistor's gate voltage is raised.

Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

Abstract: A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface is comprised of a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.