Abstract: An embodiment static random access memory (SRAM) array includes a writable SRAM cell disposed in a first row of the SRAM array and an SRAM read current tracking cell in the first row of the SRAM array. The SRAM current tracking cell includes a first read pull-down transistor and a first read pass-gate transistor. The first read pull-down transistor includes a first gate electrically connected to a first positive supply voltage line; a first source/drain electrically connected to a first ground line; and a second source/drain. The first read pass-gate transistor includes a third source/drain electrically connected to the second source/drain and a fourth source/drain electrically connected to a read tracking bit line (BL). The read tracking BL is electrically connected to a read sense amplifier timing control circuit.

Abstract: A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line.

Abstract: A memory device is provided. The memory device includes a first signal line, a memory cell array, first and second voltage adjustment circuits. The memory cell array is divided into first and second areas and includes first memory cells in the first area and second memory cells in the second area. The first and second memory cells are coupled the first signal line. Each of the first and second memory cells has a reference node. The first voltage adjustment circuit adjusts voltages at the reference nodes of the first memory cells. The second voltage adjustment circuit adjusts voltages at the reference nodes of the second memory cells. The reference nodes of the first memory cells are coupled to a ground through the first voltage adjustment circuit. The reference nodes of the second memory cells are coupled to the ground through the second voltage adjustment circuit.

Abstract: According to one embodiment, a magnetic memory element includes: a magnetic wire, a stress application unit, and a recording/reproducing unit. The magnetic wire includes a plurality of domain walls and a plurality of magnetic domains separated by the domain walls. The magnetic wire is a closed loop. The stress application unit is configured to cause the domain walls to circle around along the closed loop a plurality of times by applying stress to the magnetic wire. The recording/reproducing unit is configured to write memory information by changing magnetizations of the circling magnetic domains as the domain walls circle around and to read the written memory information by detecting the magnetizations of the circling magnetic domains.

Abstract: A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity.

Abstract: A gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in N memory cells is connected, which supplies the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in M reference cells is connected, which supplies second gate voltage at the erase verify time to a first non-selected word line connected to a memory cell array, and which supplies third gate voltage at the erase verify time to a second non-selected word line connected to a reference cell array is included. An electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current which flows through a memory cell connected to the first non-selected word line.

Abstract: A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.

Abstract: A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.

Abstract: A memory device includes a memory array comprising a including of memory cells, and control circuitry coupled to the memory array. The control circuitry includes write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel combination of additional memory cells may comprise a mini-array that includes centrally-located active memory cells surrounded by dummy memory cells. In an arrangement in which the write signal generation circuitry includes a clock latch, the parallel combination of additional memory cells may be coupled between a clock output of the clock latch and a reset input of the clock latch.

Abstract: Systems and methods of testing a reference cell in a memory array are disclosed. In a particular embodiment, a method includes coupling a first reference cell of a first reference cell pair of a memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array.

Abstract: A sense amplifier system includes a first path, a second path, a memory cell, a first reference cell, a second reference cell, and a switch component. The switch component is configured to switch connections between the first and second reference cells and the first and second paths according to a sampling phase and an amplification phase.

Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.

Abstract: A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.

Abstract: A semiconductor device comprises a circuit cell and a basic end cell. The circuit cell includes a plurality of elements aligned in a first direction, and the basic end cell is arranged adjacent to the circuit cell in the first direction and has a compensation capacitor capable of being connected to a supply voltage of the circuit cell. In the semiconductor device, a diffusion layer forming the compensation capacitor extends along the first direction in a predetermined region of the circuit cell.

Abstract: Resistance memory cells of MRAM arrays are designated as reference cells and programmed to binary 0 and binary 1 states, reference cells from one MRAM array at binary 0 and at binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of another MRAM array, reference cells from the other MRAM array at binary 0 and binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of the one MRAM array.

Abstract: A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a first value indicative of a resistance between the first node and the second node, and setting the reference level based at least in part on the measured value. Also an associated reference circuit.

Abstract: The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.

Abstract: Systems and methods of testing a reference cell in a memory array are disclosed. In a particular embodiment, a method of testing a reference cell in a memory array includes coupling a first reference cell of a first reference cell pair of the memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array.

Abstract: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.

Abstract: The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has : a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has : replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.

Abstract: Memory circuit and a tracking circuit thereof. The tracking circuit includes a dummy bit line (DBL). The tracking circuit further includes a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal. The wordline activation signal causes activation of a memory cell. The tracking circuit also includes a second circuit which is responsive to discharge of the dummy bit line to enable access to the memory cell.

Abstract: A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor.

Abstract: A magnetic random access memory (MRAM) includes a memory cell having a first transistor and a first magnetic tunneling junction (MTJ) layer, and a reference cell operable as a basis when reading data stored in the memory cell, the reference cell including second and third MTJ layers arranged in parallel to each other, and a second transistor connected in series to each of the second and third MTJ layers, the second transistor having a driving capability corresponding to twice a driving capability of the first transistor of the memory cell.

Abstract: A method of sensing a data value stored at a resistance based memory is disclosed. The method includes receiving a data signal from a data cell. The data cell includes a resistance based memory element. A reference signal is received from a reference circuit. The reference circuit includes a resistance based memory element. The data signal is converted to a data output signal having a first frequency. The reference signal is converted to a reference output signal having a second frequency. A first output signal is generated when the first frequency exceeds the second frequency. A second output signal is generated when the second frequency exceeds the first frequency.

Abstract: A nonvolatile memory device includes one or more reference cell transistors, one or more memory cell transistors, and a current source circuit including three or more field effect transistors that have gates thereof connected together, the three or more field effect transistors including two or more field effect transistors and another field effect transistor, currents flowing through the two or more field effect transistors being combined to flow through the one or more reference cell transistors, and another field effect transistor having a drain thereof connected to one of the one or more memory cell transistors.

Abstract: A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.

Abstract: The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.

Abstract: A regular capacitor is saturated by an electric charge of a regular memory cell holding a high logic level and is not saturated by an electric charge from the regular memory cell holding a low logic level. A reference capacitor is saturated by the electric charge from a reference memory cell holding the high logic level. A differential sense amplifier differentially amplifies a difference between a regular read voltage read from the regular capacitor and a voltage which is lower by a first voltage than a reference read voltage being a saturation voltage read from the reference capacitor, and generates logic of data held in the memory cell. Accordingly, a difference between the reference voltage and the read voltage corresponding to the low logic level can be made relatively large. As a result, it is possible to improve a read margin.

Abstract: Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed.

Abstract: First and second memory cell arrays are adjacent in a first direction. First and second areas are positioned adjacent to one and the other side of the first memory array in a second direction. Third and fourth areas are positioned adjacent to one and the other side of the second memory array in a second direction. A sense amplifier is arranged in the first area and a current sink is arranged in the fourth area. The sense amplifier compares a read current which flows into the current sink via a memory cell in the first memory cell array and the second area from the sense amplifier with a reference current which flows into the current sink via the third area and a reference memory cell in the second memory cell array from the sense amplifier.

Abstract: A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.

Abstract: A fuse element reading circuit including a first fuse element having a resistance which differs in accordance with whether the first fuse element is in a blown state or an unblown state, a reference voltage output circuit unit that outputs a reference voltage that differs in accordance with a normal mode or a test mode, and a voltage comparison circuit unit that compares a read voltage corresponding to the resistance of the first fuse element with the reference voltage output from the reference voltage output circuit unit.

Abstract: A semiconductor memory device includes a plurality of memory cells configured to correspond to each of a plurality of word lines for storing data; a plurality of reference memory cells configured to include first and second magnetic memory devices, whose lower electrodes are commonly connected to each other, to generate a reference current corresponding to each of the memory cells; and a sense amplification unit configured to sense and amplify the reference current and a data current corresponding to a memory cell connected to an activated word line among the word lines.

Abstract: A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line.

Abstract: A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.

Abstract: An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential.

Abstract: Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed.

Abstract: Techniques and corresponding circuitry for deriving a supply a bias voltage for a memory cell array from a received reference voltage is presented. The circuit includes a voltage determination circuit, which is connected to receive the reference voltage and generate from it the bias voltage, a temperature sensing circuit, and a calibration circuit. The calibration circuit is connected to receive the bias voltage and to receive a temperature indication from the temperature sensing circuit and determine from the bias voltage and temperature indication a compensation factor that is supplied to the voltage determination circuit, which adjusts the bias voltage based upon the compensation factor.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for generating a reference voltage for a resistive sense memory (RSM) cell, such as an STRAM cell. A dummy reference cell used to generate a reference voltage to sense a resistive state of an adjacent RSM cell. The dummy reference cell comprises a switching device, a resistive sense element (RSE) programmed to a selected resistive state, and a dummy resistor coupled to the RSE. A magnitude of the reference voltage is set in relation to the selected resistive state of the RSE and the resistance of the dummy resistor.

Abstract: A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

Abstract: A magnetic random access memory according to an example of the invention comprises a first reference bit line shared by first reference cells, a second reference bit line shared by second reference cells, a first driver-sinker to feed a first writing current, a second driver-sinker to feed a second writing current, and a control circuit which checks data stored in the first and second reference cells line by line, and executes writing simultaneously to all of the first and second reference cells by a uniaxial writing when the data is broken.

Abstract: Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include programming to a target threshold voltage within a range representative of the desired bit pattern. Reading such memory devices can include generating an analog data signal indicative of a threshold voltage of a target memory cell. The target memory cell can be sensed against a reference cell includes a dummy string of memory cells connected to a target string of memory cells, and, such as by using a differential amplifier to sense a difference between a reference cell and the target cell. This may allow a wider range of voltages to be used for data states.

Abstract: A random access memory microelectronic device, comprising a plurality of cells comprising respectively: a plurality of transistors forming a bistable, a first storage node and a second storage node, a first double gate access transistor to the first storage node and a second double gate access transistor to the second storage node, a first gate of the first access transistor and a first gate of the second access transistor being linked to a first word line, a second gate of the first access transistor and a second gate of the second access transistor being linked to a second word line, the device being moreover equipped: with a reference memory cell provided to deliver a bias potential intended to be applied to one of the respective word lines of one or several given cells of said plurality of cells during reading access of said given cells.

Abstract: A memory cell array includes reference cells each associated with a plurality of data cells of the array.

Abstract: A non-volatile static random access memory (“SRAM”) cell using variable resistance random access memory (“RAM”) cells is described. A memory tri-cell includes an SRAM cell with a first charge node and a second charge node. A first variable resistance random access memory cell is coupled between the first charge node and a supply voltage bus. A second variable resistance random access memory cell is coupled between the first charge node and a ground bus. A first control gate is coupled between the supply voltage bus and the first variable resistance random access memory cell. A second control gate is coupled between the ground bus and the second variable resistance random access memory cell.

Abstract: Whenever N data bits are stored in a cell of a memory that programs each of its cells to represent any one of 2N different patterns of N>1 bits as a respective one of 2N ordered cell states, the N data bits are mapped to a transformed pattern of N bits according to a transformation that maps the pattern of the lowest state (typically all 1's) to a different pattern, and the cell is programmed to represent the transformed pattern. The transformation may invert all, some or only one of the bits of each pattern. Whenever the cells of the memory are read, the transformation is inverted.

Abstract: To fully evaluate a real signal line and a real memory cell adjacent to a dummy signal line and utilize dummy signal line as real signal line, a semiconductor memory includes at least one real signal line connected to real memory cells driven by a real driver and at least one dummy signal line outside the real signal line connected to dummy memory cells, driven by a dummy driver. Real driver and dummy driver drive the real signal line and the dummy signal line synchronous with a common timing signal generated by an operation control circuit. Consequently, a stress evaluation is also performable, e.g., on a real signal line outside of a memory cell array under the same condition of a real signal line on the inner side. Dummy signal line is driven using common timing signal and evaluated, thus being usable as a redundancy signal line to relieve failure.

Abstract: Embodiments of the invention relate generally to a method for writing at least one memory cell of an integrated circuit; a method for writing at least two memory cells of an integrated circuit; and to integrated circuits. In an embodiment of the invention, a method for writing at least one memory cell of an integrated circuit is provided. The method includes determining a writing state of at least one reference memory cell, depending on the writing state of the at least one reference memory cell, writing the at least one memory cell, and writing the at least one reference memory cell to a given writing state.

Abstract: An embodiment of the invention relate to a memory device including a memory plane composed of memory cells located at the intersection of lines and columns, and a dummy path designed to output a signal to activate read amplifiers arranged at the bottom of the columns in the memory plane, said dummy path including dummy memory cells connected between two dummy bit lines means of selecting at least one dummy cell designed to discharge at least one of the dummy bit lines, and control means connected to the two dummy bit lines to generate said activation signal, characterized in that said device includes means of programming the number of selected cells to discharge at least said dummy bit line, to adjust the time at which said activation signal is output.

Abstract: A reference voltage supply apparatus and a driving method thereof in a ferroelectric memory device provide a reference voltage stabilized against the imprint effect thus maintaining reading reliability of the device. In the reference voltage supply apparatus (e.g., using a non-switching capacitance of a ferroelectric capacitor), a reference cell is constructed of a ferroelectric capacitor and an access switch, and provides a reference voltage to read data from a memory cell. In an active mode, the reference cell stores data of a first logic state (e.g., corresponding to the non-switching capacitance of the ferroelectric capacitor), in the reference cell, and then supplies, as a reference voltage, the voltage corresponding to the data of the first logic state to a bit line; and in a stand-by mode, a reference voltage controller stores (writes) data of a second logic state (opposite to the first logic state), into the reference cell.