Abstract: A negative voltage level translator includes an output terminal which is electrically connected to a word line of the associated memory array. The voltage level of the output terminal, and thus the voltage level of the associated word line, is controlled by a cross-coupled latch. If the word line associated with the negative voltage level translator has been selected during erasing, the cross-coupled latch enters a first state which results in the output terminal being pulled to a negative erase voltage. This negative erase voltage, which may be generated by a negative charge pump, is in this manner coupled to the control gates of the array's selected memory cells to cause the erasing of such memory cells via, for instance, electron tunneling. If the word line associated with the output terminal has not been selected for erasing, the cross-coupled latch enters a second state which results in the output terminal being maintained at a floating potential.

Abstract: A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.

Abstract: In a nonvolatile memory device, a write operation is performed upon used memory cells. Then, an erase operation is performed upon the used memory cells as well as unused memory cells. Finally, a write operation is performed upon only the unused memory cells.

Abstract: A translator (300) for generating a tool (315) for a modifying data on a chip card (10) or for a communicating with the chip card (10) is proposed, the translator (300) receiving as input data a description (310) in a card definition language provided for that purpose, said description (310) comprising information about objects on the chip card (10) which are described with the use of constructional instructions. The translator (300) comprises a means for generating an internal list of attributes (320) from the information about the objects in the description (310), there existing for each object at least one entry (330) in the internal list of attributes (320).

Abstract: A non-volatile data storage unit having a data input and a volatile memory device for storing data. The volatile memory device is preferably a latch circuit made up of a pair of cross-coupled inverter circuits which store the data in complementary form. A non-volatile memory device, such as a pair of flash memory cells, is included which also store data in complementary form. Control circuitry is provided for controlling the operation of the data storage unit, including circuitry for transferring data from the data input to the volatile memory device and circuitry for programming the non-volatile memory device with data from the volatile memory device. The storage unit also preferably includes circuitry for transferring data stored in the non-volatile memory device to the volatile memory device, with such transfer typically taking place after an interruption of power to the storage unit.

Abstract: The invention enables random read and write operations into cells in an array that contains connections from the memory cells that include at least one field effect transistor (FET transistor) to embedded bit line segments which are selectively isolatable and selectively expandable to achieve compactness of number of cell per unit area.In a given segment of the array a first select transistor is connected between a given embedded bit line segment and a first access bit line which functions as a path from a first reference voltage to the drain of a first FET memory transistor set when the first select transistor is turned off, and wherein the first access bit line functions as a path from the source of a second FET memory transistor set to a second reference voltage when the first select transistor is turned on.

Abstract: A non-volatile semiconductor memory device is provided in which a variation of threshold voltages of non-written memory cells and a potential variation of a selected bit line in preventing generation of drain disturb phenomenon are minimized Source lines SL.sub.1 ', SL.sub.2 ', SL.sub.3 ' and SL.sub.4 ' are provided in parallel to word lines WL.sub.1, WL.sub.2, WL.sub.3 and WL.sub.4, respectively, and selectively. When a data is to be written in a memory cell C.sub.11, a potential of a selected word line WL.sub.1 is set to a high voltage V.sub.pp, potentials of non-selected word lines WL.sub.2, WL.sub.3 and WL.sub.4 are set to the drain disturb preventing voltage, for example, an intermediate voltage V.sub.pp /2 which is a half of the high voltage. Further, a potential of a selected bit line BL.sub.1 is set to a potential V.sub.dd which is lower than the high voltage V.sub.pp, non-selected bit lines BL.sub.2, BL.sub.3 and BL.sub.4 are made open. Further, a potential of a selected source line SL.sub.

Abstract: A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cell

Abstract: A pulse generator circuit. The pulse generator circuit includes a first oscillator and a second oscillator coupled to the output of the first oscillator. The first oscillator is for outputting a first signal having a first frequency, and the second oscillator for outputting a second signal having a second frequency that is greater than the first frequency. The second signal is fed back to the second oscillator for controlling the operation of the second oscillator. The second oscillator is enabled to output the second signal in response to a rising edge of the first signal and disabled from outputting the second signal in response to a second edge of the second signal. To reduce power consumption of the pulse generator circuit, each of the oscillator circuits may be a ring oscillator comprising a plurality of inverters coupled in series and a feedback conductor coupled to the output of a last inverter and the input of a first inverter.

Abstract: A current mirror circuit for fast programming of semiconductor memory cells and for ease of testing and verifying the condition of the memory chips. The current mirror includes a reference branch and multiple output branches. At least one output branch connects to a programmable memory cell through FET transistors and the programming current flows from the output branch to the memory cell to supply it with the programming current. When the programming of the memory cells is accomplished the drain current of the memory cell is reduced to be below that of the current of the reference branch of the current mirror. Because the memory cell is connected in series with the output branch of the current mirror, the current of the output branch is also reduced to be below the current of the reference branch.

Abstract: The failure rate of semiconductor devices containing UPROM transistors is improved by erasing the UPROM transistors using X-rays. The semiconductor devices are subsequently exposed to UV radiation to erase other transistors charged during X-ray exposure.

Abstract: The non-volatile semiconductor memory disclosed includes an X-decoder and word line potential supply circuits, and a current setting/holding circuit. The X-decoder and the word line potential supply circuits set all word lines ground potential in the flash erasing operation, to a predetermined first over-erasing judgment reference potential in an "on" cell detecting operation, and to a predetermined second over-erasing judgment reference potential for judgment of over-erasing deeper than the first over-erasing judgment reference potential and, in an "on" cell specifying operation, set predetermined selected word lines to the first over-erasing judgment reference potential while setting other word lines than the selected word line to the second over-erasing judgment reference potential. The current setting/holding circuit sets the reference current in an "on" cell specifying reference current setting operation such that the result of the check by a sense amplifier is "on".

Abstract: A semiconductor data storage apparatus having a plurality of memory devices which are switched to a predetermined mode when a software command has been written, which have waiting time during execution of the command after the command has been written and from which data can be collectively erased, the semiconductor data storage apparatus being arranged to shorten the time required to erase data. A memory device is activated in response to a memory selection signal supplied by a decoder, a write enable signal, which has been, by an AND gate circuit, selectively supplied in response to the selection signal, brings the memory device into a write mode, upper address signals are sequentially switched during waiting time during execution of erasure after an erase command has been written so as to sequentially write erase commands on next memory devices by the decoder and AND gate circuits.

Abstract: A method of erasing memory cells in a sector of a flash programmable memory device, the sector having a plurality of word lines and a plurality of memory cells along each of the word lines, each of the cells in the sector having a source region common to all cells in the sector, the method comprising a first step of erasing the memory cells in the sector simultaneously, then reading a first cell along a first word line to determine if the first cell is under-erased. Responsive to the first cell being erased, a second cell along the first word line is read to determine if the second cell is under-erased. Responsive to the second cell being under-erased, a negative first voltage is applied to the first word line, a positive second voltage is applied to the common source of the cells in the sector, and a positive third voltage is applied to the plurality of word lines except the first word line.

Abstract: A memory chip and method for operating a memory chip, in which one or more nodes are monitored to identify an illegal condition, and a halt signal is asserted in response to the illegal condition. If an illegal condition is identified during a high voltage mode in which high voltage is applied across transistors of the chip, assertion of the halt signal is delayed until the end of the high voltage mode. In response to the halt signal, the chip halts an operation such as a memory cell erase operation. By avoiding halt signal assertion during a high voltage mode, the invention avoids problems (e.g., due to the snap back bipolar effect) which could otherwise result due to switching of transistors of the chip during the process of halting chip operation in the high voltage mode.

Abstract: Addresses for a plurality of consecutive logic blocks are managed by assigning the addresses to their corresponding addresses for physical blocks of a plurality of flash memory devices such that the addresses for the plurality of continuous logic blocks are respectively distributed into the plurality of flash memory devices. When block erase commands are inputted from the outside, chip enable signals are respectively transmitted to at least two of the flash memory devices in which physical blocks to be erased exist, in such a manner that a period in which at least two flash memory devices simultaneously perform block erase operations, exists.

Abstract: An apparatus and method, the apparatus including an NMOS pass gate separating NMOS and PMOS transistors of a CMOS memory cell configured for tunneling during program and erase through the NMOS and PMOS transistors. The additional NMOS pass gate enables the CMOS memory cell to be utilized as a memory cell in a programmable logic device (PLD). The method includes steps for programming and erasing CMOS memory cells to prevent current leakage. The steps include applying specific voltages to the sources of the NMOS and PMOS transistors during program and erase, rather than leaving either source floating. Such voltages can be applied during program or erase without additional pass gates being connected to the sources of the PMOS or NMOS transistors of individual CMOS cells, or the additional pass gate provided between the drains of the PMOS and NMOS as in the described apparatus.

Abstract: An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns.

Abstract: A flexible word-erase flash memory includes a first bank of flash transistors forming a plurality of rows and a plurality of columns, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the first bank are all coupled to a first sourceline. A second bank of flash transistors form a plurality of rows and a plurality of columns, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the second bank are all coupled to a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline.

Abstract: An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.

Abstract: A method for testing nonvolatile memory device includes the steps of forming a block including a test row and a first and a second decoding row, by connecting the sources of the memory cells in the test row together to form a common source line, connecting each column of memory cells in the three rows in series, connecting the drains of the memory cells in the second decoding row together to form a common drain line, erasing the memory cells in the first and second decoding rows, successively programming and erasing the memory cells in the test row, and measuring a first drain current flowing through the common drain line with respect to the voltage of the word line of the test row. If the first drain current exhibits a negative threshold voltage, an over-erased memory cell exists in the test row.

Abstract: A method of erasing a sector for a flash memory device, the sector having a plurality of word lines with each word line having a plurality of memory cells therealong, each cell having a source region, comprises various steps. First, all of the memory cells in the sector are programmed. The memory cells are then simultaneously erased by applying a first voltage to the sources and a second voltage to the word lines. Subsequently, a first cell along a first word line is read to determine if the first cell is under-erased. Responsive to the first cell being under-erased, the first voltage is applied to the source region of the first cell and the second voltage is applied to the first word line while a third voltage is applied to the plurality of word lines except the first word line, the third voltage being higher than the second voltage.

Abstract: A FLASH EPROM cell in accordance with the present invention is disclosed in which the erasure is accomplished under a constant electric field. The FLASH EPROM cell includes a semiconductor device including a source, a drain and a gate and a constant current circuit coupled to the source. The constant current circuit ensures that a constant field is applied to the tunneling oxide of the FLASH EPROM cell during erasure thereof. In so doing, the FLASH EPROM cell can be erased with a minimum of stress to the device. In addition, the FLASH EPROM cell of the present invention can be used with various power supplies without affecting the characteristics thereof. Finally, through the FLASH EPROM cell of the present invention, the short channel effect associated with smaller device sizes can be substantially reduced.

Abstract: A semiconductor disk device comprising a flash memory having a plurality of blocks, and a CPU for converting a logical sector address into a physical-logical block number and its offset value, for searching for a block and a data memory area in the flash memory based on the physical-logical block number and offset value, and for reading the content of the data memory area when no chain data is stored in an update data chain information memory area. The block comprises a physical-logical block memory area, a plurality of data memory areas for storing data, data status flag memory areas, one disposed corresponding to each of the data memory areas, for storing a data status flag that indicates whether the data memory area stores data, and update data chain information memory areas, one disposed corresponding to each of the data memory areas, for storing chain information indicative of the destination of data.

Abstract: A flash memory array with self-limiting erase for preventing over-erasure utilizes a self-limiting-rase floating gate transistor coupled to the memory array or to each row of memory cells. The self-limiting-erase transistor has a smaller threshold voltage than the memory cells. When all memory cells or one row of memory cells are erased, the drain of the transistor is connected via a feedback path to all word lines of the memory array or to the corresponding word line for that row of memory cells. When the self-limiting-erase transistor is turned on due to full erasing, the potential of the word lines is pulled up to the erasing voltage which is applied at the sources of the memory cells, thereby the erase operation is stopped automatically.

Abstract: A method for controlling the programming and erasure time of a nonvolatile memory array in a memory device. A first value is defined, the first value representing a predetermined number of times a program or erase operation is to be reinitiated on the memory array. A write state machine of the memory device then initiates a program or erase operation on the nonvolatile memory array. The nonvolatile memory array is subsequently verified to determine if the program or erase operation was successful. If unsuccessful, the program or erase operation is repeated either until successful, or until the operation is repeated the predetermined number of times.

Abstract: A non-volatile memory system having means for altering the sequence of operations carried out under the control of an internal state machine which controls the data processing operations performed on the memory system. A flow control register is used to bypass an operation that would be carried out during the normal functioning of the memory system, where the register contains data bits which can be set to alter the operation of the internal state machine. The memory system is first placed into a test mode which is not accessible under the normal operating conditions. After entering the test mode, data can be written to or read from the flow control register. The data in the flow control register is used to alter the process flow of the memory system, thereby allowing a system designer to monitor how changes in the process flow improve the operation of the system.

Abstract: In a nonvolatile semiconductor device having a floating gate formed over a semiconductor substrate, a control gate formed over the floating gate, a source region and a drain region formed within the semiconductor substrate, an erase or write operation is carried out by Fowler-Nordheim tunneling, so that carriers such as electrons and holes are expelled from the floating gate to one of the source and drain regions. Thereafter, carriers of a channel current flowing between the source and drain regions are enhanced and injected into the floating gate, thus converging a threshold voltage of the device.

Abstract: At the time of erasing, the erase verification is not effected but the erase voltage is repetitively applied to the source of a memory cell until it is so judged that the erase current I.sub.A flowing into the source of the memory is smaller than the reference current I.sub.B and when it is judged that the erase current I.sub.A flowing into the source of the memory cell is smaller than the reference current I.sub.B, application of the erase pulse to the source of the memory cell and the erase verification are repetitively effected. As a result, in the flash memory device, it is possible to decrease the number of times of erase verification and reduce the time required for the erasing.

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

Abstract: A nonvolatile semiconductor memory device using a NAND-type EEPROM includes a memory unit, a management unit, an erasure unit, and a control unit. The memory unit has a memory cell array divided into blocks each constituting a minimum quantity of data that may be erased. The management unit manages unused blocks. The erasure unit discriminates erased blocks of the unused blocks from non-erased blocks of the unused blocks to erase data stored in the non-erased blocks. The control unit writes data into at least one block of the unused blocks managed by the management unit. In the control unit, when a content of the written data is obtained by changing data recorded in a different block of the memory unit, and the data recorded on the another block is not necessary, the management unit receives information that the different block is an unused block.

Abstract: A method for correcting over-corrected memory cells in a flash EPROM. The flash EPROM includes an array of memory cells (25), where each of the cells includes a gate 18, a floating gate (16), a source (12), a drain (14), and a substrate (10). The method includes bulk erasing each of cells in the array of cells (step 40), which results in a plurality of over-erased cells. The over-erased cells are then corrected (step 42), which results in a plurality of over-corrected cells. The over-corrected cells are identified (step 44) and selectively erased (step 46), such that a uniform threshold voltage distribution (54) is provided for the cells in the flash EPROM.

Abstract: A non-volatile semiconductor memory comprises a plurality of memory cells each composed of a floating gate field effect transistor, and an erasing circuit connected to a common source line connected to a source electrode of each of the memory cells. The erasing circuit includes first and second field effect transistors each of which has a source connected to an erasing voltage and a drain connected to the common source line. The first field effect transistor responds to a given erase signal to apply the erasing voltage to the common source line for the purpose of erasing date stored in the memory cells. The erasing circuit includes a control circuit for turning on the second field effect transistor when a voltage on the common source line becomes higher than a reference voltage, so that the erasing voltage is supplied through the first and second field effect transistor to the common source line.

Abstract: A flash memory system utilizing low threshold voltage cells so as to provide adequate cell current during read operations even with at low power supply voltages. The cells are arranged into an array of rows and columns, with the source regions of all of the cells connected to a common source line, the drain regions of the cells in one of the columns connected to a common bit line and the control gates of the cells in one of the rows connected to a common word line. In program operations, voltages are applied to the cells so that the program current flows from the cell bit line to the common source line. This results in electrons being injected from the drain toward the floating gate and the floating gate thereby altering the threshold voltage of the cell. In read operation, voltages are applied so that current flow is in the opposite direction, namely from the source line to the bit line. The read current is then sensed at the source line by way of a sense amplifier and associated circuitry.

Abstract: A non-volatile semiconductor memory with an electrically erasable and programmable read only memory showing a high speed batch erasure operation is provided wherein applications of erasure pulse signals onto the memory cells are continued until the number of times of the erasure pulse signal applications made corresponds to a predetermined number already set before commencement of the erasure pulse signal applications, the predetermined number being set to correspond to an estimated number of times of the erasure pulse signal applications necessary for completing the batch erasure operation for subsequently repeating a set of an additional erasure pulse signal application onto the memory cells and a verifying process for verifying erasure states of all the memory cells until there is verified the fact that all the memory cells have been in erasure states.

Abstract: A nonvolatile memory-with cluster-erase flash capability. A cluster information sector is included in each of N clusters, the cluster information sector of each cluster being written with the sequence number assigned to the cluster so that no two clusters have the same sequence number. When erasing a given sector, a controller saves its sequence number prior to erasure. Then, when initializing a given erased sector, the controller sets its sequence number to a value greater than the current maximum sequence number. The controller writes user data to sectors other than the cluster information sector for the cluster thus initialized according to their address sequence. Accordingly, an invalid sector can be distinguished from a valid sector without using an overwrite approach.

Abstract: A FLASH EPROM device includes a memory array organized into a plurality of blocks of memory cells. An energizing circuit applies energizing voltages to the blocks of memory cells to read and program addressed cells, and to erase selected blocks or the whole memory array. An erase verify circuit separately verifies erasure of blocks in the plurality of block memory cells. Control logic controls the energizing circuit to re-erase blocks which fail erase verify. The control logic includes a plurality of block erase flags which correspond to respective blocks of memory cells in the array. The erase verify is responsive to the block erase flags to verify only those blocks having a set block erase flag. If the block passes erase verify, then the block erase flag is reset. Only those blocks having a set block erase flag after the erase verify operation are re-erased. To support this operation, the circuit also includes the capability of erasing only a block of the memory array at a time.

Abstract: In a semiconductor memory device 100 including a power supply voltage decision circuit 101 for detecting whether or not the power supply voltage is higher than a predetermined level to produce an output signal LVD, an oscillator 102 which produces an oscillated signal .phi. as an output signal, an intended counter value altering circuit 103, and a binary counter circuit 104, a writing or erasing time interval is elongated by the output signal LVD, when the power supply voltage becomes lower than the predetermined level.

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Abstract: A NAND Flash EEPROM string is formed in a common N-well and includes a plurality of P-channel MOS stacked-gate storage transistors and P-channel MOS string and ground select transistors. In the preferred embodiment, each P-channel storage transistor is programmed via hot electron injection from the depletion region proximate its P+ drain/N-well junction and erased via electron tunneling from its floating gate to its P-type channel as well as to its P+ source and P+ drain regions without requiring high programming and erasing voltages, respectively. Further, high P/N junction biases are not required during programming or erasing operations. This allows the dimensions of the present embodiments to be reduced to a size smaller than that of comparable conventional N-channel NAND Flash EEPROM strings.

Abstract: An electrically rewritable flash memory device which has a memory cell array arranged in rows and columns of memory cells and which is divided into a plurality of memory blocks having different memory capacities. Each memory block having one or more rows of memory cells. A common voltage control circuit is provided for each of the memory blocks for applying a first potential to a common conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential higher than the first potential to a common conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation.

Abstract: According to a time required for programing operation, respective chips of flash memories are divided into a first group and a second group of chips requiring a time longer than the first group for the programing operation, and a postburn-in test, a high temperature test, and a low temperature test are carried out to a plurality of chips belonging to the first group simultaneously, and to a plurality of chips belonging to the second group simultaneously.

Abstract: A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

Abstract: When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line.

Abstract: A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

Abstract: A flash memory and its data refresh method, where data read out in program verify mode and erase verify mode from read address are compared in each address (ST110), and data of a memory cell corresponding to inconsistent data are rewritten (ST112). Or adding values of data read out in the program verify mode and the erase verify mode are compared in each block (ST137) and a defective block is retrieved and data in each address are compared in the defective block (ST160), and data of a memory cell corresponding to inconsistent data are rewritten (ST162). Thereby, defective data can be retrieved and corrected.

Abstract: An object is to realize a nonvolatile semiconductor storage system which can prevent a false reading operation due to the overerasure, improve the lower limit of operation margin, lower the supply voltage and form a signal power supply. When each of memory transistors 1-4 is subjected to the reading operation, a negative voltage is applied to a non-selected word line WL2 from X-decoder 5 and negative voltage generating circuit 8 to prevent the false reading operation due to the overerasure. When each of the memory transistors 1-4 is subjected to the erasing operations, a negative voltage is applied to word lines WL1 and WL2 to reduce a high voltage to be applied to a source line SL. This can realize low voltage operation and single voltage power supply operation. By applying the negative voltage to the substrate of a memory transistor when it is subjected to the reading operation, the false reading operation due to the overerasure can be prevented.

Abstract: A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses.

Abstract: A content addressable memory has a pair of single-bit memory cells together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state. Each of the memory cells has a pair of transistors. One of the transistors connects a common node to a respective one of a pair of address lines, and another of the transistors connects the common node to a potential of a predefined logic level. Each of the transistors has a gate receiving a logic level of the bit of information stored in a respective memory cell so that one of the transistors is conductive in response to the logic level of the bit of the information when the other of the transistors is not conductive in response to the logic level of the bit of information. Each of the memory cells also includes a transistor connected to the match line and having a gate connected to the common node.