Abstract: A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.

Abstract: A flash-memory system is expandable. Rather than directly connecting individual flash-memory chips to a controller, flash buffer chips are used. Each flash buffer chip can connect to four banks of flash-memory chips. Chip enables for individual chips in a bank are generated from an address sent to the flash buffer chips. Two flash-specific DMA controllers are provided, each with four DMA state machines for controlling the four banks of flash-memory chips attached to a flash buffer chip. This allows for four-way interleaving. Two flash buses connect the two DMA controllers to flash buffer chips. The flash bus has a narrow byte-wide interface to send command, address, and data bytes from the DMA controller to the flash buffer chips. These command, address, and data bytes are then passed through the flash buffer chip to the flash-memory chips. Two additional command signals on the flash bus are used to select and control the flash buffer chips.

Abstract: The invention relates to a method of erasing an electrically programmable non-volatile memory device constructed as a multi-sector matrix memory and being of the type with an erase algorithm integrated into the device. The method comprises the following steps of: erasing some or all of the matrix sectors in parallel; subsequently reading and checking each erased sector; storing the address of a sector being checked when the issue of a check is unfavorable; carrying out a fresh parallel erasing step; and starting a new reading/checking step from the sector that has checked unfavorably.

Abstract: At the time of erasing data, common gate lines connected to selective gates are charged with Vcc or a voltage higher than. This enables reliable cut-off of transfer transistors at the time of erasing data. Accordingly, even if the potential of the selective gates increase in accordance with an increase in the substrate potential of a memory cell portion, current leakage through the transistors can be prevented. Further, at the time of erasing data, the common gate lines are set to V.sub.L slightly higher than Vss. This can enhance the cut-off characteristics of transfer transistors in a non-selected block, and prevent erroneous erasion of data stored in memory cells included in the non-selected block.

Abstract: A non-volatile semiconductor memory device includes an EEPROM array section and a flash memory array section formed on a single chip. The EEPROM memory array section is subjected to a bite-by-bite mode erasure whereas the flash memory array section is subjected to a batch mode erasure. The floating gate of the EEPROM array section has a large area than the floating gate of the flash memory array section.

Abstract: A method for performing multiple writes before an erase to a nonvolatile memory cell is described. A first bit is stored at a first level of a nonvolatile memory cell. A second bit is stored at a second level of the nonvolatile memory cell. A method of erasing a nonvolatile memory cell is described. A level indicator that indicates the next level of the nonvolatile memory cell to write to is incremented. A method of reading a nonvolatile memory cell includes recalling a level indicator. The nonvolatile memory cell is then sensed at a level indicated by the level indicator to determine the state of the memory cell.

Abstract: Memory cells are divided into a plurality of series circuit units arranged in matrix fashion and comprising some memory cells connected in series. The memory cells each consist of non-volatile transistors provided with a control gate electrode, a floating gate electrode and an erase gate electrode. Bit lines to which one end of each of the series circuit units of the plurality of series circuit units arranged in one row are connected in common. Column lines are provided in common for the series circuit units that are arranged in one column and that are respectively connected to each control gate electrode of the memory cells constituting each of the series circuit unit. A voltage by which the selected non-volatile transistor works in a saturation state is applied to the control gate electrode of the selected transistor of a series circuit unit by a column line, thereby injecting hot electrons from the semiconductor substrate into the floating gate electrode.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: A NAND-type flash memory device and driving method thereof is provided. The NAND-type flash memory device includes a first and a second string, a first and a second string select line, a plurality of wordlines, and a first and a second source select line between a bit line contact and a source line. Therefore, predetermined voltages are applied to a first source select line connecting a gate electrode of the first source select transistor, and a second source select line connecting a gate electrode of the second source select transistor to a gate electrode of the fourth source select transistor, thereby preventing unselected cell transistors adjacent to a selected cell transistor from being programmed during program operation of the selected cell transistor.

Abstract: A method of prioritizing program and erase commands received in an operation queue for a memory includes the step of storing a placeholder erase command in the operation queue. Subsequent erase commands are absorbed by 1) storing the subsequent erase command in the operation queue; 2) setting a corresponding status indicator for the block designated by the subsequent erase command; and 3) removing the subsequent erase command from the operation queue, wherein the subsequent erase command becomes an absorbed erase command. If a program command that designates a same block as any one of the placeholder and absorbed erase commands is stored in the operation queue, then 1) the same block is erased; 2) the status indicator for the same block is cleared, if the same block is associated with the absorbed command; 3) the program command is executed; and 4) the program command is removed from the operation queue.

Abstract: Nonvolatile memory devices and methods include an array of nonvolatile memory cells which are arranged in a plurality of rows and a plurality of columns. A plurality of word lines are also included, a respective one of which is connected to the nonvolatile memory cells in a respective one of a plurality of columns. A plurality of lockable cells are also included. A respective one of the lockable cells is connected to a respective one of the plurality of word lines. Each of the lockable cells stores therein a first or a second binary value. The first binary value indicates that nonvolatile memory cells which are connected to the corresponding column of word lines cannot be erased or reprogrammed. The second binary value indicates that nonvolatile memory cells which are connected to the corresponding column of words lines can be erased or programmed.

Abstract: A FLASH EPROM cell in accordance with the present invention is disclosed in which the erasure is accomplished under a constant electric field. The FLASH EPROM cell includes a semiconductor device including a source, a drain and a gate and a constant current circuit coupled to the source. The constant current circuit ensures that a constant field is applied to the tunneling oxide of the FLASH EPROM cell during erasure thereof. In so doing, the FLASH EPROM cell can be erased with a minimum of stress to the device. In addition, the FLASH EPROM cell of the present invention can be used with various power supplies without affecting the characteristics thereof. Finally, through the FLASH EPROM cell of the present invention, the short channel effect associated with smaller device sizes can be substantially reduced.

Abstract: A flash memory device includes a multiple checkpoint erase suspend algorithm. A user may issue an erase suspend command at anytime during an erase process. The erase procedure is suspended as fast as possible by allowing the erase procedure to be suspended at the first to occur of a plurality of checkpoints in the process. The block erase procedure includes a precondition phase (also called a pre-programming phase), in which a selected block is pre-programmed by applying a program potential, and then the pre-programming of the block is verified on a byte-by-byte basis. After the precondition phase, an erase phase is executed in which the selected block is erased by applying an erase potential to the block, and then verifying the erasing of the block. Erase suspend logic is coupled to the erase logic and executes an erase suspend procedure which interrupts the block erase procedure after receiving the erase suspend command during the first to occur of a set of checkpoints in the block erase procedure.

Abstract: A method of prioritizing program commands relative to erase commands in an operation queue for a memory includes the step of initiating an erase of a first block for a first erase command in the operation queue. The memory has a status indicator for each block. The status indicator indicates whether an erase command for its corresponding block has been received and removed from the operation queue but not yet executed (e.g., an absorbed erase command). An interrupt window is executed during the erasure of the first block to determine if the operation queue has received a second command for a second block. If the second command is a program command, then one of three steps is executed. If the first and second blocks are the same, then execution of the program command is deferred until after the erasure of the first block is complete. If the first and second blocks are not the same then the program command is either executed or deferred in accordance with the status indicator for the second block.

Abstract: A nonvolatile memory device includes a plurality of program/select lines arranged in a row direction spaced apart from each other in first prescribed intervals, a plurality of bit lines arranged in a column direction spaced apart from each other in second prescribed intervals at a substantially right angle to the plurality of the program/select lines to form a matrix of a plurality of square areas, and a plurality of control lines disposed in the column direction and adjacent to the bit lines in a one-to-one correspondence. Each cell is disposed in one of the square areas, and has a source, a drain, and a channel region. Further, a select/program gate of each cell allows the selection of the cell for programming and conducting the programming by means of charge carriers. A floating gate stores the charge carriers by means of tunneling through the channel region during erasure and provides the stored charge carriers to the program/select gate through the tunneling diode during programming.

Abstract: Erasing operation can be carried out by applying a given potential difference between the control gate electrodes and the source regions in memory transistors 1a-1d by a potential difference setting section 30. Verifying operation can be accomplished by delecting the threshold voltages of the memory transistors 1a-1d by a verify circuit 8. The potential difference setting section 30 can respond to Detect signals from the verify circuit 8, that is, to the threshold voltages of the memory transistors to control the application time of potential difference or the magnitude of potential difference. In such a manner the overerasing can effectively be prevented and the erasing time can be optimized.

Abstract: An imporved integrated circuit semiconductor static write and read and erase memory cell for storing in both one and more than one bit of binary data, having a switching transistor (M20) for switching on the memory cell, a data write bit line (26) for writing data into the cell using a column write and read and erase sense circuit (46), a data read bit line (28) for reading data stored in the memory cell, data erase bit line (32) for erasing data stored in the memory cell, a magnetic or electromagnetic element (36) for storing data in form of electromagnetism, a data reading element (34) for reading the data stored as magnetism or electromagnetism, an output current and output voltage bit line (35) for providing an output connection to a column write and read and erase sense circuit (46).

Abstract: A nonvolatile memory device. For one embodiment, the nonvolatile memory device includes a bit line, a source line, and a nonvolatile memory cell having a drain coupled to the bit line, a source coupled to the source line, a control gate, and a floating gate. The nonvolatile memory device also includes a source voltage generator circuit coupled to the source line and generating a source line voltage when programming the nonvolatile memory cell. The source voltage generator circuit varies the source line voltage based on a location of the nonvolatile memory cell in the memory array. The nonvolatile memory device may also include a drain voltage generator circuit coupled to the bit line and generating a bit line voltage when programming the nonvolatile memory cell. The drain voltage generator circuit varies the bit line voltage based on the location of the nonvolatile memory cell in the memory array.

Abstract: An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns.

Abstract: In a nonvolatile semiconductor memory device comprising an address driving section comprising an N-channel transistor (11) and a P-channel transistor (12) and a memory cell (15) for erasing stored contents therefrom by supplying a control gate (CG) with a predetermined voltage, a negative voltage generation circuit (25) supplies a negative voltage to one of source and drain of the N-channel transistor (11) on erasing the stored contents in order to supply the negative voltage to the control gate (CG) of the memory cell (15) via the N-channel transistor (11), thereby erasing the stored contents from the memory cell (15). On writing data in the memory cell (15), a positive voltage generation circuit (30) supplies the control gate (CG) of the memory cell (15) with a higher voltage than an output voltage of an address driving section (10, 11, 12) in place of the output voltage of the address driving section.

Abstract: A memory card includes data protection circuitry preventing unauthorized reading of data from and writing of data into a memory. Authorized memory access begins when specific data is attempted to be written into a specific address. This step activates a timer for an active time period during which data can be read from or written to the memory card upon receipt of appropriate control signals. When the active period of the timer has elapsed, access to the memory card is denied until the specific data is again attempted to be written into the specific address.

Abstract: The invention enables random read and write operations into cells in an array of a memory device. It includes a decoding scheme wherein the memory chip has a row address bit which is used for the row decoding also participates (in some embodiments) in the column and bit-line decoding process.The data is routed to and from the alongated bit-line by a selector at one bit-line end and/or by a separate selector at the other end of the same bit-line. This is accomplished by address circuitry and column selection circuitry. Data is read out and processed by a signal processing means such as a sense amplifier and/or data buffer.In some embodiments such as flash EEPROM device, programming voltage VPP is applied to the bit-line only through the selector at one end of the bit-line.

Abstract: Disclosed is an electrically erasable and programmable non-volatile storage device, which has: an erase operation control means for outputting a first signal to write or erase data to or from a memory cell when receiving a write or erase operation signal; a write or erase pulse width control means which decides a write or erase pulse width according to the first signal and outputs a pulse; a write or erase pulse generating means which generates a write or erase pulse to be applied to the memory cell according to the pulse output from the write or erase pulse width control means; a verifying means which decides whether or not the memory cell to which the write or erase pulse is applied reaches a threshold voltage and which outputs the decision as a second signal to the write or erase operation control means; and a write or erase pulse width setting means which outputs a third signal to change the write or erase pulse width on the basis of the first signal and the second signal to the write or erase pulse width

Abstract: A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with each of the cells including a source region, a drain region, a channel region intermediate the drain and source region, a floating gate disposed over the channel region and a control gate disposed over the floating gate, with the cells located in one of the array columns having their drains connected to a common bit line and with the cells in one of the rows having their control gates connected to a common word line. The memory system includes a control circuit carrying out read, programming and erase operations. The erase operation is performed by applying a negative voltage to control gate of the cell being erased and a positive voltage to the source of the cells being erased.

Abstract: A non-volatile memory latch device includes two PMOS memory cells and a cross-coupled static latch having two PMOS transistors and two NMOS transistors. The floating gates of each PMOS memory cell/transistor pair are coupled together. The control gates of all four PMOS devices are commonly connected to an input. The latch is programmed by applying -3 to -8 volts to the drain of one of the PMOS memory cells, floating the drain of the other PMOS memory cell, and applying 7 to 11 volts to the control gates of all four PMOS devices. The latch is erased by applying 3 to 8 volts to both drains of the PMOS memory cells and -7 to -11 volts to the control gates of all four PMOS devices. Lower programming and erasing voltages are possible with the PMOS latch, as compared with conventional NMOS latches.

Abstract: A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminates over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

Abstract: The present invention relates to a flash memory device and is constructed in such a way that the memory cell blocks are sequentially selected according to the input of the erasing signal and the output voltage of the negative charge pump is supplied only to the selected memory cell block to prevent the degradation of the operational performance of the device due to excessive load applied to the output terminal of the negative charge pump at the time of erase operation. Therefore, the present invention relates to a flash memory device in which the magnitude of the load applied to the output terminal of the negative charge pump is effectively reduced and accordingly, the degradation of operational performance of the device can be prevented.

Abstract: In a matrix array of memory cells, each memory cell includes a control gate, and first and second terminals for defining a channel therebetween, with the second terminals of the memory cells being connected to a common circuit node. During a write modes a row of memory cells and a column of memory cells are selected, and a first voltage is supplied to the control gates of the memory cells of the selected row and a second voltage which varies positively as a function of temperature is supplied to the first terminals of the memory cells of the selected column for trapping electrons in at least one of the memory cells. During an erase mode, ground potential is supplied to the control gates of all memory cells and a third voltage which varies negatively as a function of temperature is supplied to the common circuit node to remove the trapped electrons from the memory cells.

Abstract: An improved sensing device for an integrated circuit memory device is provided. In particular, the memories can be those in which memory cells are formed by insulated gate transistors, such as EPROMs and flash EPROMs. Conventionally, such memories use static sence amplifiers. The present invention provides a dynamic sence amplifier suitable for use in these memories.

Abstract: A semiconductor memory device includes a semiconductor substrate, a memory cell array having memory cells, each of which stores data, formed in matrix on the semiconductor substrate, a plurality of data latch circuits, each, of which is arranged at one end of at least one bit line connected to the memory cell array and for latching programming data, a control section for judging whether all of a plurality of latched data included in date latch groups constituted by the plurality of data latch circuits are the same as a first data or not and for controlling to change a potential of a plurality of first nodes according to the judging result, a section for detecting potentials of the plurality of the first nodes and for judging whether all data latched by the latch circuits are the same as the first data and for controlling to change a potential of a plurality of second nodes according to the judging result, and a section for detecting the potential of the plurality of second nodes and for outputting a judging r

Abstract: A common source line control circuit for a semiconductor memory device includes a resistor connected in series with a transistor to reduce the voltage across the transistor, thereby preventing snap back breakdown. The resistor and transistor are connected in series with a second transistor which together form a current path between the bulk region of a memory cell array and a ground node for discharging the bulk region during an erase voltage recovery period. The resistor can be connected between the transistors or between one transistor and the bulk region. A second resistor can be connected in series with the other resistor and the two transistors. The resistance values of the resistors are larger than the channel resistances of the transistors.

Abstract: In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

Abstract: An electrically programmable cell comprises a substrate of the first conductivity type having a channel region, a control gate on a first insulating layer above the channel region, a source region and a drain region of a second conductivity type, on both sides of the channel region, at least the drain region including a low-doped region adjacent to the channel, a floating gate on a second insulating layer above at least a portion of said low-doped region. The thickness of the second insulating layer is lower than the thickness of the first insulating layer and is low enough for having charge transfers through tunnel effect.

Abstract: A configuration circuit includes a plurality of configuration cells where each configuration cell has (a) a nonvolatile pull-up cell coupled to an output node and for coupling to a first power supply voltage, and (b) a nonvolatile pull-down cell coupled to the nonvolatile pull-up cell and to the output node and for coupling to a second power supply voltage, where the nonvolatile pull-up cell includes a first nonvolatile transistor, and the nonvolatile pull-down cell includes a second nonvolatile transistor. The configuration cell may further include a volatile transistor in the nonvolatile pull-up and/or pull-down cells. In addition, the configuration cell may include a first erase device coupled to the first nonvolatile transistor for discharging charges on the floating gate of the first nonvolatile transistor and a second erase device coupled to the second nonvolatile transistor for discharging charges on the floating gate of the second nonvolatile transistor.

Abstract: A memory system includes a flash memory having a plurality of individually erasable physical blocks, table section for holding the relationship in correspondence between the logical blocks allocated by the allocation section and the physical blocks first counting and managing section for counting and managing write counts of the respective logical blocks, first classifying section for classifying the logical blocks into a plurality of groups on the basis of the respective write counts of the logical blocks, erasure section for erasing data in a physical block allocated to a logical block to produce a free physical block, second counting and managing section for counting and managing the erasure counts of the respective physical blocks, second classifying section for classifying the physical blocks into a plurality of groups on the basis of the respective erasure counts of the physical blocks, control section for allocating the respective logical blocks to the physical blocks; and managing section for managing

Abstract: A discharge circuit for a semiconductor memory includes a first node, a second node for receiving a control signal having first and second states, and a circuit connected between the first node and ground potential and to the second node. The circuit couples the first node to ground potential when the control signal has the first state and substantially isolates the first node from ground potential when the control signal has the second state. The circuit includes a first subcircuit for defining a current path between the first node and ground potential. The first subcircuit includes a plurality of transistors connected in series, each of which having a gate, source and drain. The circuit further includes a second subcircuit for effecting predetermined gate-to-source, and drain-to-source voltages of the transistors of the first subcircuit when the control signal has the second state.

Abstract: The present invention relates to a flash memory device and, more particularly, to a flash memory device which is constructed to prevent over-erase and stress of a cell by preventing re-erase of a sector, which was confirmed as a pass, at the time of the re-erase operation due to an occurrence of a fail sector by storing the address of the sector, which was confirmed as a pass, at the time of the erase operation of a multi sector, so as to improve the reliability of the product and the life of the cell.The present invention generally applies to all the devices which utilize a multi sector erase performing algorithm among flash memory devices which utilize a stack memory cell.

Abstract: Circuitry and methods for performing a global erase of an array of electrically-erasable programmable read-only memory (EEPROM) transistors are provided. The voltages used to erase the EEPROM transistors are controlled so that the maximum voltage across the gate oxide of previously erased transistors in the array does not exceed a predetermined maximum acceptable voltage level, thereby avoiding gate oxide damage due to high electric fields.

Abstract: A method for selectibly erasing one or more non-volatile programmable memory cells in an integrated circuit. The method is applicable to an array 1 of memory cells 10 fabricated in a semiconductor substrate 30 of a first conductivity type semiconductor material, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. The cells should be formed in a first well 33 of said first conductivity type semiconductor material, the first wells being formed in second wells 31 of a second conductivity type semiconductor material, the first wells including cells in groups of one or more. The method involves the steps of applying a high voltage source to a selected one or more column lines, applying a zero voltage source to a selected one or more row lines; and applying the high voltage source to non-selected row lines.

Abstract: Nonvolatile integrated circuit memory devices, such as EEPROMs, use unselected shared latching sense amplifiers to latch data from memory cells which are to be reprogrammed after a page erase, and to resupply the latch data to the memory cells which are to be programmed after erase, to thereby internally reprogram the latched data into erased memory cells after page programming. Transferring circuits and methods are provided for transferring data between shared latching sense amplifiers to permit internal reprogramming. High speed and simplified reprogramming of EEPROMs is thereby provided.

Abstract: The present invention discloses an electronic memory system having semipermanent memory storage, a memory device for rapid data transfer and temporary memory storage, and controller for monitoring and controlling writes to the semipermanent memory storage.

Abstract: The present invention provides method to erase and program flash EEPROMS devices using a clipped sine waveform (Vg). The clipped sine waveform reduces the tunneling oxide electric field between the floating gate and the source or drain region thereby reducing electron trapping. The method for the erase cycle comprises: applying a positive voltage to a source region; grounding a well region; floating the drain region; and simultaneously applying a negative clipped sine waveform voltage to a control gate during the erase cycle. The program cycle of the invention comprises: applying a voltage to a drain region; grounding a well region; floating a source region; and simultaneously applying a clipped sine waveform voltage to the control gate whereby the clipped sine waveforms reduce the electric field in a tunnel oxide layer which reduces the electron trapping.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A control gate driver circuit (900) provides a variety of voltages to a control gate (21) of a floating gate nonvolatile memory cell (10) using a single circuit. During a read mode, a bias circuit (920) and a reference transistor (925) bias a pass transistor (936) connected to the output of a level shifter (910) to be slightly conductive and thus biases control gates without the need for a charge pump. During programming, a pulse circuit (940) gradually builds the program voltage provided to cells along a selected row, allowing the use of smaller pass transistors (932, 934) and smaller capacitors in the charge pump of the supply (930). Cells in an unselected row are driven to a different voltage, decreasing junction leakage and maintaining high disturb voltage in cells in the unselected row. The control gate driver circuit (900) is implemented using only P-channel pass transistors, eliminating the need for a costly triple-well process.

Abstract: An erase voltage control circuit for an electrically erasable non-volatile memory cell having a control electrode and a first electrode. The circuit includes negative voltage generator means for generating a negative erase voltage to be supplied to the control electrode of the memory cell and means for electrically coupling the first electrode to a voltage supply. The circuit further includes control means for selectively deactivating the negative voltage generator means when a current supplied by the voltage supply to the first electrode of the memory cell reaches a predetermined value.

Abstract: A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses.

Abstract: An object of the invention is to vary data width by changing over the readout mode, to change over the number of operating sense amplifiers in order to minimize the readout current, and to reduce the power consumption. A switch circuit operates only half of sense amplifiers by a first EN1 signal when the output data width is set at 8 bits by data width control signal BYTE. At this time, other sense amplifiers are not put in action, and hence the power consumption is saved. When the external output is 16 bits, all sense amplifiers are put in operation. Besides, in the case of internal readout operation such as verification by internal state signal RUN, all sense amplifiers are operated to perform an efficient high speed operation.

Abstract: A P-channel MOS memory cell has P+ source and drain regions formed in an N-well. A thin tunnel oxide is provided between the well surface and an overlying floating gate. In one embodiment, the thin tunnel oxide extends over a substantial portion of the active region and the device. An overlying select and control gate is insulated from the floating gate by an insulating layer. The select and control gate including an elongated extension portion for preventing overprogramming of the circuit. The device is programmed via hot electron injection from the drain end of the channel region to the floating gate, without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate to the N-well with the source, drain, and N-well regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring and destructive junction stress.

Abstract: A circuit and method for generating an erasure voltage and a programming voltage for an EEPROM array, the cells of the EEPROM array being capable of erasure and programming. A signal having an increasing voltage is generated. That signal is monitored, and the increase in voltage of said signal is terminated when the signal reaches a first selected maximum level in an erase operation of at least one cell of the EEPROM array. In a program operation of at least one cell of the EEPROM array, the increase in voltage of the signal is terminated when said signal reaches a second selected maximum level.

Abstract: This invention relates to a threshold voltage verification circuit of a non-volatile memory cell which can automatically verify a threshold voltage of the cell according to the change of electron charge which is injected to a floating gate of the cell in program operation and erasure operation for the cell.