Abstract: In the present invention a flash memory configuration is disclosed that eliminates the need for one of two pump circuits that are commonly required to support an erase function of memory cells on a flash memory chip. The flash memory cells are placed into a triple well structure with a P-well contained within a deep N-well that resides on a P-substrate. The bias voltages for erase of the flash memory cells are chosen so as to require only one voltage pump circuit to be included in the flash memory chip. The chip bias, V.sub.DD, is used for the source of the memory cells and a negative gate voltage is raised in magnitude to maintain the efficiency of the erase operation. The P-well is biased with a negative voltage that is sufficient to prevent the high negative voltage connected to the gate from causing breakdown in word line decoder circuits. The deep N-well and the P-substrate are biased such as to back bias the P/N junctions between the triple well structure.

Abstract: A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further V.sub.cc scaling becomes possible.

Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

Abstract: In a static RAM, a complete erasure of the memory is achieved by sequentially propagating an erasure control signal from one group of memory cells to a next group of memory cells through delay circuits calibrated to correspond to a maximum time duration of erasure of the previous group of cells.

Abstract: A ramping circuit gradually applies an erasing voltage to a memory cell. Within the ramping circuit an NMOS transistor is disclosed which gradually supplies the erasing voltage to the memory cell in response to an external ramping voltage. The NMOS transistor supplies the erasing voltage until the body effect loss voltage of the transistor limits a maximum erasing voltage that the NMOS transistor can supply. The specification then discloses a PMOS transistor which operates to supply the erasing voltage to the memory cell when the NMOS transistor can no longer do so. The PMOS transistor is connected to control circuitry which keeps the PMOS transistor inactive until the output voltage of the NMOS transistor is limited by its body effect voltage loss.

Abstract: A method of screening EEPROMs for data retention quality employs a UV source which is arranged to be impinged upon the devices while in wafer form, at or near an electrical probe station. Known data is stored in memory cells on an EEPROM chip while the chip is in wafer form, at a probe station. The wafer is then moved beneath a UV silo near the probe station and exposed to UV light, for a period of time and at an intensity which is sufficient to cause leakage of charge from potentially leaky floating gates. The wafer is again subjected to electrical probe where the amount of change in retained charge is detected. From this test, an indication of the charge retention ability of the devices is obtained. The UV light increases the energy state of the stored charge thus accelerating the decay of the stored charge located on the floating gates in the EEPROM device. Bits that have inherent leakage paths decay more rapidly.

Abstract: A microcomputer comprising a CPU for outputting a signal requesting generation of pulses when receiving an erase signal requesting processing to initialize a flash memory unit; a timer for generating the pulses when receiving the signal requesting generation of the pulses output by the CPU wherein the frequency of a system clock is divided to produce clock pulses and each of the pulses is generated whenever the number of clock pulses reaches a set value; and a memory control unit for executing the processing to initialize the flash memory unit as well as measuring a time it takes to carry out the processing by counting the number of pulses output by the timer when receiving the erase signal.

Abstract: An integrated electronic control circuit comprises a microcontroller connected to at least one volatile memory, at least one input/output port, a plurality of control devices, and an electronic non-volatile memory device comprising a non-volatile memory cell matrix linked to a control register, and a switch element connected between a voltage reference and the cell matrix to enable the program mode of the cell matrix under control by the microcontroller.

Abstract: A method for writing to a bit of a non-volatile memory (50) by alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). Upon completion of the write operation a verify erase (VE) indication and a verify program (VP) indication are provided to a memory controller (58), which then determines if multiple cycles are necessary. The configuration of the memory cell allows isolation of each bit in the memory array to avoid effects of writes to neighbor bits. According to one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete.

Abstract: An erase board or erasable board is provided with a substrate layer disposed underneath a clear film layer. The clear film layer is written on with dry erase markers. Graphics may be disposed directly on the substrate or a middle sheet may be provided for placement between the clear layer and the substrate. The middle sheet may accommodate graphics, design or other indicia which may be printed on the middle sheet by hand or by computer. The middle sheet may be easily and conveniently replaced and substituted with another middle sheet having an alternative design printed thereon.

Abstract: Applying a negative voltage to unselected word-lines during a read or verify operation reduces leakage current from over-erased memory cells, which allows the memory cells to be over-erased and therefore, to be programmed with lower threshold voltages. The consequence is a non-volatile memory having wider threshold voltage windows, which results in improved resolution and SNR for analog/multi-level and multi-bit-per-cell storage. During programming, the negative voltage is applied to word-lines containing unselected and erased memory cells in the same bit-line as the selected cell to prevent leakage current from over-erased cells, and a ground potential is applied to word-lines containing unselected and previously programmed cells in the selected bit-line to prevent drain disturb.

Abstract: An EEPROM device has an array of memory cells composed of nonvolatile data-storage elements that allow electrical writing and erasing of data. The array of memory cells is provided with an area for storing data representing the length of writing time for which the writing and erasing of data are performed. The writing-time data is read out from this area and held in a latch circuit. The latched data is used as the target count up to which a counter counts a clock. The counter starts counting in response to a start signal and stops counting when the actual count reaches the target count. The counter, while it is counting, outputs a high-level signal, which determines the length of writing time for which writing is performed in the memory cells.

Abstract: A method of erasing a flash memory cell to suppress bi-directional tunnel oxide stress that includes applying a negative voltage to the control gate of the flash memory cell, applying a bias voltage to the substrate of the flash memory cell and applying a bias voltage to the drain of the flash memory cell that equals the bias voltage applied to the substrate minus a fraction of a diode voltage drop across the drain junction formed between the drain and the substrate. The bias voltage applied to the drain is selected so that the drain junction is not forward biased. The fraction is in the range of 20% to 80% of the diode voltage drop.

Abstract: Disclosed is an electrically modifiable, multilevel non-volatile memory including internal refresh means. If a memory with n sectors is considered, only n-1 sectors are allocated simultaneously to the storage of the data elements, the remaining sector or refresh sector is used to receive the duplicated data from one of the n-1 sectors assigned simultaneously to the storage of the data elements. After each duplication, the duplicated sector is replaced by said refresh sector and itself becomes the new refresh sector, in such a way that that all the n sectors, in turn, take part in the refresh operation.

Abstract: An electronic control unit includes a flash memory as a nonvolatile memory, which is capable of erasing its storage contents block by block, for storing control programs and data. An erasure processing is carried out for the storage content in each of the blocks identified by an erasure command received from an external device, and a rewrite processing is carried out to replace the erased content with a new content received from the external device. The number of the erasure processing is counted only once when the first one of the erasure commands is received for a plurality of blocks, as long as the control unit is held operative after its initial condition.

Abstract: A memory management method for use in a portable computer to prolong the lifetime of an internal battery in the portable computer. The portable computer includes a non-volatile memory storage device. When the portable terminal is operating from the internal battery or cell, a recording operation is performed in an unused memory region and an address value of data to be deleted is registered in a delete queue, rather than being deleted at that time. Later, when the portable terminal is connected to an external power source, data to be deleted is deleted all at the same time, thereby reducing power consumption of the battery or cell in the portable computer. This method utilizes less capacity of the cell and prolongs operation time of the internal battery cell. Data can be recovered when a user desires recovery of the data unless the data corresponding to the address values recorded in the delete queue has already been deleted.

Abstract: To reduce the risks of erroneous data writing into an electrically erasable and programmable non-volatile memory (10) (EEPROM) when a failure in the memory (10) voltage supply (Vcc) occurs during a programming or erasing operation, the memory (10) comprising means (30) of generating programming or erasing high voltage (Vpp), means (SW.sub.i, TI.sub.i,) are provided for maintaining the high voltage (Vpp) supply to the cells (C.sub.i,j) of the memory and capacity (Chv, CR.sub.2) of sufficient power to maintain the high voltage (Vpp) during the time required for the programming or erasing operation. The invention is useful particularly for EEPROM memories mounted on chip cards and electronic labels.

Abstract: An apparatus and method for constructing a capacitor loaded memory cell. This capacitor loaded memory cell operates as a static random access memory (SRAM) cell if a particular capacitor and transistor configuration is used. Normally, capacitors are not an obvious choice as a load device for a memory cell because the intrinsic nature of capacitors is one that blocks the flow of direct current, the invention takes into account the secondary effects such as leakage of a particular dielectric used in the construction of the capacitor to modify the current blocking nature of the capacitor.

Abstract: In accordance with an embodiment of the present invention, a controller device is disclosed for use in a digital system having a host and nonvolatile memory devices. The controller device is coupled to the host and at least two nonvolatile memory devices. The host stores digital information in the nonvolatile memory unit and reads the stored digital information from the nonvolatile memory unit under the direction of the controller, the memory unit being organized into blocks of sectors of information. The controller device erases the digital information stored in the blocks of the nonvolatile memory devices in-parallel form. The controller device includes a space manager circuit responsive to address information from the host and operative to read, write or erase information in the nonvolatile memory unit based upon the host address information.

Abstract: A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.

Abstract: There is provided a non-volatile semiconductor memory which is capable of establishing a proper reading voltage for an erasure threshold voltage and a proper writing time for the reading voltage by detecting the threshold voltages for writing and erasing in a memory cell array. The present non-volatile semiconductor memory, which is called a flash EEPROM, includes a first memory cell array 1, a second memory cell array 2, a row decoder 3, a line decoder 4, a reading control circuit 5, a writing and erasing control circuit 6, a writing time control circuit 7, a high voltage generating circuit 8, a counter circuit 13, a 1/N circuit 9, and a reading voltage generating circuit 11. The first memory cell array 1 and the second memory cell array 2 are formed on a same memory cell array, and all of the data stored in both memory cell arrays can be erased at once. Thus, all the memory cells in the memory cell array have the same erasure threshold voltage.

Abstract: A method and apparatus for providing a charge pump that is particularly useful for generating high voltages and high currents for erasing and programming flash electrically-erasable programmable read only memory arrays (Flash EEPROMs). The invention includes an efficient method and circuit for generating a pumped voltage with no voltage drop from one stage to the next by using a simple two-phase clocking scheme and an auxiliary pump to gate a larger primary pump. One feature allows adjustment of the level of voltage pumping to accommodate higher voltage power supplies.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array, a plurality of word lines, a plurality of digit lines, a data setting circuit, a write data latch circuit, an X decoder, a write circuit, and a timing control circuit. In the memory cell array, memory cells are arranged in a matrix. Each word line is commonly connected to the memory cells of a corresponding page. Each digit line is commonly connected to the memory cells of a corresponding bit and address. The data setting circuit inverts input data in an erase mode and directly outputs it in a write mode. The write data latch circuit latches data output from the data setting circuit in correspondence with a bit and address designated by an address signal. The X decoder selects a word line corresponding to a page designated by an address signal out of the word lines upon reception of a simultaneous write start signal.

Abstract: The negative supply voltage used by the drivers during sector or chip level erase operations is decoded separately from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry coupled to the set of wordlines is provided. The wordline driver circuitry includes a first supply voltage source, a second supply voltage source, and a set of wordline drivers. The wordline drivers are coupled to the first and second supply voltage sources, and selectively drive wordlines in the set of wordlines with a wordline voltage from either the first supply voltage source or the second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors.

Abstract: A wear leveling system and method of a flash memory cell uses the amount of time required to perform an erasing operation on a sector of the flash memory to determine whether the memory cells in the sector have degraded to an unacceptable level. The actual time required to erase a sector of a flash memory array is compared to a reference erasing time required to erase a unit sector under the state of the worst allowable degradation. If the actual erasing time of a sector exceeds the reference erasing time, logical addresses corresponding to the sector are re-mapped to the physical addresses of a different sector. On the other hand, when the actual erasing time is shorter than or equal to the reference erasing time, a controller continues to use the unit sector.

Abstract: A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

Abstract: An EEPROM is organized in matrix form in word lines and bit lines. Storage cells are placed at the intersections of these lines. The cells include floating gate storage transistors. Groups of cells having separate bit lines but sharing a word line are created. Each group is connected to a group selection transistor. The group selection transistor selectively connects the control gates of the storage transistors to control lines, which provide potentials for enabling programming, erasure or reading of the storage transistors.

Abstract: The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.

Abstract: A flash memory cell. The flash memory cell includes first and second transistors. The first transistor has a control gate coupled to a word line, a drain coupled to a data line and a floating gate. The second transistor, similarly, includes a control gate coupled to the word line, a drain coupled to a second data line and a second floating gate. The first floating gate stores a state of the second transistor prior to programming of the flash memory cell. Further, the second floating gate stores a programmed state of the second transistor. A difference between the states of the first and second transistors represents the value of the data stored in the flash memory cell.

Abstract: A system includes a microcomputer. The microcomputer includes a clock signal circuit, a measuring circuit, a central processing unit, and a flash memory. A user sets a frequency of a clock signal provided by the clock signal circuit. The measuring unit counts a number of cycles of the clock signal in a period specified by reference data. The central processing unit receives the clock signal from the clock signal circuit and operates in accordance with the clock signal. The flash memory stores data which is electrically erased during an erase operation. The erase operation is executed during an erase time which includes a number of cycles of the clock signal calculated by the central processing unit. The central processing unit calculates a time for one cycle of the clock signal as a function of the period specified by the reference data and the number of cycles counted by the measuring unit.

Abstract: A method to program data to and erase data from a split gate flash EEPROM to improve programming and erasing speed, and to improve endurance is disclosed. The programming the split gate flash EEPROM cell is accomplished by simultaneously applying a first positive voltage to the control gate, applying a first moderately negative voltage to the semiconductor substrate, applying a slight potential to the drain region to supply a constant programming current, and applying a second positive voltage to the drain region. The first positive voltage, the first moderately negative voltage, the slight positive potential and the second positive voltage are applied for a sufficient time to cause electrons to be trapped on the floating gate.

Abstract: An electrically alterable nonvolatile semiconductor memory device has a first memory array including a plurality of first memory cells and a second memory array including at least one second memory cell, wherein contents of the first memory array and contents of the second memory array are capable of being altered independently of each other and variation of a specific quality of each second memory cell due to altering of the contents of the second memory cell is examined, in order to estimate the life of the first memory array.

Abstract: A semiconductor nonvolatile memory wherein memory cells in which data is electrically processed are arranged in the form of a matrix, provided with an error correcting circuit for correcting error bits when there are less than a predetermined number of error bits in a plurality of bits of data; a circuit for processing data in units of the plurality of bits of data in the memory cells of the plurality of units and for counting the number of the unprocessed memory cells after data is processed; and a circuit for ending the processing of the data while leaving the unprocessed memory cells when the number of the unprocessed memory cells is less than the predetermined number of error bits and making the error correcting means save the error bits.

Abstract: Integrated circuit memory devices with page copy flag cells include an array of memory cells and a plurality of flag cells coupled thereto which retain a flag to indicate whether a respective page of memory cells contains data copied in an inverted format from another page of memory cells. The memory cells and flag cells may comprise EEPROM cells and each page of memory cells preferably shares a word line with a respective flag cell. The flag may constitute a logic 1 (or logic 0) signal stored in the flag EEPROM cell to indicate whether the data in the corresponding page of memory is a true or an inverted copy of a page of data copied from another page at a different address. A page buffer is also provided to retain data read from a page of memory and read from a corresponding flag cell, and an exclusive OR gate for inverting the data outputted by the page buffer if the flag has been set and passing the outputted data unchanged if the flag has not been set.

Abstract: A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.

Abstract: This invention discloses a method of erasing a flash memory, in which the method comprises: (A) erasing all cells of a selected sector; (B) verifying in cells whether the cells are erased; (C) saving an address corresponding to a non-erased cell and re-erasing the cells when the non-erased cell is detected by the step (B); (D) verifying in cells, from the saved address to the final address whether the cells are erased; and (E) executing a slight-program for recovering over-erased cells so that the cells of the sector are normally erased.

Abstract: In a data erase operation of the present invention, a drain terminal is opened. A negative voltage of about -10 V and a voltage of about 5 V are applied to a cell gate and a source terminal, respectively. The voltage of about 1-2 V is applied to a P well terminal and an N well terminal. A ground potential is provided to a substrate. A voltage which is lower than the voltage of the source terminal and higher than the substrate voltage (ground voltage) is applied to a P well and an N well between a source diffusion layer and the substrate. Thus, an electric field generated between a source and a floating gate realizes the erase by means of F-N tunneling.

Abstract: The present invention is a non-volatile memory comprising: first and second floating gate MOS transistors which are electrically written and erased and which are operatively connected between power sources serially; and an output terminal connected to the contact point of the first and second MOS transistors; wherein a first datum is stored by writing to the first MOS transistor and erasing the second MOS transistor, and a second datum is stored by erasing the first MOS transistor and writing to the second MOS transistor. With the aforementioned memory device, through current does not flow to the power source, because only one transistor will be conductive even if read voltage is applied to the control gate of both transistors. Consequently, reading time can be shortened, without leading to increased power consumption, by maintaining the control gate at the read voltage level.

Abstract: New bias conditions for flash memory cells and X-decoder circuits for providing the bias conditions. In an erasing operation, a positive high voltage is provided to the bulk and a negative high voltage is provided to the control gate for establishing a sufficient electric field to induce electron tunneling effect. In an operation for repairing a cell's threshold voltage, the biased voltages are reversed. A first X-decoder circuit structure is presented for supplying positive and negative high voltages to the memory cells for block erasing or repairing. The first X-decoder circuit structure has a plurality of X-decoder blocks each being constructed in a separated X-decoder well, and the memory cells are fabricated in a separate common array well. A second X-decoder circuit structure is presented to provide an appropriate bias condition for erasing or repairing a small sector of word lines. For the second X-decoder circuit structure, each memory block is fabricated in a separated array well.

Abstract: An erase state machine controls the process of erasing all the memory cells in a selected sector of a flash memory array. The erase state machine includes a sequence of states for controlling generation of high positive and negative voltages, and application of the high positive voltage to all word lines in the selected sector and application of the high negative voltage to the source nodes of all memory cells in the selected sector. A sequence of two discharge states are used to discharge the high voltages from the word lines and source nodes. If an erase operation is aborted while high voltages are being generated, the erase state machine asynchronously transitions to the first of the two discharge states, and then transitions to the second discharge state and then back to a final inactive state during successive state machine clock cycles.

Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple wall. The control gate is negatively biased. By biasing the P-well and drain (or source) positively within a particular voltage range when erasing, GIDL current and degradation from a hole trapping can be diminished and hence scalable technology may be achieved.

Abstract: Methods and apparatus for achieving analog storage in a non-volatile memory array. The array consists of memory cells that utilize Fowler-Nordheim tunneling for erasure and hot electron injection for programming. Writing into a cell is performed by an initial erasure followed by a controlled sequence of program operations during which the cell is programmed in small increments. The stored voltage is read after each program step and when the voltage read back from the cell is equal or just beyond the desired analog level, the sequence of program steps is terminated. The read condition for the cell applies a positive voltage to the drain or common line and a positive voltage to the control gate. The source is connected through a load device to a negative (ground) supply. The output from the cell is the actual voltage that exists at the source node. There is no current sensing or comparison with a reference voltage to determine the output state.

Abstract: A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data.

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

Abstract: An EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a P-well of a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.

Abstract: The negative supply voltage and isolation well bias used by the drivers during sector or chip level erase operations are decoded separately from each other and from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry using shared isolation well MOS transistors coupled to the set of wordlines is provided. The wordline driver circuitry includes a first supply voltage source, a second supply voltage source, a third supply voltage source for the shared isolation well and a set of wordline drivers.

Abstract: A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area.

Abstract: Methods and systems for floating gate memory cell array erasure with wordline level retry are disclosed. A data storage device includes a memory array organized into a plurality of blocks of memory cells, each of the blocks including a plurality of wordlines of memory cells. An energizing circuit applies energizing voltages to the memory cells to read and program addressed cells, and to erase selected blocks of memory cells, or the whole memory array. An erase verify circuit separately verifies erasure of the individual wordlines that compose each block that is erased. The control logic can include a plurality of shared wordline erase flags which correspond to respective wordlines in each particular block as they are verified. If the wordline passes erase verify, then the wordline erase flag is reset. Only those wordlines having a set wordline erase flag after the erase verify operation are re-erased.

Abstract: An EEPROM includes a multiplicity of memory cells which are disposed in a memory cell array and can be addressed through the use of word, bit and source lines for writing, reading out and erasing. The memory cells which can be addressed through a single word line are divided into a multiplicity of groups, of which each is assigned a separate common source line. A method of driving the EEPROM carries out a group-by-group writing to, reading from and/or erasing of the memory cells which can be addressed through a single word line.

Abstract: A secondary storage device using a nonvolatile semiconductor memory in which individual block areas constituting the nonvolatile semiconductor memory can be used up to their limit of use. When the number of repetitions of erasure in a second block area has reached a predetermined reference value, a searching unit searches active block areas for an alternate block area. A second writing unit writes information which has been stored in the alternate block area, into the second block area. A second correspondence modifying unit associates the physical block number with the logical block number and causes a logical-physical correspondence storing unit to store the correspondence of the thus-associated block numbers. A second erasing unit erases the information stored in the alternate block area and treats the block area with the physical block number as a spare block area.