Abstract: The present invention disclosed a method of erasing a flash memory comprising the step of applying a drain bias voltage for erasing to any one of said sectors; applying a drain bias voltage for erasing to a next sector before said sector is completely erased, whereby the sectors are erased sequentially.

Abstract: Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Abstract: Techniques are used to evaluate margin of programmable memory cells. In particular, techniques are used to measure negative erased threshold voltage levels. Techniques are used to increase the longevity and reliability of memory cells by adjusting a window of memory cell operation.

Abstract: An operation control method and apparatus are described. The apparatus includes a timer circuit, a blocking circuit and a control circuit. The timer circuit provides a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal. The blocking circuit receives the done signal and provides the done signal as output if the done signal is not blocked when received. The control circuit receives a begin signal indicating that the operation is to be performed and a limit signal to indicate whether or not a condition exists that would prevent the operation from being completed in a single step. If the limit signal indicates the operation can be completed in the single step, the control circuit starts the timing circuit and controls performance of the single step until the done signal is received.

Abstract: An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns.

Abstract: A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register, and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Abstract: A control gate is loaded with a negative voltage pulse and a source region is loaded with a positive constant voltage pulse while a drain region is at a floating state. More specifically, the absolute value of the voltage applied to the control gate is increased with time for a period from the start of a memory erasing action (the application of the pulse voltage) to 2 msec and then remains constant from 2 msec to the end of the memory erasing action. As the result, a potential difference between the source region and the control gate at the start of the memory erasing action is smaller than that at the end of the memory erasing action. This prevents the tunnel oxide layer from receiving a high electric field stress at the start of the memory erasing action, thus improving the write/erase endurance.

Abstract: An architecture for a mass storage system using flash memory is described. This architecture involves organizing the flash memory into a plurality of blocks. These blocks are then divided into several categories. One of the categories is a working category used to store data organized in accordance with a pre-defined addressing scheme (such as the logical block address used in Microsoft's operating system). The other category is a temporary buffer used to store data intended to be written to one of the working blocks. Another category contains blocks that need to be erased. When data is written into the mass storage system, a block in the second category is allocated from a block in the third category. The allocated block will then be changed to a block in the first category when writing to the allocated block is completed. The correspond block in the first category is placed into the third category. As a result, blocks can be recycled.

Abstract: A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operations before a bulk erase can take place. By eliminating the need to pre-program the memory array before each erasure, the process provides a signicant improvement for low power applications, because battery life is extended and write cycle time is enhanced.

Abstract: A standard single well (e.g., n-well) complementary metal-oxide-semiconductor (CMOS) process compatible voltage pump switch routes -10 Volt for erasing a floating gate transistor when an IC substrate is grounded at 0 Volts. The voltage pump switch also routes extreme positive voltages for programming or reading the floating gate transistor. P-channel field-effect transistors (PFETs) multiplex both the read/write/programming and erasing voltages, such as in a block-erasable flash electrically erasable and programmable read only memory (EEPROM). The voltage pump switch includes a charge pump for providing to the PFET routing the erasing voltage a gate voltage that is more negative than the erasing voltage by the PFET turn-on threshold voltage (V.sub.T) magnitude.

Abstract: In a method of initializing a flash EEPROM, a pre-programming operation of a predetermined data is first performed in a plurality of memory cells of a memory cell array and then an erasing operation is performed to the plurality of memory cells. Then, a verifying operation of whether the erasing operation is correctly performed is performed. During an initializing operation composed of the pre-programming operation, the erasing operation and the verifying operation, electrons or holes trapped in a tunnel oxide film are pulled out.

Abstract: A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit.

Abstract: Disclosed is a nonvolatile memory having lockable cell array. The memory includes a lockable cell array formed of a plurality of lockable cell transistors and lockable word lines coupled to gates of the lockable cell transistors; and a lockable pass transistor array formed of a plurality of lockable pass transistors connecting the lockable word lines to a plurality of selection signals. The lockable word lines are coupled to boosting elements which are in response to capacitive coupling in a bulk during an unlock operation.

Abstract: A flash memory with a high speed erasing structure includes a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline. A wordline decoder is coupled to the wordlines and configured to selectively apply voltages to the wordlines to perform procedures on the flash transistors, where the procedures include a read procedure, an erase procedure and a program procedure. During the erase procedure, the wordline decoder is configured to apply a first increasingly negative voltage in a first voltage range to at least one selected wordline until a first threshold voltage is met, then to apply a second increasingly negative voltage in a second voltage range to the selected wordline and to simultaneously apply a third negative voltage in a third voltage range to at least one deselected wordline.

Abstract: A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with each of the cells including a source region, a drain region, a channel region intermediate the drain and source region, a floating gate disposed over the channel region and a control gate disposed over the floating gate, with the cells located in one of the array columns having their drains connected to a common bit line and with the cells in one of the rows having their control gates connected to a common word line. The memory system includes a control circuit carrying out read, programming and erase operations. The erase operation is performed by applying a negative voltage to control gate of the cell being erased and a positive voltage to the source of the cells being erased.

Abstract: A nonvolatile memory cell (600) has a read device (510), program device (515), and tunnel diode (535). A write control line (WC) is directly coupled to the tunnel diode (535). The memory cell (500) may be used to form compact arrays of memory cells to store logical data. During programming of a selected memory cell, half-select voltages are used on the write control (WC) and control gate lines (CG) for unselected memory cells to prevent disturb and minimize oxide stress.

Abstract: A data writing circuit includes: a transfer gate (TG) selecting a bit line (BL0) of a virtually grounded cell array; a latch circuit (L) connected to the bit line (BL0) via the transfer gate (TG) for latching the data to be written, given to the bit line; a switching circuit (PM) which is connected between the bit line (BL0) and a program power source (VFROG) and is activated in accordance with the data to be written which has been latched by the latch circuit (L), to thereby supply the program power source (V.sub.PROG) to the bit line (BL0). This circuit, in accordance with the data to be written, sets the bit line (BL0) to which a memory cell (M) is connected, to a state of being applied by the program power source (V.sub.PROG) or a floating state.

Abstract: An IC memory device reduces the time required to complete operations for reading, writing, or erasing data continuously from the same sector address in plural memory chips by accomplishing said operations with a single command and sector address input operation. This IC memory device comprises a data control unit, a command control unit, and a serial clock signal generator. The data control unit handles command and data I/O operations between a data bus and the memory chips. The command control unit generates and applies a chip enable signal to each corresponding memory chip based on externally supplied command data. The serial clock signal generator generates an internal serial clock signal supplied to each memory chip based on an externally supplied serial clock signal. Data can thus be read, written, or erased continuously at the same sector address in plural memory chips with the operating command and sector address being input only once.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A four state programmable memory cell includes a substrate of a first conductivity type having a channel region having a first side and a second side, a control gate located on a first insulating layer above the channel region, a drain region of a second conductivity type located on the substrate adjacent to the first side of the channel region, a source region of a second conductivity type located on the substrate adjacent to the second side of the channel region, a first insulated floating gate located on a second insulating layer above the drain region adjacent to the control gate, and a second insulated floating gate located on a third insulating layer above the source region adjacent to the control gate.

Abstract: A method for detecting erroneously programmed memory cells of a memory, in particular for detecting overprogrammed memory cells of a flash semiconductor memory. The memory includes a plurality of memory cells, which can be subdivided into a number of blocks that can be erased as a unit, which in turn can be divided into a group of subblocks that can be programmed as a unit. The erroneous programming of a memory cell of a subblock causes each subblock of a number of subblocks that can be represented by an erroneously programmed subgroup to have a similarly erroneously programmed memory cell.

Abstract: A batch erasable single chip nonvolatile memory device and a method therefor of using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation) carries out, in sequence a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvo

Abstract: A current control circuit which controls currents flowing in memory cells in a non-volatile semiconductor memory device includes a circuit which controls the currents flowing in the memory cells in an erase operation so that amounts of the currents fall within a tolerable range.

Abstract: A memory chip has an on-board search engine adapted to accept programming from a system CPU and to perform a search for a search object or pattern independently of further action by the CPU, wherein the CPU is free to perform other tasks while a search of memory banks composed of two or more such chips takes place. In some embodiments the memory chip has a dedicated bus connection for programming by the system CPU and for reporting the results of a search. In some embodiments as well the on-board search engine has a dedicated on-board bus for communication with column amplifiers and decoders of memory cell arrays on the chip. CPU and memory combinations are disclosed and methods for practicing the invention.

Abstract: In a non-volatile semiconductor memory device, a memory cell array composed of a plurality of non-volatile memory cells is provided. Each word line is connected to a row of the memory cell array, and each bit line is connected to a column of the memory cell array. The memory cell array is divided into N blocks (N is an integer more than 1) in a row direction. A control signal generating section monitors erase operations to each of the N blocks to generate an erase operation history data for each of the N blocks and generates a control signal for each of the N blocks other than a selected block based on the erase operation history data for the corresponding block, when a write operation is performed to the selected block.

Abstract: A novel test procedure is used to determine the optimum programmable charge pump levels for a flash memory array in a CPLD. According to the method of the invention, an automated tester steps through all combinations of charge pump codes and attempts to program the flash memory with each combination of voltage levels. For each combination, the results of the test (pass or fail) are logged and stored into a map or array. The center of a window of passing pump codes is taken as the starting reference point. The next step is to verify the actual voltage level associated with the pump code combination corresponding to the starting reference point. The reference pump code is loaded into the device and the corresponding flash memory cell voltage levels are measured. If the measured voltage level does not fall into the preferred range, the tester automatically adjusts the level towards the preferred range by adjusting the pump codes.

Abstract: An architecture for a state machine used to control the data processing operations performed on the memory cells contained in a memory array. The architecture is designed to control the performance of the operations and sub-operations used to erase and program the memory array. The architecture of the present invention does not utilize separate state machines for each primary operation, but instead is based on a single state machine which is capable of controlling the various functions common to the data processing operations carried out on the memory cells. A sequencer which acts upon commands input from an external microprocessor is used to determine which set of sub-operations or functions needs to be performed to implement the commanded operation. The sequencer activates a timer which acts to trigger the functions controlled by a loop controller as they are needed for a particular operation.

Abstract: A nonvolatile semiconductor memory device using a NAND-type EEPROM includes a memory unit, a management unit, an erasure unit, and a control unit. The memory unit has a memory cell array divided into blocks each constituting a minimum quantity of data that may be erased. The management unit manages unused blocks. The erasure unit discriminates a erased blocks of the unused blocks from a non-erased blocks of the unused blocks to erase data stored in the non-erased blocks. The control unit writes data into at least one block of the unused blocks managed by the management unit. In the control unit, when a content of the written data is obtained by changing data recorded in a different block of the memory unit, and the data recorded in the different block is not necessary, the management unit receives information that the different block is an unused block.

Abstract: A memory card with block erasure-type nonvolatile memory units is connected to a host apparatus by an I/O interface. The memory includes a plurality of block-erasure type nonvolatile memory units, a control circuit for inputting/outputting data to the host apparatus and managing nonvolatile memory units and address data to the memory, and a programmable logic device which converts address data to select respective erasure blocks of nonvolatile memories in accordance with a program. The control circuit programs the programmable logic device so that the address data for selecting defective erasure blocks is converted to address data for selecting other usable erasure blocks.

Abstract: Electrically erasable and programmable non-volatile memory cell, which is formed with only one MOS transistor which is formed by a source-channel-drain junction, semi conductor substrate (1) of a first conductivity type has a drain region (2) and a source region (3) of a second conductivity type with a polarity opposite to that of the first conductivity type. A gate electrode (4), which is at a floating potential, is electrically insulated from the drain area (2) by a tunneling oxide (5) and from a channel region (9), which is located between the drain area and the source area (2, 3), by a gate oxide (5; 10). It and extends at least over a part of the channel region (9) and a part of the drain region (2) in the source-channel-drain direction. A control electrode (7) is electrically insulated from the gate electrode (4) by a coupling oxide (8).

Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse.

Abstract: An electrically alterable, non-volatile memory cell has more than 2 memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The programming signals include at least a first programming signal which programs the cell by a first increment and a subsequent programming signal which programs the cell by a second increment smaller than the first increment. As the cell is being programmed to a selected state, its programming status is verified independently of reference values bounding the memory states. For this purpose, a signal indicative of the programming status (e.g., the cell's bit line signal) is compared with a reference signal corresponding to the selected state but having a value different from the reference value or values bounding the selected state. The programming operation can thus be controlled without actually reading the memory state of the cell.

Abstract: In a nonvolatile semiconductor memory device including a memory cell array obtained by arranging, in a matrix manner, electrically programmable memory cells, each of which comprises stacking a charge storage layer and a control gate on a semiconductor layer through an insulating film, the threshold voltages of the memory cells are detected after erasing, and data are programmed in a fast programmable cell at a relatively low voltage and in a slow programmable cell at a relatively high voltage, thereby suppressing variations in threshold voltages after programming within the same period of programming time.

Abstract: Step S1 is carried out to lower, at the beginning of erasing operation, a voltage across a drain of a memory cell below a positive voltage applied to a source for erasing and then step S2 is carried out to open the drain. At the beginning of the erasing operation, step S3 is carried out to apply the positive voltage to the source and then step S3-1 is carried out to apply a negative voltage to a gate. To complete the erasing operation, step S4 is carried out to force the gate to be at the ground level and then the source to be at the ground level.

Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Abstract: A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses.

Abstract: A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

Abstract: When floating gate type memory transistors undesirably enter into an over-erased state, a diagnostic potential generator supplies a first diagnostic potential to a source line and second and third diagnostic potentials to non-selected word lines and a selected word line; the potential difference between the first diagnostic potential and the second diagnostic potential causes an over-erased memory transistor to be turned off, and the potential difference between the first diagnostic potential and the third diagnostic potential allows an over-erased memory transistor to turn on so as to identify each over-erased memory transistor by its row and column addresses.

Abstract: Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply.

Abstract: Integrated circuit memory devices include circuits that can perform erase operations on multiple blocks of data simultaneously using preferred addressing techniques. The memory device contains blocks of memory cells and local decoders that are responsive to predecoded block address signals and electrically coupled a respective one of the blocks. A block size modifying circuit is electrically coupled to the local decoders and is responsive to a block size data signal and a first block address signal. The modifying circuit enables the simultaneous erasure of multiple blocks of memory cells during an erase time interval by generating the predecoded block address signals to select multiple ones of the local decoders simultaneously.

Abstract: In a flash memory, a reading bit line and a writing bit line are provided corresponding to a respective column of memory cells. A well voltage and a voltage on a source line can be controlled for each sub-block. Accordingly, data can be read at a sub-block while data can be written/erased at another sub-block, and therefore, the capacity ratio of a back ground operation region to the main memory region can be changed as desired.

Abstract: A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. Included is a decoder circuit 16 having a plurality of input lines 94, 96, for each row in the array, and having as outputs the row lines 15. The decoder circuit includes a decoder logic circuit associated with each row line, the decoder logic circuit including a plurality of low power logic devices 84-90 interconnected to perform a predetermined decoding function on the signals on the input lines for the associated row line to apply a signal to an associated row node when the decoder logic circuit determines that the associated row line is selected.

Abstract: In a nonvolatile floating gate memory cell array, memory cells can become over-erased wherein their threshold voltage becomes near zero volts or even slightly negative. To correct over-erased cells and raise their threshold voltages to a normal level, a nonvolatile memory includes a control circuit for applying a programming voltage (approximately 5V) to the bit lines of the memory cell array and a lower voltage (approximately 2V) to the word lines of the memory cell array. The lower voltage is selected to be less than the threshold voltage (e.g., 3V) for a normal cell such that normal cells are not affected. However, the cells in an over-erased state will become active by the lower threshold voltage and begin conducting. A channel current flows to the over-erased memory cells and channel hot electrons induced by this channel flow into the floating gate of the memory cell raises the threshold voltage (VTM) of the memory cell to a normal level.

Abstract: A multi-block erase circuit in nonvolatile semiconductor memory device comprises a plurality of memory blocks composed of a plurality of memory cells formed on a semiconductor substrate, each memory cell composed of at least one memory transistor with a floating gate and a control gate, and a plurality of block selectors connected to the memory blocks to select the control gates of the memory transistors within a selected memory block and to erase the memory transistors during an erase operation, wherein each block selector has storing means for storing block selection flags to select the control gates of the memory transistors within at least one selected memory block during the erase operation and for storing reset flags to float the control gates of the memory transistors within the remaining unselected memory blocks, thereby erasing simultaneously only the memory transistors within the selected memory blocks during the erase operation.

Abstract: A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to remove charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a first relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a first moderately large positive voltage pulse to a first diffusion well. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float. The method to erase then proceeds with the source erasing to detrap the tunneling oxide of the flash EEPROM cell.

Abstract: A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses.

Abstract: A method for updating the content of EEPROM memory used for controlling processes run on a microprocessor used to control the operations of a long term memory array which includes moving an update process stored in the EEPROM memory to a random access memory associated with the microprocessor; and then using the update process stored in random access memory for erasing the contents of the EEPROM memory, and furnishing data to the microprocessor on a sector by sector basis from a host computer through an interface used by the microprocessor to provide data to the long term memory array. The data furnished by the host is written sector by sector to the EEPROM memory until the EEPROM memory has been updated.

Abstract: The present invention has a structure wherein a word line erasing voltage is inhibited from being applied to a sector (each word line) in which it is decided that erasure has been completed. Consequently, a method for controlling erasure of a nonvolatile semiconductor memory is provided in which distribution of a threshold can be tight without increasing a layout area so that a threshold of a reference cell for erasure can be lowered, read can be performed without boosting the word line by using a power supply having a low voltage, and high-speed read and low power consumption can thus be realized.

Abstract: The present invention provides method to erase flash EEPROMS devices using a positive sine waveform (Vs) and negative Vg that drives a cell in to snapback breakdown to remove trapped electron in the tunnel oxide and improve device performance. The snapback breakdown operation of one cell in the array lowers the tunnel oxide electric field for all cells in the array. The snapback breakdown generates a substrate current that reduces the electric field thereby reducing electron and hole trapping.