Abstract: A data storage device may include a storage including a plurality of storage regions each composed of a plurality of pages; and a controller. The controller is configured to select a plurality of target open regions from open regions among the storage regions on the basis of health information of the open regions, in each of which a programmed page and an unprogrammed page coexist, and perform control so that refresh operations for the respective target open regions are performed in a time-distributed manner.

Abstract: A row hammer control method and a memory device are provided. The memory device monitors the row hammer address(es) having the number of accesses equal to or more than a predetermined number of times or having a higher number of accesses as compared with other access addresses during the first row hammer monitoring time frame and malicious row hammer address(es) accessed at random sampling time points during the second row hammer monitoring time frame and being the same as the row hammer address(es), notifies a memory controller of the malicious row hammer address(es) when the number of malicious row hammer addresses exceeds a threshold value, and causes a target refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address(es) to be performed.

Abstract: Embodiments of the invention are directed to systems and methods for conducting a transaction utilizing a cryptocurrency. The user may fund a cryptocurrency account with his pre-existing cryptocurrency. An issuer may purchase cryptocurrency within a cryptocurrency exchange. The user may then utilize a payment device (e.g., a Crypto Debit Card) that is associated with a cryptocurrency balance to conduct a transaction with a merchant for goods and/or services. An authorization request message may be transmitted to the authorizing entity computer. The authorizing entity computer may determine a cryptocurrency amount corresponding to the fiat currency transaction amount of the authorization request message. A sell request message may be transmitted to an exchange that facilitates the sale of the cryptocurrency amount.

Abstract: A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

Abstract: Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a maintenance operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of operations at the memory location, to schedule a maintenance operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled maintenance operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further operations at the memory location until after the count has been decreased.

Abstract: Described systems, apparatuses, and methods relate to volatile memories that are refreshed to maintain data integrity, such as dynamic random-access memory (DRAM) and synchronous DRAM (SDRAM). A memory device includes multiple dies, with each die having a memory array to be refreshed. The multiple dies may be interconnected via at least one inter-die bus of the memory device. A memory controller sends a command to the memory device to enter a self-refresh mode. In response, a die of the multiple dies can enter the self-refresh mode and initiate or otherwise coordinate refresh operations of the other dies. To do so, the die may transmit at least one refresh-related command to at least one other die using the inter-die bus. Multiple different signaling schemes and timing approaches are disclosed. The described inter-die refresh control principles may be implemented in energy-efficient applications, such as in low-power double data rate (LPDDR) SDRAM.

Abstract: Provided is an operating method of a storage device. The method includes providing temperature information of each of a plurality of volatile memory devices in the storage device to a host device; and receiving a setting command related to a refresh operation of the plurality of volatile memory devices from the host device, wherein the plurality of volatile memory devices are classified into groups based on temperature information, and wherein the setting command indicates a number of rows of the plurality of volatile memory devices to be refreshed differently for each of the groups based on the temperature information.

Abstract: A memory system includes: a memory device suitable for providing row-hammer data to set refresh rates for adjacent word lines of a target word line, and performing a target refresh operation on one or more word lines corresponding to a first row-hammer address according to a first target refresh command; and a memory controller suitable for generating a plurality of sampling addresses by sampling an active address, generating a plurality of counting values by comparing the sampling addresses with the active address, calculating a plurality of adjacent addresses corresponding to the sampling addresses based on the counting values and the row-hammer data, and providing the adjacent addresses as the first row-hammer address with the first target refresh command.

Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.

Abstract: A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.

Abstract: An apparatus includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit which is configured to activate first and second internal signals in a time-division manner in response to a first external command A first number of the word lines arc selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal. The second number is smaller than the first number.

Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells.

Abstract: The present disclosure relates to the field of integrated circuit technologies, and provides a method and device for testing an SR cycle as well as a method and device for testing an AR number. The method for testing an SR cycle includes: executing a preset number of data-retention-capacity acquisition steps, the data-retention-capacity acquisition step including determining a preset refresh time; sending an SR entry command to control a memory to enter an SR operation; sending an SR exit command to control the memory to exit the SR operation after the memory executes the SR for the preset refresh time; detecting a current data retention capacity of the memory; obtaining a cycle of a function of the data retention capacity with respect to the corresponding preset refresh time; and determining the SR cycle of the memory with the cycle of the function.

Abstract: A method of operating a host device to control a storage device which includes a register is provided. The method includes: providing the storage device with a partial array refresh setting indicating a non-masking segment among a masking segment and the non-masking segment; providing a refresh command to the storage device; and providing a write command for the masking segment to the storage device to control the storage device to store data while a partial array refresh is performed in the storage device based on the refresh command.

Abstract: Methods, apparatuses, and systems related to operations for controlling direct refresh management (DRFM) operations. A memory may process a DRFM sample command using bank logic located downstream from a command decoder. The bank logic may be configured to process the DRFM sample command according to an operating state of a targeted memory bank.

Abstract: The disclosure provides a semiconductor storage element which is provided with an error detection and correction circuit and, when an uncorrectable error occurs in the semiconductor storage element, capable of promptly transferring the occurrence to the outside, and provides a semiconductor storage device and a system-on-chip using the same. The semiconductor storage element includes a storage part storing data, an error detection and correction part detecting an error in the data stored in the storage part and correcting the error if possible, a monitoring part issuing an uncorrectable error signal when an uncorrectable error occurs in the error detection and correction part, and a terminal transmitting the uncorrectable error signal to the outside.

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

Abstract: A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

Abstract: A method for refreshing row hammer includes the following operations. A row hammer refresh instruction for a target word line is determined. According to the row hammer refresh instruction, a preset row hammer refresh signal is set to a valid state. The valid state of the preset row hammer refresh signal indicates that the row hammer refresh instruction is performed in a first refresh period. In response to detecting that the row hammer refresh instruction is not completed within the first refresh period, the valid state of the preset row hammer refresh signal will be continued to a next refresh period of the first refresh period.

Abstract: A memory device includes a memory block and a peripheral circuit. The memory block includes a first word line group of word lines included in the memory block and a second word line group of the word lines included in the memory block. The word lines of the first word line group are different from the word lines of the second word line group. The peripheral circuit provides the first word line group and the second word line group with an equalizing voltage during an equalizing section overlapping an erase voltage discharging section for the memory block to constantly keep voltages of the first word line group and the second word line group to the equalizing voltage.

Abstract: Methods, systems, and devices for illegal operation reaction are described. A memory device may receive one or more commands to perform one or more respective access operations on an array of memory cells. A first circuit of the memory device may determine that the one or more commands would violate one or more thresholds associated with operation of the memory device, such as a timing threshold. In some cases, the first circuit may compare the one or more commands to the one or more patterns of commands stored at the memory device. A second circuit of the memory device may erase one or more memory cells of the memory device based on determining that the one or more thresholds associated with operation of the memory device would be violated, based on comparing the set of commands to the one or more patterns, or a combination thereof.

Abstract: A semiconductor memory apparatus includes an address generation circuit and an operation determination circuit. The address generation circuit generates a refresh target address that corresponds to a word line, among a plurality of word lines, the word line being adjacent to another word line in which row hammering has occurred. The operation determination circuit configured to generate an address matching information by comparing a row hammering address with the refresh target address.

Abstract: Apparatuses, systems, and methods for reset of row hammer detector circuits. A row hammer detector circuit includes a hash circuit configured to store a hash key and provide a first count value based on a hash between the hash key and a row address corresponding to a row of memory cells of a memory array. The row hammer detector circuit is configured to provide a match signal in response to the count value exceeding a threshold to cause a targeted refresh of a victim row adjacent the row of memory cells. In response to exit from a self-refresh mode, the hash circuit is configured to update the stored hash key with a new hash key.

Abstract: A refresh control circuit includes: a random output sub-circuit for sequentially receiving n single-row addresses and m single-row addresses in L single-row addresses, a single enabling duration of word lines pointed to by the n single-row addresses being greater than a preset duration, the m single-row addresses ranking top m in occurrence frequency, the L single-row addresses corresponding to word lines turned on between adjacent refresh commands, n being a natural number, and m being a positive integer; and for receiving a first random number which is a positive integer less than or equal to n+m, and then outputting an i-th received single-row address, i being equal to the first random number; and a row hammer address generation sub-circuit for outputting a row hammer address corresponding to the received single-row address acting as a refresh object corresponding to the refresh command.

Abstract: A refresh circuit includes: a refresh control module configured to receive a refresh command to output a row address refresh signal, the row address refresh signal being outputted a number of times of a preset value each time the refresh command is received; and further configured to receive a temperature signal to adjust the preset value, the higher a temperature represented by the temperature signal, the greater the adjusted preset value; a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh.

Abstract: A refresh circuit and a memory. The refresh circuit includes: a row hammer address generation module, configured to receive a row activate command, a precharge command, and a single row address corresponding to the row activate command, and output a row hammer address corresponding to the single row address, where each of the single row addresses corresponds to a word line, the row activate command is configured to activate a word line pointed to by the single row address, and the precharge command is configured to inactivate the word line; and output the row hammer address if a single activation time of the word line is greater than a preset time; and a signal selector, configured to receive the row hammer address and a regular refresh address, and at least output the row hammer address.

Abstract: A memory device includes memory cells connected to a first word-line, wherein the memory cells include a data region in which data is stored and a counting value backup region in which the number of times the first word-line is activated is backed up, a counting table for storing a first row address corresponding to the first word-line and a first counting value as a counting result of the number of times the first word-line is activated, and a comparator configured to compare the first counting value with a first backed-up counting value stored in the counting value backup region; and when the first counting value is greater than the first backed-up counting value, back up the first counting value in the counting value backup region, or when the first backed-up counting value is greater than the first counting value, overwrite the first backed-up counting value into the counting table.

Abstract: In a method of operating a memory device, a first command to allow the memory device to enter an idle mode is received. A reference time interval is adjusted based on process, voltage and temperature (PVT) variation associated with the memory device. The reference time interval is used to determine a start time point of a power control operation for reducing power consumption of the memory device. A first time interval during which the idle mode is maintained is internally measured based on the first command. The power control operation is performed in response to the first time interval being longer than the reference time interval.

Abstract: A memory core including a memory core including memory cells that are arranged in a plurality of rows and a plurality of columns; and a refresh target selection circuit suitable for storing an address and a risk score of each of activated rows among the rows, wherein the refresh target selection circuit is further suitable for increasing the risk score of a corresponding row whenever the corresponding row is activated, whenever a row at a ‘+2’ position of the corresponding row is activated, and whenever a row at a ‘?2’ position of the corresponding row is activated.

Abstract: A method and device for testing a memory array structure, and a non-transitory storage medium are provided. The method includes that: respective storage data corresponding to each preset test pattern is written into a to-be-tested memory array, the each preset test pattern being one of preset test patterns in a preset test pattern library; a row aggressing test is repeatedly performed on the to-be-tested memory array until a bit error occurs in the storage data, to obtain row aggressing test times, corresponding to the each preset test pattern, of the to-be-tested memory array, where the bit error characterizes that the storage data has changed; a target preset test pattern corresponding to the to-be-tested memory array is determined from the preset test pattern library based on the row aggressing test times; and an array structure of the to-be-tested memory array is determined based on the target preset test pattern.

Abstract: Embodiments of the present application provide a refresh circuit and a memory. The refresh circuit includes: a refresh control module configured to receive and execute a refresh command to output a row address refresh signal; and further configured to receive a process corner signal to adjust an execution proportion of the refresh command, the faster a process corner represented by the process corner signal, the higher the adjusted execution proportion; a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh. The embodiments of the present application help reduce the consumption of refresh currents.

Abstract: A semiconductor memory device is provided. The semiconductor memory device can suppress increases in power consumption. As a result, damage to the data normally caused by row problems can be prevented. The semiconductor memory device includes a control unit. The control unit controls the time interval for refreshing the memory. If the frequency of a read/write access requirement to the memory during a predetermined period is higher, then the control unit shortens the interval between memory refresh operations.

Abstract: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM), and an associated host device are described. The memory device includes control circuitry that can determine an operational status of the memory device (e.g., whether the memory device is currently performing a self-refresh operation). The control circuitry can also transmit a signal indicative of the operational status to the host device in response to receiving a command directing the memory device to exit a self-refresh mode. The host device can operate based on the signal. The signal may therefore allow the memory device, the host device, or both to manage operations, including whether to send, receive, or process commands and data read/write requests during times that may be associated with self-refresh operations.

Abstract: Apparatuses, systems, and methods for direct refresh management (DRFM) commands. A controller provides a DRFM command to a memory along with a row address. A command decoder of the memory provides an activate command and then a pre-charge command along a signal line to a bank. During a tRP time after the pre-charge command before a next activate command, a DRFM sampling command is provided along the signal line which causes the address to be latched in a DRFM latch. Responsive to a later DRFM service command, one or more wordlines based on the address in the DRFM latch are refreshed.

Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.

Abstract: A device is provided that includes a first memory and a second memory and an accessing circuit. Actual addresses of the first memory and the second memory alternately correspond to reference addresses of a processing circuit. The accessing circuit is configured to perform the steps outlined below. A read command corresponding to a reference read address is received from the processing circuit to convert the reference read address to an actual read address of the first memory and the second memory. A first read data is read from a first one of the first memory and the second memory according to the actual read address and a second read data is prefetched from a second one of the first memory and a second memory according to a next first read address simultaneously.

Abstract: A memory system includes a memory module and a memory controller. The memory module includes data chips that store data and are assigned to a first sub-channel that generates a first code word or a second sub-channel that generates a second code word, where the first code word and the second code are used to fill a single cache line. The memory controller, upon detection of a hard-fail data chip among the data chips, copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding I/O, and defines new mapping between the ECC chip and the corresponding I/O pins.

Abstract: A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell may be determined to a higher bit resolution than a data read value. A write condition may be selected for the RRAM cell, based on the cell characteristic. The RRAM cell may be written to, using the selected write condition.

Abstract: A refresh circuit includes: a signal generation module, configured to generate an inversion signal and a carry signal based on a refresh command; an adjustment unit, configured to generate, if a first refresh signal and a second refresh signal are generated based on the refresh command, an inversion adjustment signal according to the inversion signal, and generate, if only the first refresh signal is generated based on the refresh command, the inversion adjustment signal according to an inversion signal corresponding to a first refresh signal generated based on a current refresh command, and generate the inversion adjustment signal only according to an inversion signal corresponding to a second refresh signal generated based on a next refresh command; and a counting module, configured to generate a first output signal and a second output signal, and invert the first output signal based on the inversion adjustment signal.

Abstract: A refresh circuit includes signal selector configured to select one of normal and redundant word line logical addresses as output, output signal of which is designated as first logical address; row address latch connected to output terminal of signal selector and configured to output row hammer address and row hammer flag signal according to first logical address; seed arithmetic unit connected to output terminal of row address latch and configured to generate seed address according to row hammer address; logical arithmetic unit connected to output terminal of seed arithmetic unit and configured to obtain row hammer refresh address according to seed address, row hammer refresh address is adjacent physical address of seed address; and pre-decode unit connected to output terminal of logical arithmetic unit and configured to receive row hammer refresh address, and convert it into physical address to be used by memory array of memory to perform refresh operation.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic targeted refresh steals. A memory bank may receive access commands and then periodically enter a refresh mode, where auto refresh operations and targeted refresh operations are performed. The memory bank may receive a refresh management command based on a count of access commands directed to the memory bank. Responsive to the refresh management signal, a panic targeted refresh operation may be performed on the memory bank. A number of times the refresh management signal was issued may be counted, and based on that count a next periodic targeted refresh operation may be skipped.

Abstract: Embodiments of the present application provide a method and apparatus for determining a refresh counter of a DRAM. The method includes: writing data to a target memory cell connected with a target word line in the DRAM, and controlling the DRAM to perform refreshes starting from a preset word line according to a preset rule; determining, according to whether the data can be read accurately from the target memory cell after the refreshes, an intermediate refresh counter of refreshes on the target word line; and controlling, based on the intermediate refresh counter, the DRAM to perform refreshes starting from the target word line according to the preset rule, and determining the refresh counter of the DRAM according to whether the data can be read accurately from the target memory cell after the refreshes.

Abstract: A storage device may include: a memory device including a temperature sensor; and a memory controller for acquiring, from the memory device, temperature information sensed by the temperature sensor for a temperature management period, performing a performance limiting operation of limiting the performance of the memory device according to the temperature information, calculating the temperature management period by using the temperature information, and updating the temperature management period by using history information on a performance history of the performance limiting operation.

Abstract: Apparatuses, systems, and methods for main sketch and slim sketch circuits for address tracking. The main sketch circuit receives a row address and changes selected count values in a first storage structure based on hash values generated based on the row address. Those count values are compared to a first threshold, and if that threshold is exceeded, a slim sketch circuit also receives the row address and changes selected count values in a second storage structure based on hash values generated based on the row address. Based on the selected count values from the first storage structure, the second storage structure, or combinations thereof, the row address may be determined to be an aggressor address.

Abstract: A dynamic random-access memory array includes a plurality of memory cells and sensor cells physical arranged in a row. The sensor cells include a transistor and a capacitor having an input terminal connected to a first non-gate terminal of the transistor. A wordline is connected to transistor gates of both the memory cells and sensor cells in the row. A sensor amplifier has inputs connected to the sensor cell, a high voltage reference line, and a low voltage reference line, and an output in communication with a row refresh circuit. If the sensor amplifier detects that the sensor cell voltage falls outside of the range of the high and low voltage reference lines, then a trigger signal is output to request that the row refresh circuit perform a priority row refresh of the memory cells and the sensor cell in the row.