Data Refresh Patents (Class 365/222)
  • Patent number: 11222686
    Abstract: Refresh commands may be provided at random intervals from a memory controller to a memory device. In some examples, refresh requests may be provided at random intervals which may be used to provide refresh commands from the memory controller to the memory device at random intervals. In some examples, an average time interval between refresh requests may be equal to a refresh interval of the memory device. In some examples, a maximum number of times the memory controller may postpone providing a refresh command to the memory device may be a random number. In some examples, a maximum value of the random number may be based, at least in part, on a minimum number of refresh commands required within a time interval by the memory device.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Hidekazu Noguchi
  • Patent number: 11217284
    Abstract: Memory devices and systems with per pin input/output termination and driver impedance calibration capabilities, and associated methods, are disclosed herein. In one embodiment, a device apparatus includes circuitry dedicated to an individual DQ pin of the device apparatus. The circuitry can be configured to (i) generate, at least in part, a voltage at the DQ pin based, at least in part, on an impedance internal to a host device electrically connected to the device apparatus and (ii) compare the voltage to a target voltage. Based, at least in part, on the comparison, the circuitry can be configured to adjust a resistance of an output driver and/or a termination circuit of the device apparatus that correspond to the DQ pin to adjust the impedance of the output driver and/or termination circuit to match an impedance associated with a corresponding input/output pin of the host device.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Eric J. Stave
  • Patent number: 11205482
    Abstract: A semiconductor storage device includes a plurality of memory cells connected to each other in series, a plurality of word lines respectively connected to gates of the plurality of memory cells, and a control circuit configured to perform a read operation by applying a first voltage higher than ground voltage to the plurality of word lines during a first time period at the beginning of which each word line is at ground voltage, applying a second voltage lower than the first voltage to a first word line during a second time period subsequent to the first time period, applying a third voltage higher than the second voltage to the first word line during a third time period subsequent to the second time period, and determining data of the memory cells connected to the first word line while all portions of the first word line are at the third voltage.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: December 21, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Takeshi Hioka, Koji Kato
  • Patent number: 11195568
    Abstract: Methods and systems for controlling refresh operations of a memory device. A method disclosed herein includes receiving, by a refresh controller of the memory device, a refresh command from a host for performing the refresh operation on a plurality of memory rows. The method further includes selecting, by the refresh controller, at least one memory row from the plurality of memory rows for the refresh operation using a refresh-row selection circuitry. The at least one memory row is selected by performing digital reading or analog reading of at least one row condition cell (RCC) and at least one supplemental cell that are connected to each memory row of the memory rows. The method further includes performing, by the refresh controller, the refresh operation on the selected at least one memory row.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: December 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Atishay, Anirudh B K, Rajeev Verma, Vishnu Charan Thummala
  • Patent number: 11163488
    Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
  • Patent number: 11159155
    Abstract: A chip includes a level control circuit, an output circuit, a level supply circuit, and an output terminal. The level control circuit is configured to output a response signal in response to an operation mode of the chip. The output circuit has an output side, and the output side couples to the output terminal. When the operation mode of the chip is a working mode, the response signal is at a first level, and the output circuit is configured to output an output signal at the output terminal. When the operation mode of the chip is a power saving mode, the response signal is at a second level, the output side of the output circuit is in a floating state, and the level supply circuit is configured to provide a level voltage to the output terminal according to the response signal, so that the output terminal has a fixed level.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: October 26, 2021
    Assignee: REALTEK SINGAPORE PRIVATE LIMITED
    Inventors: Yunhua Shi, Jyun-Ren Chen
  • Patent number: 11152078
    Abstract: Embodiments of the disclosure are drawn to apparatuses methods for checking redundancy information for row addresses prior to performing various refresh operations, such as auto refresh and targeted refresh operations. In some examples, refresh operations may be multi pump refresh operations. In some examples, a targeted refresh operation may be performed prior to an auto refresh operation responsive to a multi pump refresh operation. In some examples, redundancy information for the auto refresh operation may be performed, at least in part, during the targeted refresh operation. In some examples, refresh operations on word lines may be skipped when the redundancy information indicates the word line is defective or unused.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bin Du, Liang Li, Yu Zhang, Yin Lu
  • Patent number: 11151265
    Abstract: Aspects of the present invention disclose a method for securely storing data. The method includes one or more computer processors receiving, by one or more computer processors, a request to store data, wherein the data includes a plurality of elements. The method further includes generating a plurality of elements of encoded data by on applying one or more encoding algorithms to the data, wherein a quantity of the plurality of elements of the encoded data is equal to a quantity of the plurality of elements of the data. The method further includes distributing the plurality of elements of the encoded data into two or more subsets of the encoded data, without duplication. The method further includes transmitting the two or more subsets of the encoded data to a corresponding quantity of two or more storage systems.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Georges-Henri Moll, Oliver Oudot, Philippe Kaplan, Xavier Nodet
  • Patent number: 11152053
    Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: October 19, 2021
    Inventors: Sang-Hyuk Kwon, Nam Sung Kim, Kyomin Sohn, Seongil O, Haesuk Lee
  • Patent number: 11145351
    Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit is configured to generate an ECS command by controlling a speed of a first counting operation that is performed based on a refresh command or a bank refresh command, according to a temperature and a refresh mode of the semiconductor device, or is configured to generate the ECS command by performing a second counting operation based on a periodic signal. The ECS control circuit is configured to sequentially generate an ECS active command, an ECS read command, an ECS write command, an ECS pre-charge command, and an end signal based on the ECS command. The refresh mode includes a fine granularity refresh (FGR) mode, and the temperature includes a high temperature that is a temperature above a certain temperature.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventors: Jung Ho Lim, Byeong Chan Choi
  • Patent number: 11145356
    Abstract: A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: October 12, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Fu-Cheng Tsai, Heng-Yuan Lee, Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou
  • Patent number: 11132142
    Abstract: A memory device may include a first wordline and a second wordline, each having multiple memory cells. The memory device may also include control circuitry to facilitate writing a data pattern to the memory cells of the first wordline and facilitate copying the data pattern from the first wordline to the second wordline. Copying the first wordline to the second wordline may include activating the second wordline such that the first wordline and the second wordline are simultaneously active. A memory cell of the first wordline may be written a data value of the data pattern, and the memory cell may drive, at least partially, a corresponding memory cell of the second wordline with the data value.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Byung S. Moon, Harish N. Venkata, Gary L. Howe, Myung Ho Bae
  • Patent number: 11133050
    Abstract: A memory device applies different refresh rates to target data (or objective data) according to data characteristics (i.e., required reliability levels). The memory device includes a memory cell array provided with a plurality of memory cells, a row decoder configured to selectively activate word lines of the memory cell array in response to a row address signal, and a refresh controller configured to output the row address signal in response to the row address signal. The refresh controller controls a refresh ratio of a first storage region and a second storage region contained in the memory cell array in response to a changeable refresh control value.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: September 28, 2021
    Assignee: SK hynix Inc.
    Inventor: Ho Sung Cho
  • Patent number: 11120860
    Abstract: Methods of operating a number of memory devices are disclosed. A method may include adjusting a count of a refresh address counter of at least one memory device of a number of memory devices such that the count of the refresh address counter of the at least one memory device is offset from a count of a refresh address counter of at least one other memory device of the number of memory devices. The method may also include receiving, at each of the number of memory devices, a refresh command. Further, the method may include refreshing, at each of the number of memory devices, a row of memory cells indicated by the count of an associated refresh address counter. Related systems and memory modules are also described.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, James S. Rehmeyer
  • Patent number: 11107517
    Abstract: A semiconductor memory device includes: a plurality of banks each suitable for refreshing at least one word line corresponding to a refresh address according to a row active signal; a refresh control circuit suitable for controlling, in response to a refresh command, an activation timing of the row active signal according to mode signals and a counting signal; a refresh counter suitable for generating the counting signal by counting the number of times the row active signal is activated, and generating sequence signals which are sequentially activated; and a detection circuit suitable for generating flag signals by combining the sequence signals, and generating a detection signal according to a corresponding one of the flag signals when any of the mode signals is activated, wherein the refresh counter is initialized by the detection signal.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventor: Kyung-Mook Kim
  • Patent number: 11107510
    Abstract: Apparatuses and methods related to memory bank power coordination in a memory device are disclosed. A method for memory bank power coordination may include concurrently performing a memory operation by a threshold number of memory regions, such as banks or subarrays, and executing a command to cause a budget area, such as a register, to perform a power budget operation associated with the memory operation. The threshold number of memory regions may be set based at least in part on a threshold power consumption value, and the number of memory regions to concurrently perform an operation may be controlled by a bank arbiter. A counter having a value representing the threshold number of memory regions may be decremented while performing an operation or incremented upon completion of an operation associated with one of the memory regions. A number of the memory regions may be selected to perform a processing-in-memory operation.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kelley D. Dobelstein, Jason T. Zawodny, Kyle B. Wheeler
  • Patent number: 11100974
    Abstract: A system includes first and second sets of memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address input circuit coupled to the address path. The command address input circuit includes a counter that stores and increments the row address. The system also includes a flip-flop that stores the row address in response to receiving a command to refresh the first set of memory banks.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Joosang Lee
  • Patent number: 11101281
    Abstract: The semiconductor device includes a fin FA selectively protruded from an upper surface of a semiconductor substrate SB, a gate insulating film GF1 formed on an upper surface and a side surface of the fin FA and having an insulating film X1 and a charge storage layer CSL, and a memory gate electrode MG formed on the gate insulating film GF1. Here, the thickness of the charge storage layer CSL on the upper surface of the fin FA is larger than the thickness of the charge storage layer CSL on the side surface of the fin FA.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: August 24, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shibun Tsuda
  • Patent number: 11100013
    Abstract: A memory system includes a memory circuit including a plurality of pages, including a particular page having a page activation time. The memory system also includes a memory controller circuit configured to receive a memory access request corresponding to data of the particular page. The memory controller circuit is also configured to transmit, in response to a determination that the particular page is inactive, an activation command to the memory circuit to activate the particular page, and to schedule a future transmission of an initial memory command for the particular page based on the page activation time.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 24, 2021
    Assignee: Apple Inc.
    Inventor: Shane J. Keil
  • Patent number: 11094384
    Abstract: A sensing circuit includes a current generating circuit and a sensing circuit. The current generating circuit includes a first portion configured to generate a first mirrored current corresponding to a first reference cell programmed to a low logical value, a second portion configured to generate a second mirrored current corresponding to a second reference cell programmed to a high logical value, and a transistor configured to generate a reference voltage by conducting a first reference current equal to a sum of the first mirrored current and the second mirrored current. The sensing circuit includes a sense amplifier configured to generate an output voltage having a logical value based on a second reference current and a cell current of a memory cell, the second reference current being generated from the reference voltage.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Tien-Chun Yang
  • Patent number: 11094369
    Abstract: A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits, each of the plurality of address storing circuits suitable for storing a sampling address as a latch address, a valid bit indicating whether the latch address is valid, and a valid-lock bit indicating whether the latch address is accessed more than a certain number of times, each of the plurality of address storing circuits further suitable for outputting the latch address as a target address according to the valid bit and valid-lock bit; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to a refresh command.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventors: Nogeun Joo, Jungho Lim, Byeongchan Choi, Jeongtae Hwang
  • Patent number: 11087821
    Abstract: A memory module includes a plurality of memory devices each including a memory cell array, and a register clock driver connected to the memory devices. The register clock driver detects a row hammer address among row addresses corresponding to word lines of the memory cell array, converts a refresh command, among a plurality of refresh commands received from a memory controller for refreshing the memory cell array, to a row hammer refresh command, and transmits the row hammer refresh command and the row hammer address to each of the memory devices.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongpil Son, Wooyeong Cho
  • Patent number: 11086566
    Abstract: In a storage device having an improved data receiving rate, the storage device includes: a plurality of memory devices each including a plurality of select signal pads; and a memory controller for providing a plurality of select signals representing a selected memory device among the plurality of memory devices through the plurality of select signal pads, wherein some select signals among the plurality of select signals include stack information indicating a number of the plurality of memory devices controlled by the memory controller.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: August 10, 2021
    Assignee: SK hynix Inc.
    Inventors: Jin Yong Seong, Jun Sang Lee
  • Patent number: 11079784
    Abstract: A power management integrated circuit (PMIC) includes a voltage regulator, a monitoring circuit, and a count register. The voltage regulator is configured to generate an output voltage. The monitoring circuit is configured to receive a feedback voltage of the output voltage, and to determine at each of periodic intervals whether the feedback voltage is outside a threshold voltage range. The count register is configured to store a count value indicative of a number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 3, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinseong Yun, Kyudong Lee, Jaejun Lee
  • Patent number: 11081191
    Abstract: A device, for example a memory system, is disclosed wherein two or more operational modes may be set. The clock toggle rate and ODT resistors are dynamically controlled based on one or more of a desired margin of signal integrity, performance, cooling rate, and power consumption.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 3, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yoseph Hassan, Shay Benisty
  • Patent number: 11074578
    Abstract: Described herein are systems and methods in which more secure methods are provided for a connected device to conduct transactions. In accordance with embodiments of the disclosure, a transaction code is generated and provided to the connected device. The transaction code may be stored in association with the information for the transaction such that when the transaction code is received at a transaction processing server, the transaction processing server is configured to generate an authorization request that includes the transaction information. The authorization request may then be routed to an authorization server associated with an account maintained by the transaction processing server.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: July 27, 2021
    Assignee: Visa International Service Association
    Inventors: Krishna Prasad Koganti, Mark Douglas McGee, David Tseselsky, Brendan Xavier Louis
  • Patent number: 11068200
    Abstract: Methods and systems are provided for improving memory control. A memory architecture includes a plurality of memory units and an interface. A respective memory unit of the plurality of memory units is configured with a Processing-In-Memory (PIM) architecture. The interface includes a plurality of lines. The interface is coupled between the plurality of memory units and a host. The interface is configured to receive one or more signals from a host via the plurality of lines. The respective memory unit of the plurality of memory units is coupled with a respective line of the plurality of lines, and the respective memory unit is further configured to receive a respective signal of the one or more signals via the interface so as to be individually selected by the host.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: July 20, 2021
    Assignee: Alibaba Group Holding Limited
    Inventors: Dimin Niu, Lide Duan, Yuhao Wang, Xiaoxin Fan, Zhibin Xiao
  • Patent number: 11062768
    Abstract: A semiconductor memory apparatus may include a memory bank, a global buffer array, and an input and output circuit. The memory bank includes a local data circuit, and the global buffer array includes a global data circuit. The local data circuit is operably coupled to the global data circuit. The global buffer array may be operably coupled to the input and output circuit. The memory bank is disposed in a core region, and the global buffer array and the input and output circuit may be disposed in a peripheral region separated from the core region.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Dong Keun Kim
  • Patent number: 11054995
    Abstract: Methods, systems, and devices for row hammer protection for a memory device are described. A memory device may identify a threshold of related row accesses (e.g., access commands or activates to a same row address or a row address space) for a memory array. In a first operation mode, the memory device may execute commands received from a host device on the memory array. The memory device may determine that a metric of the received row access commands satisfies the threshold of related row accesses. The memory device may switch the memory array from the first operation mode to a second operation mode based on satisfying the threshold. The second operation mode may restrict access to at least one row of the memory, while the first mode may be less restrictive. Additionally or alternatively, the memory device may notify the host device that the metric has satisfied the threshold.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11055235
    Abstract: A storage cell includes a selection circuit, a first memory transistor, and a second memory transistor. The selection circuit is coupled to a source line and a common node. When the selection circuit is turned on, the selection circuit forms an electrical connection between the source line and the common node. The first memory transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a control terminal coupled to a control line. The second memory transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a control terminal coupled to the control line. The first memory transistor and the second memory transistor are 2-dimension charge-trapping devices or 3-dimension charge-trapping devices.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 6, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Wein-Town Sun, Ching-Hsiang Hsu
  • Patent number: 11056167
    Abstract: Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of defective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Yoshifumi Mochida, Hiroei Araki
  • Patent number: 11055022
    Abstract: A storage system and method are provided for early host command fetching in a low queue depth environment. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: determine a host's behavior for updating a submission queue; begin executing at least one command based on the determined host's behavior before receiving notification from the host that the host has updated the submission queue; receive notification from the host that the host has updated the submission queue; determine whether the submission queue has been updated with the at least one command that the controller began executing; and in response to determining that the submission queue has been updated with the at least one command that the controller began executing, continue executing the at least one command.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 6, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11049545
    Abstract: Methods of operating a memory device are disclosed. A method may include determining a number of active commands associated with at least one memory bank of a memory device during a first time interval. The method may further include adjusting a row hammer refresh rate for the at least one memory bank for a second time interval based on the number of active commands associated with the at least one memory bank during the first time interval. A memory device and an electronic system are also described.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Joo-Sang Lee
  • Patent number: 11042325
    Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 22, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jie Zheng, Steven R. Carlough, William J. Starke, Jeffrey A. Stuecheli, Stephen J. Powell
  • Patent number: 11043259
    Abstract: According to various embodiments, an in-memory computation system is disclosed. The system includes a dynamic random access memory (DRAM) module. The system further includes a memory controller configured to violate a timing specification for the DRAM module and activate multiple rows of the DRAM module in rapid succession to enable bit-line charge sharing.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: June 22, 2021
    Assignee: THE TRUSTEES OF PRINCETON UNIVERSITY
    Inventors: David Wentzlaff, Fei Gao, Georgios Tziantzioulis
  • Patent number: 11037616
    Abstract: A system for refresh operations in semiconductor memories, and an apparatus and method therefore, are described. The system includes, for example, memory cells in memory banks that are refreshed during a self-refresh operation or an auto refresh operation. The self-refresh operation includes a different number of refresh activations than the auto refresh operation. The system further includes a row control circuit configured to refresh the memory cells in the memory banks based on refresh control signals received from a refresh control circuit, the refresh control signals provided by the refresh control circuit based on internal control signals received by the refresh control circuit from a command control circuit. The auto refresh operation includes a per bank refresh operation configured to refresh a corresponding memory bank or an all-bank refresh operation configured to refresh all memory banks.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Toru Ishikawa, Shinji Bessho, Takuya Nakanishi
  • Patent number: 11037615
    Abstract: A refresh processing method, apparatus, and system, and memory controllers are provided, to improve memory access efficiency. The refresh processing apparatus includes a plurality of memory controllers that are in one-to-one correspondence with a plurality of memory spaces. Any first memory controller in the plurality of memory controllers is configured to: receive N first indication signals and N second indication signals that are output by N memory controllers other than the first memory controller, where N is greater than or equal to 1; and determine a refresh policy of a first memory space based on at least one of the following information: the N first indication signals, the N second indication signals, and refresh indication information of the first memory space.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: June 15, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hengchao Xin, Jing Xia, Yining Li, Zhenxi Tu
  • Patent number: 11031066
    Abstract: Methods of operating a memory device are disclosed. A method may include determining an operating temperature of a memory bank of a memory device. The method may also include adjusting at least one refresh interval for the memory bank based on the operating temperature of the memory bank. Further, the method may include skipping at least one refresh of the memory bank based on at least one of the operation temperature of the memory bank and a number of active signals received at the memory bank. A memory device and an electronic system are also described.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Yutaka Ito
  • Patent number: 11031065
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
  • Patent number: 11024359
    Abstract: A memory device may include a cell array and a cycle calculating circuit. The cycle calculating circuit may calculate an operating cycle of a refresh operation to be performed at the cell array, based on an operating temperature of the memory device. In response to the operating temperature being lower than a first temperature, the cycle calculating circuit may be configured to calculate the operating cycle by integrating one or more slope values of a second slope value to an nth slope value that are arranged from a highest temperature to a lowest temperature. The second slope value may correspond to a second temperature, the nth slope value may correspond to an nth temperature, n may be a natural number of 2 or more, and a number of the one or more slope values may be based on the operating temperature.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: June 1, 2021
    Inventor: Minsang Park
  • Patent number: 11024383
    Abstract: The memory controller controls a memory device. The controller is configured to determine to perform a target operation on a first memory block and determine an activation voltage level transferred to a block word line based on block state information of a second memory block.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: June 1, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Ho Her, Dong Hyun Kim, Seung Il Kim, Youn Ho Jung
  • Patent number: 11024397
    Abstract: A nonvolatile memory device is provided. A nonvolatile memory device comprises a word line, a bit line, a memory cell array including a first memory cell at an intersection region between the word line and the bit line, a word line voltage generating circuitry configured to generate a program voltage, the program voltage to be provided to the word line, a row decoder circuitry configured to receive the program voltage from the word line voltage generating circuitry and configured to provide the program voltage to the word line, a verification circuitry configured to generate a verification signal in response to verifying a success or a failure of programming of the first memory cell, and a control circuitry configured to apply the program voltage to the first memory cell in response to the verification signal, and configured to cut off the program voltage in response to the verification signal.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: June 1, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seul Bee Lee, Dong Hun Kwak, Jong-Chul Park
  • Patent number: 11016811
    Abstract: The present disclosure includes apparatuses and methods to determine timing of operations. An example method includes performing a first operation type that uses a shared resource in a memory device. The method includes applying a scheduling policy for timing of continued performance of the first operation type based upon receipt of a request to the memory device for performance of a second operation type that uses the shared resource.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jeremiah J. Willcock
  • Patent number: 11017833
    Abstract: Apparatuses and methods for pure-time, self-adopt sampling for RHR refresh. An example apparatus includes a memory bank comprising a plurality of rows each associated with a respective row address, and a sampling timing generator circuit configured to provide a timing signal having a plurality of pulses. Each of the plurality of pulses is configured to initiate sampling of a respective row address associated with a row of the plurality of rows to detect a row hammer attack. The sampling timing generator includes first circuitry configured to provide a first subset of pulses of the plurality of pulses during a first time period and includes second circuitry configured to initiate provision of a second subset of pulses of the plurality of pulses during a second time period after the first time period.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jun Wu, Dong Pan
  • Patent number: 11011110
    Abstract: An information handling system organic light emitting diode (OLED) display adapts presentation of visual information to manage a display thermal state, such as to maintain a uniform thermal condition. In one example embodiment, a first display zone of plural pixels presents visual images with a first refresh rate, such as the nominal refresh rate established by the display settings, and a second display zone presents visual images with a partial pixel refresh rate that reduces power dissipation and, thus, thermal energy release so that a more uniform thermal state may be achieved at the display.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: May 18, 2021
    Assignee: Dell Products L.P.
    Inventors: Jong Seo Lee, Deeder M. Aurongzeb, Asim M. Siddiqui
  • Patent number: 11011218
    Abstract: A system for refresh operations including multiple refresh activations, and a method and an apparatus therefore, are described. The system includes, for example, a memory array; a command address input circuit configured to provide a command for a per bank refresh operation or an all-bank refresh operation, a command control circuit configured to receive the command, and provide first and second internal control signals; a refresh control circuit configured to provide a first refresh control signal; and a row control circuit configured to provide a second refresh control signal. The provided first internal control signal is based on the provided command. For the per bank refresh operation, the provided second internal control signal is based on the second refresh control signal, and, for the all-bank refresh operation, the provided second internal control signal is based on the first internal control signal delayed by the command control circuit.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shinji Bessho, Toru Ishikawa, Takuya Nakanishi
  • Patent number: 11004497
    Abstract: Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: George B. Raad, Jonathan S. Parry, James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10990477
    Abstract: A method for controlling the refresh of data in reprogrammable nonvolatile memories includes a plurality of memory pages for storing data.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: April 27, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Valentin Gherman
  • Patent number: 10990740
    Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: April 27, 2021
    Inventors: Jin-Tae Kim, Sung-We Cho, Tae-Joong Song, Seung-Young Lee, Jin-Young Lim
  • Patent number: 10991879
    Abstract: A phase change memory cell includes a first electrode, a second electrode located over the first electrode, a vertical pillar structure located between the first and second electrodes, the pillar structure containing a first phase change memory (PCM) material portion, a second PCM material portion and an intermediate electrode located between the first PCM material portion and the second PCM material portion, and a resistive liner containing a first segment electrically connected in parallel to the first PCM material portion between the first electrode and the intermediate electrode, and a second segment electrically connected in parallel to the second PCM material portion between the intermediate electrode and the second electrode. The first PCM material portion has a different electrical resistance than the second PCM material portion, and the first segment of the resistive liner has a different electrical resistance than the second segment of the resistive liner.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 27, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ricardo Ruiz, Lei Wan, John Read, Zhaoqiang Bai, Mac Apodaca