Data Refresh Patents (Class 365/222)
  • Patent number: 11908508
    Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: February 20, 2024
    Inventors: Dale H. Hiscock, Debra M. Bell, Michael Kaminski, Joshua E. Alzheimer, Anthony D. Veches, James S. Rehmeyer
  • Patent number: 11901026
    Abstract: A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: February 13, 2024
    Assignee: NeuroBlade Ltd.
    Inventors: Elad Sity, Eliad Hillel
  • Patent number: 11894042
    Abstract: A method for refreshing row hammer includes the following operations. A row hammer refresh instruction for a target word line is determined. According to the row hammer refresh instruction, a preset row hammer refresh signal is set to a valid state. The valid state of the preset row hammer refresh signal indicates that the row hammer refresh instruction is performed in a first refresh period. In response to detecting that the row hammer refresh instruction is not completed within the first refresh period, the valid state of the preset row hammer refresh signal will be continued to a next refresh period of the first refresh period.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jixing Chen
  • Patent number: 11887694
    Abstract: A memory device includes a memory block and a peripheral circuit. The memory block includes a first word line group of word lines included in the memory block and a second word line group of the word lines included in the memory block. The word lines of the first word line group are different from the word lines of the second word line group. The peripheral circuit provides the first word line group and the second word line group with an equalizing voltage during an equalizing section overlapping an erase voltage discharging section for the memory block to constantly keep voltages of the first word line group and the second word line group to the equalizing voltage.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: January 30, 2024
    Assignee: SK hynix Inc.
    Inventor: Tae Heui Kwon
  • Patent number: 11886745
    Abstract: Methods, systems, and devices for illegal operation reaction are described. A memory device may receive one or more commands to perform one or more respective access operations on an array of memory cells. A first circuit of the memory device may determine that the one or more commands would violate one or more thresholds associated with operation of the memory device, such as a timing threshold. In some cases, the first circuit may compare the one or more commands to the one or more patterns of commands stored at the memory device. A second circuit of the memory device may erase one or more memory cells of the memory device based on determining that the one or more thresholds associated with operation of the memory device would be violated, based on comparing the set of commands to the one or more patterns, or a combination thereof.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Nathaniel J. Meier
  • Patent number: 11881244
    Abstract: A semiconductor memory apparatus includes an address generation circuit and an operation determination circuit. The address generation circuit generates a refresh target address that corresponds to a word line, among a plurality of word lines, the word line being adjacent to another word line in which row hammering has occurred. The operation determination circuit configured to generate an address matching information by comparing a row hammering address with the refresh target address.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: January 23, 2024
    Assignee: SK hynix Inc.
    Inventor: Jung Ho Lim
  • Patent number: 11881247
    Abstract: Apparatuses, systems, and methods for reset of row hammer detector circuits. A row hammer detector circuit includes a hash circuit configured to store a hash key and provide a first count value based on a hash between the hash key and a row address corresponding to a row of memory cells of a memory array. The row hammer detector circuit is configured to provide a match signal in response to the count value exceeding a threshold to cause a targeted refresh of a victim row adjacent the row of memory cells. In response to exit from a self-refresh mode, the hash circuit is configured to update the stored hash key with a new hash key.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: January 23, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Patent number: 11869567
    Abstract: A refresh control circuit includes: a random output sub-circuit for sequentially receiving n single-row addresses and m single-row addresses in L single-row addresses, a single enabling duration of word lines pointed to by the n single-row addresses being greater than a preset duration, the m single-row addresses ranking top m in occurrence frequency, the L single-row addresses corresponding to word lines turned on between adjacent refresh commands, n being a natural number, and m being a positive integer; and for receiving a first random number which is a positive integer less than or equal to n+m, and then outputting an i-th received single-row address, i being equal to the first random number; and a row hammer address generation sub-circuit for outputting a row hammer address corresponding to the received single-row address acting as a refresh object corresponding to the refresh command.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xianlei Cao
  • Patent number: 11862222
    Abstract: A refresh circuit includes: a refresh control module configured to receive a refresh command to output a row address refresh signal, the row address refresh signal being outputted a number of times of a preset value each time the refresh command is received; and further configured to receive a temperature signal to adjust the preset value, the higher a temperature represented by the temperature signal, the greater the adjusted preset value; a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh.
    Type: Grant
    Filed: November 27, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yinchuan Gu, Geyan Liu
  • Patent number: 11854595
    Abstract: A refresh circuit and a memory. The refresh circuit includes: a row hammer address generation module, configured to receive a row activate command, a precharge command, and a single row address corresponding to the row activate command, and output a row hammer address corresponding to the single row address, where each of the single row addresses corresponds to a word line, the row activate command is configured to activate a word line pointed to by the single row address, and the precharge command is configured to inactivate the word line; and output the row hammer address if a single activation time of the word line is greater than a preset time; and a signal selector, configured to receive the row hammer address and a regular refresh address, and at least output the row hammer address.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: December 26, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xianlei Cao
  • Patent number: 11848043
    Abstract: A memory device includes memory cells connected to a first word-line, wherein the memory cells include a data region in which data is stored and a counting value backup region in which the number of times the first word-line is activated is backed up, a counting table for storing a first row address corresponding to the first word-line and a first counting value as a counting result of the number of times the first word-line is activated, and a comparator configured to compare the first counting value with a first backed-up counting value stored in the counting value backup region; and when the first counting value is greater than the first backed-up counting value, back up the first counting value in the counting value backup region, or when the first backed-up counting value is greater than the first counting value, overwrite the first backed-up counting value into the counting table.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: December 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Min You, Ho-Youn Kim, Won-Hyung Song, Hi Jung Kim
  • Patent number: 11829224
    Abstract: In a method of operating a memory device, a first command to allow the memory device to enter an idle mode is received. A reference time interval is adjusted based on process, voltage and temperature (PVT) variation associated with the memory device. The reference time interval is used to determine a start time point of a power control operation for reducing power consumption of the memory device. A first time interval during which the idle mode is maintained is internally measured based on the first command. The power control operation is performed in response to the first time interval being longer than the reference time interval.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: November 28, 2023
    Inventors: Dongyeon Park, Youngjae Park, Hyungjin Kim, Reum Oh, Jinyong Choi
  • Patent number: 11830537
    Abstract: A memory core including a memory core including memory cells that are arranged in a plurality of rows and a plurality of columns; and a refresh target selection circuit suitable for storing an address and a risk score of each of activated rows among the rows, wherein the refresh target selection circuit is further suitable for increasing the risk score of a corresponding row whenever the corresponding row is activated, whenever a row at a ‘+2’ position of the corresponding row is activated, and whenever a row at a ‘?2’ position of the corresponding row is activated.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: November 28, 2023
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11823756
    Abstract: A method and device for testing a memory array structure, and a non-transitory storage medium are provided. The method includes that: respective storage data corresponding to each preset test pattern is written into a to-be-tested memory array, the each preset test pattern being one of preset test patterns in a preset test pattern library; a row aggressing test is repeatedly performed on the to-be-tested memory array until a bit error occurs in the storage data, to obtain row aggressing test times, corresponding to the each preset test pattern, of the to-be-tested memory array, where the bit error characterizes that the storage data has changed; a target preset test pattern corresponding to the to-be-tested memory array is determined from the preset test pattern library based on the row aggressing test times; and an array structure of the to-be-tested memory array is determined based on the target preset test pattern.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: November 21, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jianbin Liu, Maosong Ma
  • Patent number: 11817142
    Abstract: Embodiments of the present application provide a refresh circuit and a memory. The refresh circuit includes: a refresh control module configured to receive and execute a refresh command to output a row address refresh signal; and further configured to receive a process corner signal to adjust an execution proportion of the refresh command, the faster a process corner represented by the process corner signal, the higher the adjusted execution proportion; a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh. The embodiments of the present application help reduce the consumption of refresh currents.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: November 14, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yinchuan Gu, Geyan Liu
  • Patent number: 11798609
    Abstract: A semiconductor memory device is provided. The semiconductor memory device can suppress increases in power consumption. As a result, damage to the data normally caused by row problems can be prevented. The semiconductor memory device includes a control unit. The control unit controls the time interval for refreshing the memory. If the frequency of a read/write access requirement to the memory during a predetermined period is higher, then the control unit shortens the interval between memory refresh operations.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: October 24, 2023
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Junichi Sasaki
  • Patent number: 11798622
    Abstract: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Joemar Sinipete, John Christopher Sancon, Mingdong Cui
  • Patent number: 11798613
    Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: October 24, 2023
    Assignee: ETRON TECHNOLOGY, INC.
    Inventors: Chao-Chun Lu, Bor-Doou Rong, Chun Shiah
  • Patent number: 11798610
    Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: October 24, 2023
    Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
  • Patent number: 11783885
    Abstract: Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM), and an associated host device are described. The memory device includes control circuitry that can determine an operational status of the memory device (e.g., whether the memory device is currently performing a self-refresh operation). The control circuitry can also transmit a signal indicative of the operational status to the host device in response to receiving a command directing the memory device to exit a self-refresh mode. The host device can operate based on the signal. The signal may therefore allow the memory device, the host device, or both to manage operations, including whether to send, receive, or process commands and data read/write requests during times that may be associated with self-refresh operations.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Hyun Yoo Lee
  • Patent number: 11783881
    Abstract: Apparatuses, systems, and methods for direct refresh management (DRFM) commands. A controller provides a DRFM command to a memory along with a row address. A command decoder of the memory provides an activate command and then a pre-charge command along a signal line to a bank. During a tRP time after the pre-charge command before a next activate command, a DRFM sampling command is provided along the signal line which causes the address to be latched in a DRFM latch. Responsive to a later DRFM service command, one or more wordlines based on the address in the DRFM latch are refreshed.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Joo-Sang Lee
  • Patent number: 11763894
    Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: September 19, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Hun Kwak
  • Patent number: 11762768
    Abstract: A device is provided that includes a first memory and a second memory and an accessing circuit. Actual addresses of the first memory and the second memory alternately correspond to reference addresses of a processing circuit. The accessing circuit is configured to perform the steps outlined below. A read command corresponding to a reference read address is received from the processing circuit to convert the reference read address to an actual read address of the first memory and the second memory. A first read data is read from a first one of the first memory and the second memory according to the actual read address and a second read data is prefetched from a second one of the first memory and a second memory according to a next first read address simultaneously.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: September 19, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yung-Hui Yu, Chih-Wea Wang
  • Patent number: 11756646
    Abstract: A memory system includes a memory module and a memory controller. The memory module includes data chips that store data and are assigned to a first sub-channel that generates a first code word or a second sub-channel that generates a second code word, where the first code word and the second code are used to fill a single cache line. The memory controller, upon detection of a hard-fail data chip among the data chips, copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding I/O, and defines new mapping between the ECC chip and the corresponding I/O pins.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: September 12, 2023
    Inventors: Taekwoon Kim, Wonhyung Song, Jangseok Choi
  • Patent number: 11735262
    Abstract: A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell may be determined to a higher bit resolution than a data read value. A write condition may be selected for the RRAM cell, based on the cell characteristic. The RRAM cell may be written to, using the selected write condition.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: August 22, 2023
    Assignee: Hefei Reliance Memory Limited
    Inventors: Brent Haukness, Zhichao Lu
  • Patent number: 11721383
    Abstract: A refresh circuit includes: a signal generation module, configured to generate an inversion signal and a carry signal based on a refresh command; an adjustment unit, configured to generate, if a first refresh signal and a second refresh signal are generated based on the refresh command, an inversion adjustment signal according to the inversion signal, and generate, if only the first refresh signal is generated based on the refresh command, the inversion adjustment signal according to an inversion signal corresponding to a first refresh signal generated based on a current refresh command, and generate the inversion adjustment signal only according to an inversion signal corresponding to a second refresh signal generated based on a next refresh command; and a counting module, configured to generate a first output signal and a second output signal, and invert the first output signal based on the inversion adjustment signal.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: August 8, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jixing Chen
  • Patent number: 11721382
    Abstract: A refresh circuit includes signal selector configured to select one of normal and redundant word line logical addresses as output, output signal of which is designated as first logical address; row address latch connected to output terminal of signal selector and configured to output row hammer address and row hammer flag signal according to first logical address; seed arithmetic unit connected to output terminal of row address latch and configured to generate seed address according to row hammer address; logical arithmetic unit connected to output terminal of seed arithmetic unit and configured to obtain row hammer refresh address according to seed address, row hammer refresh address is adjacent physical address of seed address; and pre-decode unit connected to output terminal of logical arithmetic unit and configured to receive row hammer refresh address, and convert it into physical address to be used by memory array of memory to perform refresh operation.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: August 8, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xian Fan
  • Patent number: 11715512
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic targeted refresh steals. A memory bank may receive access commands and then periodically enter a refresh mode, where auto refresh operations and targeted refresh operations are performed. The memory bank may receive a refresh management command based on a count of access commands directed to the memory bank. Responsive to the refresh management signal, a panic targeted refresh operation may be performed on the memory bank. A number of times the refresh management signal was issued may be counted, and based on that count a next periodic targeted refresh operation may be skipped.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Liang Li, Yu Zhang, Yuan He
  • Patent number: 11705178
    Abstract: Embodiments of the present application provide a method and apparatus for determining a refresh counter of a DRAM. The method includes: writing data to a target memory cell connected with a target word line in the DRAM, and controlling the DRAM to perform refreshes starting from a preset word line according to a preset rule; determining, according to whether the data can be read accurately from the target memory cell after the refreshes, an intermediate refresh counter of refreshes on the target word line; and controlling, based on the intermediate refresh counter, the DRAM to perform refreshes starting from the target word line according to the preset rule, and determining the refresh counter of the DRAM according to whether the data can be read accurately from the target memory cell after the refreshes.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: July 18, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jing Chen, Wei-Chou Wang
  • Patent number: 11694728
    Abstract: A storage device may include: a memory device including a temperature sensor; and a memory controller for acquiring, from the memory device, temperature information sensed by the temperature sensor for a temperature management period, performing a performance limiting operation of limiting the performance of the memory device according to the temperature information, calculating the temperature management period by using the temperature information, and updating the temperature management period by using history information on a performance history of the performance limiting operation.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: July 4, 2023
    Assignee: SK hynix Inc.
    Inventors: Jeong Hyun Kim, Jin Soo Kim, Min Su Son, Na Young Lee, Chui Woo Lee
  • Patent number: 11688451
    Abstract: Apparatuses, systems, and methods for main sketch and slim sketch circuits for address tracking. The main sketch circuit receives a row address and changes selected count values in a first storage structure based on hash values generated based on the row address. Those count values are compared to a first threshold, and if that threshold is exceeded, a slim sketch circuit also receives the row address and changes selected count values in a second storage structure based on hash values generated based on the row address. Based on the selected count values from the first storage structure, the second storage structure, or combinations thereof, the row address may be determined to be an aggressor address.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yu Zhang, Liang Li
  • Patent number: 11682444
    Abstract: A dynamic random-access memory array includes a plurality of memory cells and sensor cells physical arranged in a row. The sensor cells include a transistor and a capacitor having an input terminal connected to a first non-gate terminal of the transistor. A wordline is connected to transistor gates of both the memory cells and sensor cells in the row. A sensor amplifier has inputs connected to the sensor cell, a high voltage reference line, and a low voltage reference line, and an output in communication with a row refresh circuit. If the sensor amplifier detects that the sensor cell voltage falls outside of the range of the high and low voltage reference lines, then a trigger signal is output to request that the row refresh circuit perform a priority row refresh of the memory cells and the sensor cell in the row.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: June 20, 2023
    Assignee: Lenovo Golbal Technology (United States) Inc.
    Inventors: Jonathan Hinkle, Jose M Orro
  • Patent number: 11681536
    Abstract: Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes performing a read operation on a non-volatile memory to obtain a first value. The method further includes comparing the value to a predetermined value to obtain a comparison result. The method further includes determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result. The method further includes performing, based on the determining, a read operation on the boot image to obtain data associated with booting of a device. The method further includes booting the device based at least on the data. Related systems and devices are provided.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: June 20, 2023
    Assignee: Lattice Semiconductor Corporation
    Inventors: Fulong Zhang, John Gordon Hands, Wei Han, Mark Everhard
  • Patent number: 11669425
    Abstract: Disclosed are devices and methods for periodically powering up a storage device(s) (SSDs) associated with a vehicle to avoid and prevent data loss. The disclosed embodiments provide mechanisms for preserving stored data collected during the running of a vehicle without requiring the main power supply to be routed through the CPU. Through the improved configuration and application of the disclosed power management integrated circuitry (PMIC), storage devices of a vehicle are enabled to be provided direct power and refreshed without powering on the vehicle (e.g., starting the car). The PMIC also ensures that the necessary power can be provided to and maintained to the storage device(s) in the event of an unexpected power loss.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Poorna Kale, Kishore Rao
  • Patent number: 11670355
    Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: June 6, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minsu Kim, Namhyung Kim, Daejeong Kim, Dohan Kim, Chanik Park, Deokho Seo, Wonjae Shin, Changmin Lee, Ilguy Jung, Insu Choi
  • Patent number: 11664063
    Abstract: Aggressor rows may be detected by comparing access count values of word lines to a threshold value. Based on the comparison, a word line may be determined to be an aggressor row. The threshold value may be dynamically generated, such as a random number generated by a random number generator. In some examples, a random number may be generated each time an activation command is received. Responsive to detecting an aggressor row, a targeted refresh operation may be performed.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: May 30, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Simon J. Lovett
  • Patent number: 11664061
    Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: May 30, 2023
    Inventors: Youngcheon Kwon, Sanghyuk Kwon, Kyomin Sohn, Jaeyoun Youn, Haesuk Lee
  • Patent number: 11663124
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data may be retrieved from a memory array for the pattern matching operation by a read operation, a refresh operation, an error correction operation, and/or a pattern matching operation. The data may be retrieved from incoming data input lines instead of or in addition to the memory array. How the data is stored or retrieved for pattern matching operations may be controlled by a memory controller.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: May 30, 2023
    Assignee: Micron Technology, Inc.
    Inventors: James S. Rehmeyer, Libo Wang, Anthony D. Veches, Debra M. Bell, Di Wu
  • Patent number: 11657865
    Abstract: A dynamic memory system having multiple memory regions respectively storing multiple types of data. A controller coupled to the dynamic memory system via a communication channel and operatively to: monitor usage of a communication bandwidth of the communication channel; determine to reduce memory bandwidth penalty caused by refreshing the dynamic memory system; and in response, reduce a refresh rate of at least one of the memory regions based on a type of data stored in the respective memory region.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Gil Golov
  • Patent number: 11651811
    Abstract: A memory apparatus comprises: a sampling circuit for sampling an input address through a sampling method corresponding to a first selection signal among at least two sampling methods, a storage circuit for storing up to N number of addresses having different values among sampled addresses received from the sampling circuit, an arranging circuit for determining an output sequence of addresses stored in the storage circuit through an arranging method corresponding to a second selection signal among the two arranging methods, and setting, as a target address, an address outputted according to the output sequence, a selection control circuit for setting each of the first selection signal and the second selection signal based on a state of the storage circuit, and a refresh operation circuit for controlling a target refresh operation on a row of memory cells corresponding to the target address.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: May 16, 2023
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11651812
    Abstract: A memory system includes: a memory controller suitable for: generating a normal refresh command and a target refresh command when a number of inputs of an active command reaches a certain number, and providing the active command, the normal refresh command, the target refresh command, and an address; and a memory device including a plurality of banks and suitable for: performing a target refresh operation on one or more word lines of at least one bank in response to the target refresh command, determining a row hammer risk level per bank by counting, within a periodic interval, a number of inputs of the target refresh command per bank based on the address, and performing a hidden refresh operation corresponding to the row hammer risk level per bank in response to the normal refresh command.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: May 16, 2023
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Duck Hwa Hong, Jeong Tae Hwang
  • Patent number: 11651815
    Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Yoshihito Morishita, Daigo Toyama, Takamasa Suzuki
  • Patent number: 11651818
    Abstract: According to one embodiment, a memory device includes: a variable resistance memory region; a semiconductor layer; an insulating layer; first and second word lines; and a first select gate line. When information stored in the first memory cell is read, or when information is written into the first memory cell, after a voltage of the first select gate line is set to a first voltage and voltages of the first and second word lines are set to a second voltage, the voltage of the first select gate line is increased from the first voltage to a third voltage. After the voltage of the first select gate line is increased to at least the second voltage, the voltage of the first word line is decreased from the second voltage to the first voltage, and the voltage of the second word line is increased from the second voltage to a fourth voltage.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: May 16, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Takahiko Iizuka
  • Patent number: 11651810
    Abstract: A memory system includes: a plurality of memory chips each including a plurality of banks and each suitable for generating a tracking address by tracking a row-hammer risk of selected banks among the banks, encrypting the tracking address using an encryption key to output tracking information to a corresponding data bus of a plurality of data buses and performing a target refresh operation according to a row-hammer address transferred through a command/address bus; and a memory controller suitable for collecting the tracking information for the banks transferred through the plurality of data buses to generate and output the row-hammer address to the command/address bus.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: May 16, 2023
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11651813
    Abstract: A clock correction circuit in which a correction accuracy of a duty cycle is increased is provided.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: May 16, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hun-Dae Choi, Ga Ram Choi
  • Patent number: 11646072
    Abstract: An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: May 9, 2023
    Assignee: SK hynix Inc.
    Inventors: Hyun Seung Kim, Ho Uk Song, Tae Kyun Shin, Min Jun Choi, Duck Hwa Hong
  • Patent number: 11644989
    Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeon-kyu Choi, Ki-seok Oh, Seung-jun Shin, Hye-ran Kim
  • Patent number: 11644979
    Abstract: A processing device in a memory system assigns a memory page to a sensitivity tier of a plurality of sensitivity tiers. The processing device determines respective scan intervals for the plurality of sensitivity tiers, wherein the respective scan intervals are based on at least one characteristic of a memory device, the at least one characteristic comprising memory cell margins of the memory device. The processing device scans a subset of a plurality of memory pages, wherein the subset comprises a number of memory pages from each sensitivity tier identified according to the respective scan intervals.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: May 9, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Gary F. Besinga, Cory M. Steinmetz, Pushpa Seetamraju, Jiangang Wu, Sampath K. Ratnam, Peter Feeley
  • Patent number: 11640840
    Abstract: An electronic device includes a memory having a plurality of memory rows and a memory refresh functional block that performs a victim row refresh operation. For the victim row refresh operation, the memory refresh functional block selects one or more victim memory rows that may be victims of data corruption caused by repeated memory accesses in a specified group of memory rows near each of the one or more victim memory rows. The memory refresh functional block then individually refreshes each of the one or more victim memory rows.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: May 2, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: SeyedMohammad SeyedzadehDelcheh, Gabriel H. Loh
  • Patent number: 11640346
    Abstract: A method includes monitoring a temperature of a memory component of a memory sub-system to determine that the temperature of the memory component corresponds to a first monitored temperature value; writing data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the first monitored temperature value; determining that the first monitored temperature value exceeds a threshold temperature range; monitoring the temperature of the memory component of the memory sub-system to determine that the temperature of the memory component corresponds to a second monitored temperature value that is within the threshold temperature range; and rewriting the data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the second monitored temperature value.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: May 2, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ting Luo, Tao Liu, Christopher J. Bueb, Eric Yuen, Cheng Cheng Ang