Abstract: Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

Abstract: A memory includes: a plurality of word lines; and a row circuit configured to: activate at least one word line among the word lines to an active voltage level during an active operation and discharge the activated word line during a precharge operation; and discharge the word line from the active voltage level to a precharge voltage level in different manners during the precharge operation in response to a precharge command and during the precharge operation during a refresh operation.

Abstract: A memory device and a control method of the memory device are provided. The memory device includes a memory array and a control logic circuit. The memory array includes memory cell rows. The control logic circuit includes a counter and a reset circuit. The counter counts a number of an access performed on the memory cell rows to generate a count value corresponding to the accessed memory cell row among the memory cell rows, and sets the count value to a random value when the count value is equal to the predetermined value and when the access is performed. The reset circuit resets the count value to a predetermined value in responses to a refresh command. When the count value reaches to the threshold value, the control logic circuit arranges memory cell rows nearby the accessed memory cell row into a mitigation operation.

Abstract: A memory includes: a memory core; a list storage circuit suitable for storing a weak row list of rows that are vulnerable to a row hammer attack in the memory core; and a row hammer attack detection circuit suitable for selecting rows that are row-hammer-attacked among rows in the memory core as hammered rows, and increasing a probability that the rows stored in the list storage circuit are selected as the hammered rows.

Abstract: An operation method of a memory may include receiving an active command and an active address; determining whether a row corresponding to the active address and a row corresponding to a target row address are able to be substantially simultaneously activated; activating the row corresponding to the active address; and activating the row corresponding to the target row address in response to determining that the row corresponding to the active address and the row corresponding to the target row address are able to be substantially simultaneously activated.

Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.

Abstract: Disclosed in the present invention are a highly energy-efficient CAM based on a single FeFET and an operating method thereof, which relate to a design of an FeFET-based memory suitable for low power consumption and high performance. A brand-new design of a CAM cell based on the single FeFET is achieved by fully utilizing the storage characteristics of the FeFET, so that the number of transistors is saved, the search energy consumption is reduced, and the nonvolatility of data storage is obtained. The present invention utilizes a 2T-1FeFET structure, and combines the advantages of the FeFET and CMOS. Without reducing performance, only one FeFET is utilized to implement a less area overhead and a lower energy consumption compared with a traditional CMOS-based CAM, and non-volatility is achieved.

Abstract: The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.

Abstract: A semiconductor memory device includes: a memory core including memory cells and configured to output core data stored in the memory cells in response to a read request, a command decoder configured to decode at least one command input from an external device, a command log register configured to sequentially store the at least one command in response to a register enable signal and output the at least one command as a command log in response to a command log read signal, and a mode register set configured to generate the register enable signal or the command log read signal in response to a mode register set command transmitted to the command decoder.

Abstract: Apparatuses and methods for row hammer counter mat. A memory array may have a number of memory mats and a counter memory mat. The counter mat stores count values, each of which is associated with a row in one of the other memory mats. When a row is accessed, the count value is read out, changed, and written back to the counter mat. In some embodiments, the count value may be processed within access logic of the counter mat, and a row hammer flag may be provided to the bank logic. In some embodiments, the counter mat may have a folded architecture where each sense amplifier is coupled to multiple bit lines in the counter mat. The count value may be used to determine if the accessed row is an aggressor so that its victims can be refreshed as part of a targeted refresh.

Abstract: A refresh control circuit includes: a counting bloom filter that includes N hash control logics, each of which performs a hash operation on input data and outputs an M-bit sequence and M counters, each of which corresponds to a bit of the M-bit sequence, and updates count values of corresponding counters indicated by values of the M-bit sequences obtained from the N hash logics by using an address of a row of the memory cells as the input data; a candidate row determiner that determines rows of the memory cells accessed in a predetermined period in which the count values of the corresponding counters are greater than a threshold value as candidate rows for a target refresh operation; and a target refresh controller that outputs target refresh signals for rows of the candidate rows adjacent to one or more target rows determined by the candidate row determiner.

Abstract: Methods, systems, and devices for adjusting a refresh rate during a self-refresh state are described. A memory system may enter a self-refresh state and execute a first set of refresh operations on a set of rows of memory cells at the memory system according to a first rate. The memory system may determine, based on executing the first set of refresh operations, that a counter associated with the set of refresh operations satisfies a threshold for a second time while the memory system is in the self-refresh state. In response to the counter satisfying the threshold for the second time, a flip-flop circuit at the memory system may modify an output of the flip-flop circuit and the memory system may decrease the rate for executing the refresh operations to a second rate based on the modified output of the flip-flop circuit.

Abstract: Some areas (e.g., boundary wordlines) in a block of memory can be more error prone than others. Typically, errors in these areas are not detected until after the entire block is programmed. Handling such errors then can result in performance penalties and large data relocations. With the embodiments presented herein, a two-stage programming operation is provided. In the first stage, only the error-prone areas of the block are programmed, and a check is made to determine if an error occurred in that programming. In the second stage, the remaining portions of the block are programmed, but that only occurs after it is determined that the error-prone areas have been programmed successfully. Detecting and dealing with errors in the error-prone areas before the entire block is programmed avoid the performance penalties and large data relocations noted above.

Abstract: Apparatuses, systems, and methods for sample rate adjustment. A memory may sample row addresses based on a sampling rate to determine aggressor addresses. The memory includes a sample adjustment circuit which monitors a rate of refresh operations and adjusts the sampling rate based on the monitored rate. The sample adjustment circuit may provide a calculated temperature value based on the monitored rate, and the calculated temperature may be used to set a sampling rate. The refresh rate may be based on a measured temperature.

Abstract: A memory control circuit and a refresh method for a dynamic random access memory (DRAM) array are provided. The memory control circuit includes a mode register circuit, a command decoder and a refresh circuit. The mode register circuit includes a plurality of mode registers. The command decoder receives a refresh command and sets a flag of a target mode register corresponding to the refresh command among the plurality of mode registers to a setting value. The refresh circuit refreshes the DRAM array in response to the refresh command through the command decoder and the setting value of the flag of the target mode register.

Abstract: Systems and methods for multi-wordline direct refresh operations in response to a row hammer error in a memory bank. The approach includes detecting, by a row hammer mitigation component, a row hammer error in a memory bank; and then triggering, by the row hammer mitigation component, a response to the row hammer error. Further, a memory controller receives, from a mode register, data, based on an aliasing row counter policy, selecting a type of multi-wordline direct refresh operation to be performed on a plurality of victim memory rows within the memory bank, wherein the plurality of victim memory rows are dispersed across a plurality of memory sub-banks. The approach includes concurrently executing the selected multi-wordline direct refresh operation to the plurality of victim memory rows.

Abstract: Signaling indicative of a command to initialize a plurality of memory dies of a memory device can be received by the memory device. Initialization of a memory die of the memory device can be delayed, at the memory die and based at least in part on fuse states of an array of fuses of the memory die, by an amount of time relative to receipt of the signaling by the memory device. Delaying initialization of memory dies of the memory device in a staggered or asynchronous manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.

Abstract: A memory device is provided. The memory device includes a plurality of memory chips that are stacked, wherein each of the memory chips includes a memory cell array, which includes a plurality of memory cell rows, a chip identifier generator configured to generate a chip identifier signal indicating a chip identifier of each of the memory chips, a refresh counter configured to generate a target row address for refreshing the memory cell rows in response to a refresh command, and a refresh row address generator, which receives the chip identifier signal and the target row address and outputs one of the target row address and an inverted target row address, obtained by inverting the target row address, as a refresh row address based on the chip identifier signal, and performs a refresh operation on a memory cell row corresponding to the refresh row address.

Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.

Abstract: A memory device controller for a non-volatile memory device can be configured to allow exclusive access to initiate or increment a refresh routine based on an earlier-received one of a refresh command from a host device or an interval-triggered refresh command from the controller. The memory device controller can be configured to lock out access to the refresh routine from a later-received one of the refresh command from the host device or the interval-triggered refresh command from the controller. The memory device controller can release a lock on access to the refresh routine upon completion of a block refresh routine for a memory block of the memory device. In some examples, the refresh command from the host device can be based on a power cycle status of the host device.

Abstract: A circuit structure for realizing circuit pin multiplexing, comprising an MCU module, a temperature sensing circuit and a functional module circuit. The output end of the temperature sensing circuit is connected with an enable signal interface of the MCU module, the output voltage of the temperature sensing circuit is always higher than the threshold voltage of the enable signal, and the MCU module is connected with the functional module circuit. The circuit structure of the present invention realizes the mutual influence of analog signal output and digital signal transmission by designing a temperature sensing output curve, and achieves multi-function multiplexing of a single pin, so that the output of the analog signal and the input of the digital signal can share the pins, it solves the problem of the limitation of the number of pins, and promotes the transmission of the signal and improves the cost performance of the circuit.

Abstract: A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.

Abstract: A refresh control circuit includes the following: an address output circuit configured to output a to-be-refreshed address signal including a block address signal and a row address signal; a block decoding circuit configured to: receive the block address signal; decode the block address signal and output a first block selection signal for selecting multiple data blocks from the memory array, in response to that the memory array is subjected to no row hammer attack, or decode the block address signal and output a second block selection signal for selecting one data block from the memory array, in response to that the memory array is subjected to a row hammer attack; and a row decoding circuit, configured to receive the row address signal, decode the row address signal and output a row selection signal.

Abstract: An auto refresh limiting circuit includes an oscillating signal generating part that generates an internal oscillating signal, the internal oscillating signal being a pulse having a period reflecting an internal temperature of a semiconductor memory device; a masking signal generating part that generates a masking signal by using an auto refresh command signal and the internal oscillating signal, the masking signal being deactivated during a pulse of the auto refresh command signal, the pulse of the auto refresh command signal being first generated after the pulse of the internal oscillating signal is generated; and an auto refresh masking part that converts the pulse of the auto refresh command signal into a pulse of an auto refresh driving signal, the conversion of the pulse of the auto refresh driving signal being masked according to the activation of the masking signal.

Abstract: Apparatuses, systems, and methods for access based targeted refresh operations. A memory bank has a first sub-bank and a second sub-bank. A refresh control circuit detects an aggressor in one of the sub-banks. Responsive to an access in the other sub-bank, the refresh control circuit performs a targeted refresh operation based on the sub-bank based on the aggressor address.

Abstract: Embodiments relate to a test method, a computer apparatus, and a computer-readable storage medium. The test method includes: writing first data into a target memory cell; performing reverse writing on the target memory cell; reading second data stored in the target memory cell after the reverse writing; determining whether the second data are the same as the first data; and determining that write recovery time of the target memory cell fails when the second data are the same as the first data. The present disclosure can make an effective test of determining whether the write recovery time fails.

Abstract: An integrated circuit includes a sampling control circuit configured to generate a sampling enable signal by dividing a sampling period into a plurality of sub-sections according to an active counting signal generated by counting a number of inputs of an active signal during the sampling period, and comparing the active counting signal with a random signal for each sub-section; and a sampling circuit configured to sample and store an input address according to the sampling enable signal.

Abstract: A voltage supply circuit includes a temperature compensation circuit and a voltage regulation circuit. The temperature compensation circuit includes a comparator circuit comparing a device temperature value with a reference value to output a comparison result, and a compensation controller circuit receiving the comparison result, a compensation value control signal, and a compensation enable signal, and outputting a voltage control signal according to the comparison result. The voltage regulation circuit receives the voltage control signal and provides a voltage output according to the control signal.

Abstract: A method including obtaining temperature values of at least one region of the non-volatile memory, each temperature value obtained at a given time instant, for each obtained temperature value at each given time instant, calculating the value of an operating function representative of an operating condition of the non-volatile memory, the value such operating function being time-dependent according to the temperature time-variation of such at least one region of the non-volatile memory, summing subsequent computed values of said operating function to obtain an accumulated value being representative of an elapsed fraction of a time limit associated with the at least one region of the non-volatile memory, comparing the accumulated value with a threshold value, and, based on said comparison, performing a management operation on the cells of the at least one region of the non-volatile memory when the accumulated value has a magnitude equal or greater than the threshold value.

Abstract: An effect known as “rowhammer” may be mitigated in a DRAM organized in sub-banks of two or more rows. Row activation commands directed to a sub-bank may be detected. The number of row activation commands occurring within a refresh window may be counted and compared with a threshold. When it is detected that the number of row activation commands within the refresh window exceeds the threshold, an additional refresh command may be provided to the DRAM.

Abstract: Virtualized scan chain testing in a random access memory array, and related methods and computer-readable media are disclosed. To facilitate virtualized scan chain testing, the memory array includes an integrated test circuit that causes the memory array to behave as a serialized scan chain. The integrated test circuit forces serialized write and read access to offset entries in the memory array on each scan cycle in a scan mode based on received serialized test data. After the number of scan cycles equals the number of entries the memory array, the entries in the memory array are fully initialized with test data from the serial test data flow. In subsequent scan cycles, the integrated test circuit continues to perform serial read operations to cause stored serial test data to be serially shifted out as an output serial data flow that then be compared to the original serial test data.

Abstract: Methods of operating a memory device are disclosed. A method may include determining an amount of activity associated with at least one memory bank of a memory device. The method may further include adjusting a row hammer refresh rate for the at least one memory bank based on the amount of activity associated with the at least one memory bank. Memory devices and systems are also described.

Abstract: An operation method of memory may include activating a first row that is selected in a first bank, activating a second row that is selected in a second bank, receiving an all-bank counting command, reading a first access count from memory cells of specific columns of the first row in response to the all-bank counting command, increasing the first access count, writing the increased first access count in the memory cells of the specific columns of the first row, reading a second access count from memory cells of specific columns of the second row in response to the all-bank counting command, increasing the second access count, and writing the increased second access count in the memory cells of the specific columns of the second row.

Abstract: An operating method of a memory device, the method including, receiving a row address, determining whether an operating mode is a byte mode, counting up an access count value for the row address while ignoring a page bit, when the operating mode is the byte mode, selecting a target row hammer address among target row addresses using access count values for the target row hammer address, calculating a victim row address corresponding to the target row hammer address, and performing a target refresh operation on the victim row address.

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.

Abstract: The present disclosure provides methods, apparatuses, and systems having reduced power noise in a refresh operation. In some embodiments, an operating method includes: performing, in response to receiving a first refresh command, a first normal refresh, at a first refresh timing, in which first N word lines of a plurality of word lines are simultaneously refreshed, and a first target refresh, at a second refresh timing, on at least one first victim word line that is adjacent to a maximum activated word line that is most frequently activated from among the plurality of word lines; and performing, in response to receiving a second refresh command, a second normal refresh, at a third refresh timing, in which second N word lines are simultaneously refreshed, and a second target refresh, at a fourth refresh timing, on at least one second victim word line that is adjacent to the maximum activated word line.

Abstract: Methods and apparatus for video processing are described. The processing may include video encoding, video decoding, or video transcoding. An example video processing method includes performing a conversion between a video and a bitstream of the video including one or more output layer sets according to a format rule. At least one of the one or more output layer sets consists of a trick mode access representation including only intra random access points pictures or only intra-coded pictures. The format rule specifies whether or how level information for the trick mode representation is indicated in the bitstream.

Abstract: In some implementations, a memory device may detect power up and may identify, based on detecting the power up, a plurality of blocks of the memory device for which a power up based refresh determination is to be performed. The memory device may perform the power up based refresh determination on the plurality of blocks. The memory device may determine whether a block, of the plurality of blocks, satisfies at least one of an age condition that is based on a difference between a current time and an opening time associated with opening the block for programming, or a temperature condition that is based on a difference between a current temperature and an opening temperature associated with the block at the opening time. The memory device may selectively refresh the block based on determining whether the block satisfies at least one of the age condition or the temperature condition.

Abstract: A memory includes: a plurality of memory banks suitable for storing data; a read peripheral region including circuits suitable for transferring data that are read from one memory bank among the memory banks to a memory controller during a read operation; a write peripheral region including circuits suitable for transferring write data that are transferred from the memory controller to one memory bank among the memory banks during a write operation; and a self-refresh counter circuit suitable for activating a self-refresh read signal for activating the read peripheral region whenever a self-refresh operation is performed N times, where N is an integer equal to or greater than 1.

Abstract: A Near Memory Processing (NMP) module including: a plurality of memory units; an Input/Output (I/O) interface configured to receive commands from a host system, wherein the host system includes a host memory controller configured to access the plurality of memory units; a decoder configured to decode the commands and generate a trigger; and an NMP memory controller configured to: receive the trigger from the decoder; and generate a signal in response to the trigger to synchronize the NMP module with the host system.

Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

Abstract: A method of controlling a row hammer swaps a first address entry with a second address entry having the smallest second access number and randomly swaps the first address entry with a third address entry having a third access number which is not the greatest value, in an address table representing a correlation between an address entry accessed during a row hammer monitoring time frame and an access number, thereby preventing a hacker-pattern row hammer aggression from being easily performed.

Abstract: A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a memory cell array, a normal refresh row address generator, a hammer refresh row address generator, a refresh selection signal generator, and a selector. The normal and hammer refresh row address generators generates a normal refresh row address and a hammer refresh row address, respectively, in response to a refresh counting control signal. The refresh selection signal generator sequentially generates normal and hammer refresh selection signals in response to the refresh counting control signal. The selector selects the normal refresh row address or the hammer refresh row address in response to the normal and hammer refresh selection signals. A normal refresh operation and a hammer refresh operation are sequentially performed on a memory cell array block among plural memory cell array blocks in response to the refresh row address.

Abstract: An integrated circuit memory device includes an array of storage cells configured into multiple banks. Each bank includes multiple segments. Register storage stores per-segment values representing per-segment refresh parameters. Refresh logic refreshes each segment in accordance with the corresponding per-segment value.

Abstract: A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.

Abstract: A memory device and an operating method of the memory device are provided. The operating method comprises receiving an activation-refresh command from a memory controller, decoding a target address and an internal command from the activation-refresh command, and performing an activation operation based on the internal command for the target address and performing a refresh operation on at least one block to which the target address does not belong.

Abstract: The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a cross-point memory array includes memory cells. A media controller reads one or more first memory cells and determines a read status. The read status indicates an error when reading the first memory cells. In response to this error, the controller refreshes the first memory cells. The controller uses the read status to determine zero-to-one failures associated with the first memory cells. If a number of these failures exceeds a threshold, then a refresh is applied to neighboring memory cells of the first memory cells. The physical addresses for the neighboring memory cells are determined by the controller from the physical addresses for the first memory cells.