Data Refresh Patents (Class 365/222)
  • Patent number: 10885966
    Abstract: A method of protecting a DRAM memory device from the row hammer effect includes the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks and to execute, on each activation of a row of a sub-bank (b) of the memory, an increment step of a required number of preventive refreshments (REFRESH_ACC; REFRESH_ACC/PARAM_D) of the sub-bank (b) using an activation threshold (PARAM_D) of the sub-bank (b). The prevention logic is also configured to execute a preventive refresh sequence of the sub-banks according to their required number of preventive refreshes. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: January 5, 2021
    Assignee: UPMEM
    Inventors: Fabrice Devaux, Renaud Ayrignac
  • Patent number: 10878907
    Abstract: Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: December 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Patent number: 10878142
    Abstract: Disclosed are methods and systems for producing bipole source modeling with reduced computational loads. A method may comprise receiving first electromagnetic data and second electromagnetic data from a first shotpoint and a second of a marine electromagnetic survey, modelling a first electromagnetic field and second electromagnetic field for one or more dipole sources of a bipole source and combining a plurality of data points to provide an approximation of an electromagnetic field for the bipole source. A system may comprise electromagnetic sensors, a bipole source, wherein the bipole source comprise a pair of electrodes that are separated by a distance, wherein the bipole source is configured to generate an electromagnetic field, and a data processing system configured to receive electromagnetic data from a plurality of shotpoints of the bipole source and model electromagnetic fields for one or more dipole sources of the bipole source from the electromagnetic data.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: December 29, 2020
    Assignee: PGS Geophysical AS
    Inventors: Lars Erik Magnus Björnemo, Carl Joel Gustav Skogman
  • Patent number: 10878877
    Abstract: A memory device applies different refresh rates to target data (or objective data) according to data characteristics (i.e., required reliability levels). The memory device includes a memory cell array provided with a plurality of memory cells, a row decoder configured to selectively activate word lines of the memory cell array in response to a row address signal, and a refresh controller configured to output the row address signal in response to the row address signal. The refresh controller controls a refresh ratio of a first storage region and a second storage region contained in the memory cell array in response to a changeable refresh control value.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Ho Sung Cho
  • Patent number: 10877951
    Abstract: Techniques are disclosed for notifying network control software of new and moved source MAC addresses. In one embodiment, a switch may redirect a packet sent by a new or migrated virtual machine to the network control software as a notification. The switch does not forward the packet, thereby protecting against denial of service attacks. The switch further adds to a forwarding database a temporary entry which includes a “No_Redirect” flag for a new source MAC address, or updates an existing entry for a source MAC address that hits in the forwarding database by setting the “No_Redirect” flag. The “No_Redirect” flag indicates whether a notification has already been sent to the network control software for this source MAC address. The switch may periodically retry the notification to the network control software, until the network control software validates the source MAC address, depending on whether the “No_Redirect” is set.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: December 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Josep Cors, Venkatesh K. Janakiraman, Sze-Wa Lao, Sameer M. Shah, David A. Shedivy, Ethan M. Spiegel, Natarajan Vaidhyanathan, Colin B. Verrilli
  • Patent number: 10872638
    Abstract: The subject technology performs the following in a storage system including memory dies, where each memory die includes its own temperature sensor. The subject technology determines a temperature of each of the memory dies based on a temperature reading from each memory die's temperature sensor. The subject technology determines whether data is hot data or cold data, where hot data is more likely to be changed after it is written than cold data. In response to determining that the data is hot data, the subject technology stores the data in a memory die with a relatively higher temperature than another one of the memory dies. Further, in response to determining that the data is cold data, the subject technology stores the data in a memory die with a relatively cooler temperature than another one of the memory dies.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 22, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jingfeng Yuan, James M. Higgins, Jeff Whaley
  • Patent number: 10868024
    Abstract: A method includes forming first and second gate stacks over a substrate. Each of the first and second gate stacks includes a tunneling dielectric layer, a floating gate over the tunneling dielectric layer, a middle dielectric layer over the floating gate, and a control gate over the middle dielectric layer. A conductive layer is formed over the first and second gate stacks. The conductive layer is etched to form a erase gate between the first and second gate stacks. Etching the conductive layer is performed such that a top surface of the erase gate is not higher than a top surface of the control gate and such that the top surface of the erase gate is at least partially curved inwards.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Ming Wu, Wei-Cheng Wu, Yuan-Tai Tseng, Shih-Chang Liu, Chia-Shiung Tsai, Ru-Liang Lee, Harry-Hak-Lay Chuang
  • Patent number: 10867656
    Abstract: A memory includes: first to Nth areas refreshed based on first to Nth refresh control signals, respectively; a control signal generation circuit suitable for generating the second to Nth refresh control signals by sequentially delaying the first refresh control signal, and generating the first refresh control signal by delaying the Nth refresh control signal; an address counter suitable for changing a refresh address, corresponding to each round for activations of the first to Nth refresh control signals, based on the Nth refresh control signal; and a refresh stop circuit suitable for stopping a refresh operation when the round is repeated by a predetermined number.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: December 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Yo-Sep Lee
  • Patent number: 10861519
    Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: William F. Jones, Jeffrey P. Wright
  • Patent number: 10854311
    Abstract: A determination is made by a processing device included in a memory component that an operation to program data to a location in the memory component has failed, the data is programmed to a different location in the memory component by the processing device upon determining the operation has failed, and a notification that the data has been programmed to the different location in the memory component is provided by the processing device to a processing device operatively coupled to the memory component.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Adam J. Hieb
  • Patent number: 10847207
    Abstract: Apparatuses and methods for maintaining an active state of a word driver signal are described. The word driver may be included in a memory device including a hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. During an operation such as a refresh operation, a driving signal provided by a word driver to a subword driver may be held in an active state while the driving signal provided by a main word driver to the subword driver transitions between active and inactive states. In some examples, the word driver may include a latch for latching an activation signal at an initiation of a refresh operation to maintain a state of the driving signal.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Nobuo Yamamoto, Takamasa Suzuki
  • Patent number: 10847205
    Abstract: A memory system includes a first memory chip that includes a first temperature sensor, and a memory controller that includes a second temperature sensor. The memory controller is configured to: perform, at a first timing, a first temperature acquisition process including acquiring a first measured temperature using the first temperature sensor or the second temperature sensor; select one of the first temperature sensor and the second temperature sensor for a second temperature acquisition process based the first measured temperature; and perform, at a second timing later than the first timing, the second temperature acquisition process including acquiring a second measured temperature using the selected one of the first temperature sensor or the second temperature sensor.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: November 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yohei Maruyama, Katsuya Ohno
  • Patent number: 10847204
    Abstract: An apparatus comprises first and second memory regions each to store data using a data storage technology for which retention of data for longer than a predetermined period of time is dependent on a refresh operation for refreshing data in the memory region being performed at a frequency that is greater than or equal to a minimum refresh frequency. The apparatus further comprises at least one controller to control storage of data in the first memory region with the refresh operation performed at a first frequency lower than said minimum refresh frequency when valid data is stored in the first memory region, and to control storage of data in the second memory region with the refresh operation performed at a second frequency that is greater than or equal to said minimum refresh frequency. The at least one controller is configured to communicate with the first memory region via a first memory channel and with the second memory region via a second memory channel.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: November 24, 2020
    Assignee: ARM LIMITED
    Inventor: Wei Wang
  • Patent number: 10836400
    Abstract: An example apparatus comprises a memory resource configured to store data and transmit data. The apparatus may further include a safety controller coupled to the memory resource configured to receive the data from the memory resource, receive latched data from an application controller, and determine whether to allow an output of commands from the application controller in response to a comparison of the data from the memory resource and the latched data from the application controller.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Alberto Troia
  • Patent number: 10838942
    Abstract: Techniques are disclosed for notifying network control software of new and moved source MAC addresses. In one embodiment, a switch may redirect a packet sent by a new or migrated virtual machine to the network control software as a notification. The switch does not forward the packet, thereby protecting against denial of service attacks. The switch further adds to a forwarding database a temporary entry which includes a “No_Redirect” flag for a new source MAC address, or updates an existing entry for a source MAC address that hits in the forwarding database by setting the “No_Redirect” flag. The “No_Redirect” flag indicates whether a notification has already been sent to the network control software for this source MAC address. The switch may periodically retry the notification to the network control software, until the network control software validates the source MAC address, depending on whether the “No_Redirect” is set.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Josep Cors, Venkatesh K. Janakiraman, Sze-Wa Lao, Sameer M. Shah, David A. Shedivy, Ethan M. Spiegel, Natarajan Vaidhyanathan, Colin B. Verrilli
  • Patent number: 10839886
    Abstract: Aspects of the disclosure provide systems and methods for adaptive data retention management in non-volatile memory. A solid state device (SSD) includes non-volatile memory (NVM) for storing data. The SSD is configured to determine a temperature of the NVM. If the temperature of the NVM is below a predetermined temperature, the SSD maintains a data retention refresh rate of the data stored in the NVM. If the temperature of the NVM is equal to or above the predetermined temperature, the SSD adjusts the data retention refresh rate at a first rate and then a second rate, each adjustment based on the temperature of the NVM. The first rate and the second rate are different, for example, the second rate is less than the first rate.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: November 17, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jingfeng Yuan, Jeffrey Lee Whaley, Xiaoheng Chen, Wei Wang
  • Patent number: 10824573
    Abstract: Apparatuses and methods related to implementing refresh and access modes for memory. The refresh and access modes can be used to configure a portion of memory. The portions of memory can correspond to protected regions of memory. The refresh and access modes can influence the security level of data stored in the protected regions of memory.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Nathaniel J. Meier
  • Patent number: 10825504
    Abstract: A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a corresponding one of the plurality of memory cells MC; and a control circuit that intermittently monitors accesses to the plurality of word lines WL, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines WL in a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the Row Hammer problem, etc. can be taken.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Yuan He
  • Patent number: 10818338
    Abstract: Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: George B. Raad, Jonathan S. Parry, James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10818335
    Abstract: A memory storage apparatus having a plurality of operating modes is provided. The memory storage apparatus includes a memory control circuit and a memory cell array circuit. The memory control circuit controls the memory storage apparatus to operate in one of the operating modes. The memory control circuit controls the memory storage apparatus to operate in a first operating mode and controls the memory storage apparatus to switch from the first operating mode to a second operating mode to refresh storage data of the memory cell array circuit. The memory storage apparatus operates in a third operating mode to refresh storage data in the memory storage apparatus. An operating voltage of the memory storage apparatus operating in the second operating mode is smaller than an operating voltage of the memory storage apparatus operating in the third operating mode.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: October 27, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Che-Min Lin, Hsi-Yuan Wang
  • Patent number: 10811093
    Abstract: In an embodiment, a method of accessing logic data stored in a differential memory using single-ended mode includes: storing second logic data in an auxiliary memory module of the differential memory by copying first logic data stored in a first main memory module of the differential memory into the auxiliary memory module; refreshing the first logic data; receiving a request for reading the first logic data; when refreshing the first logic data, fetching the second logic data when refreshing the first logic data in response to the request for reading the first logic data; and when not refreshing the first logic data, fetching the first logic data in response to the request for reading the first logic data.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: October 20, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Fabio Enrico Carlo Disegni
  • Patent number: 10810145
    Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Frank F. Ross, Randall J. Rooney
  • Patent number: 10811074
    Abstract: A storage device may include a monitoring module which monitors a characteristic degradation rate of a plurality of blocks included in a cell array of a nonvolatile memory; a group management module which designates the plurality of blocks as one or more groups, on the basis of a monitoring result of the monitoring module; a refresh period management module which determines refresh periods for each of the one or more groups; and a processor which performs refresh on the one or more groups in accordance with the determined refresh periods.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Won Jung, Shin Ho Oh, Dong Hoon Ham
  • Patent number: 10811078
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
  • Patent number: 10802977
    Abstract: A processing system tracks counts of accesses to memory pages using a set of counters located at the memory module that stores the pages, wherein the counts are adjusted at least in part based on refreshes of the memory pages. This approach allows a processing system to efficiently maintain the counts with relatively small counters and with relatively low overhead. Furthermore, the rate at which the counters are adjusted, relative to the page refreshes, is adjustable, so that the access counts are useful for a wide variety of application types.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 13, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Georgios Mappouras, Amin Farmahini Farahani, Nuwan Jayasena
  • Patent number: 10802758
    Abstract: There are provided a memory controller and a memory system having the same. The memory controller includes: a temperature monitor device configured to count values that vary according to operation statuses of memory devices; a status check device configured to output status information of the memory devices based on the count values; and a scheduler configured to store the status information according to arrangements of the memory devices, and output the status information in response to a request received from a host.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventor: Young Jae Jin
  • Patent number: 10796746
    Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner
  • Patent number: 10796750
    Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Akhilesh Patil, Eric D. Hunt-Schroeder
  • Patent number: 10796774
    Abstract: A flash memory controller refreshes memory blocks in a flash memory device by setting different refresh cycles for individual memory blocks in the flash memory device. The flash memory controller records a number of erase operations performed on each memory block of the flash memory device. Upon detecting that a bit error rate of a memory block is greater than a preset threshold, the flash memory controller determines a refresh cycle for the memory block based on recorded number of erase operations performed on the memory block, and then refreshes the memory block according to the refresh cycle.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 6, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Liang Shi, Yejia Di, Hsing Mean Sha, Yuangang Wang, Dongfang Shan
  • Patent number: 10790004
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating a refresh address locally at a memory bank. The memory bank may include or be associated with a bank logic circuit that latches an initial refresh address from a global row address bus for a first pump of a refresh operation. The bank logic circuit then updates the latched refresh address received to generate a new refresh address for a second pump of the refresh operation. A memory device may include multiple memory banks that share the global row address bus.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kiyotake Sakurai, Takuya Nakanishi, Shinji Bessho
  • Patent number: 10790029
    Abstract: Apparatus and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Luyen Vu, Kalyan C. Kavalipurau, Jae-Kwan Park, Erwin E. Yu
  • Patent number: 10777282
    Abstract: A memory controller to control a memory device includes an Error Checking and Correcting (ECC) engine to perform error detection on data read from the memory device and a data operation manager. The data operation manager is to control a first rewrite operation of the memory device on selected memory cells to compensate for a drift in a distribution of the selected memory cells, based on a result of a test read operation of the memory device on test cells, determine a distribution adjustment degree based on a result of a normal read operation, as an ECC decoding operation corresponding to the normal read operation of the memory device is successfully performed by using the ECC engine, and control a second rewrite operation of the memory device based on the determined distribution adjustment degree.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Chu Oh, Young-geun Lee
  • Patent number: 10770135
    Abstract: A memory macro includes a first input terminal, a first input pin, a first memory cell array, a second memory cell array, a first set of driver circuits, a second set of driver circuits and a logic circuit. The first input pin is configured to receive a first signal indicating an operational mode of the memory macro. The first set of driver circuits is coupled to the first memory cell array. The second set of driver circuits is coupled to the second memory cell array. The logic circuit has a first terminal coupled to the first input pin and is configured to receive the first signal. The logic circuit is coupled to the first and second set of driver circuits, and is configured to generate a second signal and a third signal responsive to the first signal, and cause a change in the operational mode of the memory macro.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pankaj Aggarwal, Jui-Che Tsai, Ching-Wei Wu
  • Patent number: 10762930
    Abstract: A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: September 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyung Sik Won, Seung Han Oak, Jun Phyo Lee
  • Patent number: 10762931
    Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sanjeev Kumar Jain, Jaspal Singh Shah
  • Patent number: 10755762
    Abstract: A semiconductor device includes a counter configured to count a refresh signal and output a counting signal. The semiconductor device may include a mode control circuit configured to receive a first mode signal for controlling a refresh cycle and a second mode signal for constantly controlling a refresh cycle, in correspondence to error correction code information, configured to output an advanced refresh signal in which the refresh cycle is adjusted, by controlling the counting signal depending on the first mode signal, and configured to output a smart refresh signal which has a constant refresh cycle, in correspondence to the second mode signal. The semiconductor device may include a refresh control circuit configured to output a bank address for performing a refresh operation that is set in correspondence to the advanced refresh signal and the smart refresh signal, to a bank.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Yong Seop Kim
  • Patent number: 10741235
    Abstract: An apparatus is disclosed. The apparatus includes an address counter configured to provide a refresh address to a refresh circuit, wherein the address counter includes a plurality of counter cells coupled in series from a first counter cell to a last counter cell downstream of the first counter cell, wherein an output of each of the plurality of counter cells each correspond to an address bit of the refresh address, wherein the address bit of the refresh address provided by a later counter cell downstream of an earlier counter cell is a less significant bit of the refresh address than the address bit of the refresh address provided by the earlier counter cell.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Takaaki Nakamura, Kazuya Saso
  • Patent number: 10741263
    Abstract: Devices and techniques are disclosed herein to provide a high-voltage bias signal in a standby state of the storage system without exceeding a limited maximum standby current allowance of the storage system. The high-voltage bias signal can enable a string driver circuit in the standby state to couple a global word line to a local word line, to provide a bias to, or sink a voltage from, a pillar of a string of memory cells of the storage system in the standby state, such as to reduce read disturbances in the storage system.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo, Shigekazu Yamada
  • Patent number: 10733128
    Abstract: A processor includes, an engine that transmits a read command or the other command; and a command transfer unit that performs arbitration to select a command to be executed among the commands transmitted from the engines and outputs the command selected, wherein the command transfer unit that, in case that the read command is selected on the arbitration, brings a subsequent read command into the arbitration after a period represented an issue interval control value in relation to a data transfer length of the read command selected, the subsequent read command being transmitted from the engine which has transmitted the read command selected on the arbitration.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: August 4, 2020
    Assignee: NEC CORPORATION
    Inventor: Shin Kamiyamane
  • Patent number: 10734042
    Abstract: A semiconductor device includes an input/output (I/O) control signal generation circuit, a pipe circuit and an auto-pre-charge signal generation circuit. The I/O control signal generation circuit generates an input control signal, an output control signal and an internal output control signal. The pipe circuit latches an internal command/address signal based on the input control signal and outputs the latched internal command/address signal as a latch signal. The auto-pre-charge signal generation circuit generates an auto-pre-charge signal from the latch signal and the internal latch signal.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Myung Kyun Kwak, Seung Hun Lee
  • Patent number: 10726904
    Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: July 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jungwon Suh, Yanru Li, Michael Hawjing Lo, Dexter Tamio Chun
  • Patent number: 10726903
    Abstract: The present disclosure provides a row-determining circuit. The row-determining circuit includes a plurality of row latches and a target row generator connected to the plurality of row latches. The target row generator is configured to generate a plurality of target row records respectively for a plurality of banks and then send the plurality of target row records respectively to the plurality of row latches. The plurality of row latches are configured to generate a plurality of row address records based on the plurality of target row records.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: July 28, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Nung Yen, Yu-Hsiang Liu
  • Patent number: 10714150
    Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Joe M. Jeddeloh, Brent Keeth
  • Patent number: 10705757
    Abstract: There are provided a memory interface, a command queue controller configured to determine an execution order of normal commands and a suspend command; a command time controller configured to receive the normal commands, and output command and time information by providing a corresponding additional operation time to each of the normal commands; a command time manager configured to match the command and time information to each of the normal commands to be stored therein, and output an end signal; and an input/output interface configured to receive the normal commands and the suspend command, and transmit the normal commands and the suspend command to a memory device through a channel.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung Kwan Hong, Ik Sung Oh
  • Patent number: 10706910
    Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: July 7, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, Richard E. Perego, Craig E. Hampel
  • Patent number: 10698734
    Abstract: The present disclosure includes apparatuses and methods to determine timing of operations. An example method includes performing a first operation type that uses a shared resource in a memory device. The method includes applying a scheduling policy for timing of continued performance of the first operation type based upon receipt of a request to the memory device for performance of a second operation type that uses the shared resource.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Jeremiah J. Willcock
  • Patent number: 10692562
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: George B. Raad, Jonathan S. Parry, James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10691393
    Abstract: A processing circuit of a display panel, a display method and a display device are provided. The display panel is divided into a plurality of display regions. The processing circuit includes: a plurality of display control circuits corresponding to the plurality of display regions respectively; a sight line acquisition circuit configured to acquire a focused region of the display panel on which sight lines of human eyes are focused; and a control circuit configured to determine from the plurality of display regions a first display region overlapping the focused region and a second display region not overlapping the focused region, enable the display control circuit corresponding to the first display region to output first image data, and enable the display control circuit corresponding to the second display region to output second image data having a refresh rate smaller than the first image data.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: June 23, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tiankuo Shi, Xue Dong, Dong Chen, Xiaomang Zhang, Wei Sun, Lingyun Shi, Yan Li, Xiaochuan Chen, Shengji Yang
  • Patent number: 10692561
    Abstract: A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-soo Jang, Eunsung Seo, Seungjun Bae
  • Patent number: 10685696
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jason M. Brown, Daniel B. Penney